CN110890415A - 一种复合内钝化膜单沟槽结构高可靠性整流器件应用芯片 - Google Patents
一种复合内钝化膜单沟槽结构高可靠性整流器件应用芯片 Download PDFInfo
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Abstract
本发明提供一种复合内钝化膜单沟槽结构高可靠性整流器件应用芯片,芯片台面的采用单沟槽设计,沟槽内壁表面采用复合内钝化层结构,复合内钝化层由多晶硅膜以及底层高纯度纳米级氧化膜、氮化硅膜、玻璃组成。芯片由中间层单晶半导体本体、上层为P型硼结区和下层为N型磷结区的芯片体、台面、上电极金属层、下电极金属层。本发明解决了芯片沟槽采用玻璃作为钝化层的保护膜的可靠性差和高温特性差的问题。
Description
技术领域
本发明涉及一种半导体器件,更具体地说涉及一种复合内钝膜单沟槽高可靠性整流器件应用芯片。
背景技术
在现有技术中,半导体整流器件应用芯片沟槽内壁表面采用钝化结构,保护芯片P/N结不受外界水汽和杂质的干扰和影响,目前在行业中通常采用简单的、单层的玻璃层,作为半导体整流器件应用芯片的沟槽内壁表面的钝化结构物质,其虽然工艺简单、成本较低,玻璃热膨胀系数与硅衬底匹配性差,玻璃在使用或芯片工作过程中易破碎,其固定和阻止有害杂质能力不佳,如钠离子等对器件表面的沾污能力,封装后的热稳定性和可靠性较差。随着成品封装对半导体整流器件可靠性的不断需求,需要有一种便于实施批量生产、批次一致性好、成本适中、可靠性高的沟槽内壁表面钝化结构。对于钝化层的基本要求是:能在封装温度变化过程后、且长期有效地阻止有害杂质对器件表面的沾污;热膨胀系数与硅衬底匹配;膜的生长温度低;钝化膜的组份和厚度均匀性好;便于制成后续提供良好欧姆接触的金属层。国内复合内钝化膜均采用SIPOS(掺氧多晶硅)作为台面钝化保护膜结构,其仅能满足150度结温及以下的应用场合。在高温或高压环境下可靠性差,芯片反向漏电流上升,芯片失效比例高。
发明内容
本发明要解决的技术问题在于沟槽采用玻璃作为钝化层的保护膜的可靠性差和高温特性差的问题。
本发明提供一种复合内钝化膜单沟槽结构高可靠性整流器件应用芯片,本发明所述芯片的采用单沟槽设计,沟槽内壁表面采用复合内钝化层结构,复合内钝化层由多晶硅膜以及底层高纯度纳米级氧化膜、氮化硅膜、玻璃组成。
本发明所述芯片由中间层单晶半导体本体、上层为P型硼结区和下层为N型磷结区的芯片体、台面、上电极金属层、下电极金属层。
作为本发明单沟槽的更进一步的改进,沟槽侧面和上层台面的夹角≥120°设计。使复合钝化层在热胀冷缩的过程中在夹角位置不易断裂。
在硅片扩散完成形成P/N结单向导通后,在硅片两侧涂光刻胶,在需要开沟的区域曝光紫外光,放置在显影液和定影液中,去除开沟区域的光刻胶,使用电子级的氢氟酸对沟槽区域的硅进行蚀刻腐蚀,需要分3次完成蚀刻工序,第一次时间30±2MIN,第二次时间45±2MIN,第三次时间100±2MIN,最终使沟槽侧面和上层台面的夹角≥120°。
作为本发明沟槽内壁表面采用复合内钝化层结构,更进一步的改进是,复合内钝化层结构除了要求覆盖在沟槽侧壁外,还要求部分覆盖在上层台面的边缘区域,使对沟槽侧面更好的保护,提高芯片的稳定性和可靠性。
与现有技术相比,由于采用了本发明的硅整流器件的复合内钝化层结构,具有以下优点:本发明采用的氮化硅膜是惰性介质,介质特性优于直接采用玻璃的二氧化硅性质膜以及SIPOS(掺氧多晶硅)内钝化膜,抗钠能力强,热稳定性好,能明显提高器件的可靠性和稳定性。氮化硅膜还有着超高致密性、超强硬度、异常稳定的化学特性及优秀的离子与水汽阻挡能力,再敷盖上特殊的玻璃钝化材料,使击穿集中在硅材料体内,从而最大限度的提升了击穿的电压、降低了表面电场的影响。但氮化硅与单晶硅的结合能力和粘附能力较弱,本发明引进一层纳米级高纯度氧化层以及多晶硅,来增加氮化硅的粘附性能和牢度。高纯度氧化层位于多晶硅底层,不但提供多晶硅的优选排序,而且提供多晶硅的黏附层。而多晶硅在其晶核长成晶面时因取向不同,所以在形貌上形成“毛面”,有助于增加氮化硅膜的结合和粘附力。
本发明使硅整流器件的击穿集中在硅材料体内,从而最大限度的提升了击穿的电压、降低了表面电场的影响。在器件处于反向偏置的状态下,P型面的负电荷等于N型面的正电荷。由于PN结台面处被腐蚀成斜坡状,使耗尽层在台面的表面被拉伸,从而明显地降低了表面电场的影响。当击穿产生时,击穿并不在器件表面而在其体内。高击穿电压、高传导性的优化组合结构正是采用这种结构将表面电场影响降到最低,结合选取低电阻率硅材料来实现的。此外,氮化硅钝化膜加上致密的超纯玻璃钝化层,这种多重钝化保护结构使器件绝对与外界环境隔绝,确保了器件的高耐压、化学稳定性、及其优秀的高温特性。再加上器件结构的合理设计,使得PN结击穿电压十分稳定,并能超过2600V。钝化后,器件的两面用真空镀镍膜或化学镀镍金技术,再经合金法处理,使得金属与硅表面产生良好的欧姆接触,从而确保了在器件封装前的高稳定性和高可靠性,适合在各领域应用。
附图说明:
图1为本发明实施的结构示意图。
100 单晶半导体本体
101 扩散或离子注入法形成的P型掺杂层或N型掺杂层。
102 台面结构区域的多晶硅薄膜以及其下为纳米级高纯度氧化层
103 台面结构区域的氮化硅薄膜
104 特种玻璃材质的玻璃
105 金属层,位于两侧单沟槽台面复合多层内钝化膜的中间
106 金属层,位于另一侧电极引出端
107 台面造型
108 扩散或离子注入法形成的N型掺杂层或P型掺杂层(与101相对应。若101为N型掺杂层,则108为P型掺杂层;若101为P型掺杂层,则108为N型掺杂层)
具体实施方式:
下面结合附图对具体实施方式作详细说明:
109 图1给出了本发明实施例的结构示意图。图中,一种硅整流器件的复合内钝化层结构,包括有:中间层100单晶半导体本体、上层101为P型掺杂层或N型掺杂层的芯片体、下层108为N型掺杂层或P型掺杂层的芯片体(具体说明见上面108)、台面107、上电极金属层105、下电极金属层106,台面结构区域的多晶硅薄膜以及其下为纳米级高纯度氧化层102、台面结构区域的氮化硅薄膜103、特种玻璃材质的玻璃钝化层104;所述台面结构区域的多晶硅薄膜以及其下为纳米级高纯度氧化层102、台面结构区域的氮化硅薄膜103、特种玻璃材质的玻璃钝化层104组成的复合多层依次覆盖在芯片体台面107上,所述上电极金属105位于两侧单沟槽台面复合多层内钝化膜的中间,下电极金属层106位于芯片体复合多层钝化区的对侧。
上述发明例并不构成对本发明的限制,凡采用等同替换或等效变换的形式所获得的技术方案,均落在本发明的保护范围之内。
Claims (5)
1.一种复合内钝化膜单沟槽结构高可靠性整流器件应用芯片,芯片的采用单沟槽设计,沟槽内壁表面采用复合内钝化层结构,复合内钝化层由多晶硅膜以及底层高纯度纳米级氧化膜、氮化硅膜、玻璃组成。
2.根据权利要求1所述芯片,其特征在于:由中间层单晶半导体本体、上层为P型硼结区和下层为N型磷结区的芯片体、台面、上电极金属层、下电极金属层。
3.根据权利要求1所述的单沟槽设计,其特征在于:沟槽侧面和上层台面的夹角≥120°设计。
4.根据权利要求1和权利要求3所述的单沟槽设计,其特征在于:在硅片扩散完成形成P/N结单向导通后,在硅片两侧涂光刻胶,在需要开沟的区域曝光紫外光,放置在显影液和定影液中,去除开沟区域的光刻胶,使用电子级的氢氟酸对沟槽区域的硅进行蚀刻腐蚀,需要分3次完成蚀刻工序,第一次时间30±2MIN,第二次时间45±2MIN,第三次时间100±2MIN,最终使沟槽侧面和上层台面的夹角≥120°。
5.根据权利要求1所述芯片,其特征在于:本发明沟槽内壁表面采用复合内钝化层结构,复合内钝化层结构除了要求覆盖在沟槽侧壁外,部分覆盖在上层台面的边缘区域,使对沟槽侧面更好的保护,提高芯片的稳定性和可靠性。
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CN202662607U (zh) * | 2012-07-26 | 2013-01-09 | 黄山市七七七电子有限公司 | 具有单一角度台面造型的芯片 |
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CN115547856A (zh) * | 2022-10-20 | 2022-12-30 | 安徽钜芯半导体科技有限公司 | 一种高性能半导体整流芯片及其制备工艺 |
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