CN110828571A - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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CN110828571A
CN110828571A CN201910647082.1A CN201910647082A CN110828571A CN 110828571 A CN110828571 A CN 110828571A CN 201910647082 A CN201910647082 A CN 201910647082A CN 110828571 A CN110828571 A CN 110828571A
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jfet
gate
mosfet
semiconductor device
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CN110828571B (zh
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马丁·多梅杰
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Semiconductor Components Industries LLC
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Abstract

本发明公开了一种半导体器件及其制备方法，所述半导体器件包括源极区，所述源极区被配置为提供MOSFET的MOSFET源极的至少一部分以及JFET的JFET源极的至少一部分。所述半导体器件包括JFET沟道区，所述JFET沟道区与所述源极区和所述MOSFET的MOSFET沟道区串联，并且设置在第一JFET栅极和第二JFET栅极之间。所述半导体器件包括JFET漏极，所述JFET漏极至少部分地设置在所述MOSFET的栅极的栅极绝缘体和所述JFET沟道区的至少一部分之间，并且与所述第一JFET栅极和所述第二JFET栅极电接触。该类型的半导体器件的各种示例性实施方式为SiC功率MOSFET提供改善的短路能力和耐久性，对RDS‑ON的影响最小。

Description

半导体器件及其制备方法
技术领域
本说明书涉及碳化硅半导体器件及其制备方法。
背景技术
碳化硅(SiC)半导体器件(诸如SiC MOSFET)具有多个有利特征，例如，与传统的硅基器件相比。例如，SiC MOSFET非常适合于高功率应用。SiCMOSFET能够处理高电压和高操作温度。另外，SiC MOSFET具有低漏极到源极导通电阻(RDS-ON)(当设计为具有短沟道区时)和快速开关以及低功率损耗，从而实现高效操作。
然而，一些此类有利特征也与潜在的困难或挑战相关联。例如，在短路操作期间，上面提到的短沟道区可能导致电流上升到非常高的电平(例如，对于1200V SiC MOSFET，VDS＝600-800V)。另外，较低的RDS-ON虽然在正常操作期间具有优势，但导致较差的短路耐久性。例如，短路电流密度在此类情况下增加，这导致功率密度增加和短路故障时间减少。
发明内容
根据一个方面，半导体器件包括源极区，该源极区被配置为提供MOSFET的MOSFET源极的至少一部分以及JFET的JFET源极的至少一部分。半导体器件包括JFET沟道区，该JFET沟道区与源极区和MOSFET的MOSFET沟道区串联，并且设置在第一JFET栅极和第二JFET栅极之间。半导体器件包括JFET漏极，该JFET漏极至少部分地设置在MOSFET的栅极的栅极绝缘体和JFET沟道区的至少一部分之间，并且与第一JFET栅极和第二JFET栅极电接触。
根据另一方面，半导体器件包括MOSFET和JFET，JFET与MOSFET的MOSFET沟道区串联，JFET具有第一JFET栅极和第二JFET栅极，第一JFET栅极和第二JFET栅极均短接到JFET的JFET源极，其中，第一JFET栅极设置在半导体器件的表面和JFET的JFET沟道区之间，并且JFET的JFET漏极设置在第一JFET栅极和MOSFET沟道区之间。
根据又一方面，制备半导体器件的方法包括：在第二导电类型的外延层中形成第一导电类型的阱；在阱内形成JFET沟道区，JFET沟道区具有第二导电类型；在JFET沟道区上形成第一JFET栅极，第一JFET栅极具有第一导电类型；形成JFET源极区和JFET漏极区，JFET源极区和JFET漏极区具有第二导电类型，第一JFET栅极被设置在JFET源极区和JFET漏极区之间；在JFET源极区和阱之间形成电触点，以提供阱的至少一部分作为JFET的电连接到JFET源极区的第二JFET栅极；形成MOSFET的MOSFET源极触点，MOSFET源极触点电连接到JFET源极和第一JFET栅极，并且通过电触点电连接到第二JFET栅极；以及形成MOSFET的MOSFET栅极，MOSFET栅极与JFET漏极、阱和外延层至少部分地交叠。
一个或多个实施方式的细节在随附附图和以下描述中阐明。其他特征将从说明书和附图中以及从权利要求书中显而易见。
附图说明
图1是SiC功率金属氧化物半导体场效应晶体管(MOSFET)的框图，该MOSFET具有串联连接的结型栅场效应晶体管(JFET)，该JFET具有短接到其源极区的双面栅极以改善短路性能。
图2是图1的实施方式的附加示例性特征的框图，示出了示例性导电类型。
图3是示出图2的示例性电流/电压特性的曲线图。
图4示出了可用于获得图1和图2的示例性MOSFET结构或类似MOSFET结构的示例性处理步骤。
图5示出了图4的处理的另外的示例性处理步骤。
图6示出了图4和图5的处理的另外的示例性处理步骤。
图7示出了图4-图6的处理的另外的示例性处理步骤。
图8示出了图4-图7的处理的另外的示例性处理步骤。
图9是示出了图4-图8的处理的示例性操作的流程图。
图10示出了用于图1-图2的MOSFET结构的示例性实施方式的模拟/测试的器件。
图11是示出了使用图10的示例获得的结果的第一曲线图。
图12是示出了使用图10的示例获得的结果的第二曲线图。
具体实施方式
在SiC MOSFET的正常操作期间，可能发生不期望的短路电流。例如，SiCMOSFET的接通的错误时可发生并导致短路电流。可以使用短路保护机制，但是SiC MOSFET必须能够承受不期望的短路电流，直到可以激活此类机制。
尽管可以通过例如增加所使用的沟道长度或通过降低管芯上的沟道密度来改善SiC MOSFET的短路性能概况，但是此类增加也导致在正常操作期间的缺点，诸如较高的RDS-ON、较高的导通状态功率损耗、较高的成本和较慢的开关。
该文献描述了SiC功率MOSFET的各种示例性实施方式，该MOSFET具有改善的短路能力和耐久性，对RDS-ON的影响最小。如下详细所述，各种示例性实施方式实现短路耐受能力和RDS-ON之间的改善折衷，包括提供短路电流饱和(作为降低沟道密度，或仅增加沟道长度或串联电阻的替代或除此之外)。
更具体地讲，各种示例性实施方式通过例如添加JFET来提供上述和附加特征和优势，该JFET具有短接到其源极的双面栅极，与MOSFET沟道串联。如下详细所述，具有上面提到的包括的JFET的功率SiC MOSFET的各种示例性实施方式提供了短路性能和RDS-ON之间的改善折衷，而在一些实施方式中，除了在常规SiC功率MOSFET制造技术中使用的步骤之外，仅需要单个附加掩蔽注入步骤。此外，短路性能得到改善，对SiC功率MOSFET的电特性影响很小或没有影响，同时提供调谐功率MOSFET的能力，以满足有关短路性能和RDS-ON的广泛要求。
具体地讲，包括的JFET的双面栅极提供对表面条件(例如，在处理期间可能发生的界面电荷和SiC消耗，诸如在氧化或干蚀刻期间)的灵敏度的降低。出于这些和其他原因，所描述的实施方式提供稳定、可调且耐用的方法以获得SiC功率MOSFET的改善短路性能。
图1是SiC功率MOSFET 100的框图，该MOSFET具有JFET(114、116、118、120、122，如下所述)，该JFET具有双面栅极(118、120)以改善短路性能。在图1的示例中，SiC功率MOSFET100是竖直功率MOSFET器件。这样的竖直功率MOSFET器件在其作为功率晶体管的正常容量中提供各种功能和特征的方式的细节在本文中通常不再详细描述，除非在理解MOSFET 100的短路性能和相关方面可能是必要的或有帮助的。
在图1中，MOSFET 100被示为包括电连接到漏极区104的漏极触点102。漂移区106(在一些上下文中也称为外延层)为MOSFET 100的电流提供电流路径的一部分。在正常操作期间，施加在设置在下面的栅极氧化物(绝缘体)110上的栅极108处的电压使电流124流过源极触点112和对应的源极区114，流入与源极区114串联的区域116中(并且为上面提到的JFET结构提供沟道)，并且流过JFET漏极区122到达MOSFET沟道区126。
因此，如图所示，所提到的JFET结构包括第一栅极118和第二栅极120，以及漏极122。第二JFET栅极120电连接到源极区114和源极触点112，并且当电流124行进通过漂移区106时以及当电流124在漏极104/漏极触点102和源极区114/源极触点112之间流动时，部分地包括由电流124穿过的MOSFET沟道区126。
一般来讲，并且如下详细所述，图1的MOSFET 100由此示出JFET结构(114、116、118、120、122)，该JFET结构具有第一栅极118，该第一栅极电短接到其源极114，并且与MOSFET沟道区126串联。另外，在JFET沟道116内仔细控制的掺杂水平引起沿着JFET沟道116的横向电压降，并且导致JFET沟道116在高电流下(例如，在短路情况下)的夹断。这种夹断导致电流饱和并减小短路电流，如下所述和所示。
图2是图1的实施方式的附加示例性特征的框图，示出了示例性导电类型。相对于图3，以及图4-图8，各种替代实施方式可以使所示的导电类型相反。
在图2中，切口202示出JFET结构(114、116、118、120、122)的JFET区(118，以及116、120的部分)以及JFET区202的扩展视图202a。如图所示，图2示出用于源极区114和JFET漏极区122的N+掺杂，用于第一JFET栅极118的P+掺杂，用于JFET沟道116的N掺杂，用于第二JFET栅极120的P掺杂(具有连接区部分121a中的P+掺杂，以及连接区部分121b中的P掺杂)，以及用于漂移区106的N-掺杂。另外在图2中，栅极氧化物(绝缘体)110被示为SiO2。当然，上述导电类型仅仅是为了举例，并且在其他实施方式中可以反转。
如上所述，图1和图2的实施方式的结构和操作是高度可调的。例如，扩展的JFET区202a被示为包括n掺杂浓度ND，并且具有JFET沟道的宽度WJFET，具有JFET沟道区的长度L。通过选择这些参数ND、WJFET和L的绝对值和相对值，可以控制短路电流的夹断和饱和电平，如下例如相对于图3所述和所示。
在图2中，可以观察到，MOSFET 100可被构造有源极注入区114、116，其在顶部表面附近具有高峰值(即，区域114中的N+)，具有下部平台(N)，该下部平台具有本文所述的精确控制的掺杂分布。可以相对于沟道区116的掺杂水平N独立地控制N+区114的掺杂水平。
另外，可以提供具有比N+源极114更高掺杂的附加P+注入物118，以产生用于本文所述的JFET箍缩电阻的p栅极的第一侧或顶侧，其中源极触点108还连接到P+区118。如可以观察到的，第一栅极118因此以对JFET沟道116的结构和功能的任何改变或破坏的物理和电屏障的方式提供保护(例如，否则可能由于工艺引起的表面条件而发生，诸如界面电荷、或者通过氧化或干蚀刻消耗的SiC)。
在不同环境中的操作期间，MOSFET 100可能需要或受益于本文所述的各种特性的不同程度。例如，一些操作环境可能非常容易受到频繁和/或大的短路电流的影响。其他环境可能需要相对较快的开关速度。因此，一些操作环境可受益于相对较大的导通电阻RDSON和较高程度的短路保护，而其他操作环境可受益于较低的RDSON和相关联的较快的开关速度。
MOSFET 100提供调谐结构和操作特性并实现刚刚提到的调谐类型的能力。例如，当MOSFET处于导通状态时，图2的区域116a的掺杂ND可被选择为提供期望电平的附加串联电阻，但是在指定的高电流(例如，短路)下夹断。
为了提供这样的调谐，n掺杂浓度ND、JFET沟道的宽度WJFET和JFET沟道区的长度L被选择和配置为使夹断在指定(短路)电流下发生。例如，对于给定的L值，可以控制作为ND·WJFET的乘积的参数，其在本文中可以称为JFET沟道剂量。类似操作特性可通过保持(ND·WJFET)/L的恒定比率由不同构造(例如，对于ND、WJFET或L中的一个或多个的改变)获得。在其他实施方式中，ND不必是恒定的，诸如其中跨沟道区的n掺杂的积分具有与(ND·WJFET)相同的值的掺杂分布。
在一些示例性实施方式中，上面提到的参数的值可包括JFET沟道长度为L＝1μm，ND＝1.2·1018cm-3，并且WJFET＝100nm。更一般地，沟道长度L可以方便地保持为短，例如为约0.5μm至2.5μm。如刚刚提到的，可以通过使用沟道剂量与所选沟道长度的比率来获得用于短路性能的期望操作特性。
可以部分地控制N区116a的夹断，例如通过注入。例如，在118、116和120中可能存在竖直变化的掺杂浓度，其中掺杂分布由注入能量和剂量控制。例如，栅极108和漏极104之间的线可用于限定竖直或深度方向。
图3是示出图1和图2的MOSFET的示例性电流/电压特性的曲线图。如图3所示，并且如刚刚描述的，当JFET的漏极电压VD增加时，漏极电流ID也增加，直到达到饱和电压VDSAT。在该电压下，JFET电流ID也达到饱和值IDSAT。通过达到并保持饱和值IDSAT，提供短路保护，并且为要实现的故障保护机制提供时间。使用与SiC MOSFET沟道串联的JFET区202的优点在于JFET具有低导通电阻，增加了MOSFET的总RDSon，但其具有夹断电流，这将限制MOSFET的最大短路电流，如图3所示。常规SiC MOSFET将不具有这种饱和行为，这导致显著更高的短路电流和降低的短路能力。
图4-图8示出了可用于获得图1和图2的示例性MOSFET结构或类似MOSFET结构的示例性处理步骤。图9是示出了图4-图8的处理的示例性操作的流程图。在以下描述中，对图4-图8的讨论还参考图9的特定对应操作。
在图4中，外延层402形成为轻掺杂的N-层，对应于图1和图2的漂移区106，并且使用掩模408(902)执行Al注入404以形成P阱406。例如，可以在600℃下实现热注入。
在图5中，使用掩模508(904)执行磷注入502以形成JFET沟道504。例如，可以在JFET沟道深度处执行中间源极掺杂(例如，1e18cm-3范围)。再次使用掩模508(906)，进一步注入502用于形成N+区506。所描述和示出的注入502使用例如SiO2掩模508，因为SiO2的对应沉积和回蚀刻可用于形成用于自对准的准确MOSFET沟道(长度)定义的间隔物。此外，如上所述，区域504的ND浓度可被注入到合适的深度，以获得期望的RDSON/短路特性。
在图6中，P+注入SiO2掩膜602用于执行Al P+注入，并且由此使表面与P阱区(908)接触。在图7中，P箍缩SiO2注入掩膜702用于执行P箍缩注入，并且由此产生顶部(第一)p-栅极区706(910)。在其他实施方式中，可以将P箍缩注入物与P+掩膜结合。
在图8中，示出了具有包括的JFET的经处理的MOSFET的最终版本，此处具有对应于图1和图2的那些符号和附图标记的符号和附图标记。如图9的流程图所示和所提到的，可执行高温退火(例如，在1600-1700℃下)以活化各种掺杂物原子(912)。在该步骤期间，SiC表面可被碳盖覆盖。最终，在图9中，在高温退火后可以执行栅极氧化与后氧化退火、多晶硅沉积和图案化、以及欧姆接触形成(914)。
图10示出了用于图1-图2的MOSFET结构的示例性实施方式的模拟/测试的器件，其结果示于图11-图12的曲线图中。在图10中，源极区1002与JFET沟道(箍缩电阻)1004串联，该JFET沟道形成在第一(顶部)栅极1006和第二(底部)栅极1008之间。漏极区1010完成JFET结构，同时MOSFET沟道区1012形成在JFET漏极1010和MOSFET漏极区1014之间。
相对于图10，对1200V SiC MOSFET进行了最高至VDS＝600V的ID-VDS特性的器件模拟。改变箍缩电阻1004中的掺杂浓度，以便调谐各种实施方式的特定导通电阻和短路电流密度。
图11示出了在VDS＝600V时电流密度的强烈降低，由于所描述的箍缩电阻，并且包括使用双栅极JFET结构，在RDSon中具有非常小的损失。由于本文所述的箍缩电阻，ID-VDS特性显示出真正的饱和特性。SiC MOSFET特别适合于使用与源极串联的箍缩电阻，因为例如随着电流增加在VGS上提供负反馈，并且RDSon对SiC MOSFET中的VGS具有显著依赖性(由于例如SiC/SiO2界面陷阱)。
图12示出与常规SiC MOSFET(No_Pinch_IDsat)相比，并且对于具有单面栅极(Single_IDsat)的串联连接的JFET，在600V下的模拟短路电流密度与本文所述实施方式的特定导通电阻(Double_IDsat)。通过改变JFET沟道区中的掺杂浓度ND来生成用于Double_IDsat以及用于单面栅极的数据点，并且通过降低管芯上的沟道密度来生成用于常规SiCMOSFET的数据点。从该比较中可以清楚地看出，使用与SiC MOSFET沟道串联的双栅极JFET显著降低短路电流密度，代价是RDSon适度增加。通过仔细调谐JFET沟道区中的ND，可以为不同应用选择RDSon和短路能力之间的合适折衷。可使用单面栅极JFET来实现类似的效果，但RDSon和短路电流密度之间的折衷显著更差。对于单面栅极JFET，预计批量制造也将更加困难，因为该概念对于表面电荷、通过氧化消耗SiC并过蚀刻到SiC中将是敏感的，而本发明不受这些限制，因为JFET沟道掩埋在高度掺杂的P+区下方。
如上文相对于图1-图12所示和所述，与改善的短路能力相结合的低RDSon用高度可调的方法实现，该方法在这两个方面之间提供了期望的折衷，所有这些方面都将继续变得重要，因为开发出具有甚至更低RDSon值的SiC MOSFET(例如，使用减小的单元间距、较低的寄生JFET电阻和可能较高的沟道迁移率)。所描述的特征用于许多重要的应用中，诸如电机驱动系统，包括电动车辆和混合电动车辆中的动力传动系统。
在一些实施方式中，如本文所述的半导体器件对于值L可具有JFET沟道剂量ND·WJFET，其被配置为使夹断在指定的短路电流下发生。在一些实施方式中，如本文所述的半导体器件可具有(ND·WJFET)/L的比率，其被配置为使夹断在指定的短路电流下发生。在一些实施方式中，如本文所述的半导体器件可包括MOSFET，该MOSFET是竖直功率碳化硅(SiC)MOSFET。在一些实施方式中，如本文所述的半导体器件可包括源极区，该源极区被配置为提供MOSFET的MOSFET源极的至少一部分以及JFET的JFET源极的至少一部分。在一些实施方式中，如本文所述的半导体器件可包括JFET漏极，该JFET漏极至少部分地设置在半导体器件的表面处。在一些实施方式中，制备如本文所述的半导体器件的方法可包括形成JFET沟道区，该JFET沟道区具有沟道宽度WJFET、沟道长度L和掺杂分布，其被选择为在MOSFET的指定短路电流下提供JFET沟道区的夹断。
应当理解，在前面的描述中，当元件诸如层、区域、衬底或部件被提及在另一个元件上，连接到另一个元件，电连接到另一个元件，耦接到另一个元件，或电耦接到另一个元件上时，该元件可直接在另一个元件上，连接或耦接到另一个元件上，或者可以存在一个或多个中间元件。相反，当元件被提及直接在另一个元件或层上、直接连接到另一个元件或层、或直接耦接到另一个元件或层时，不存在中间元件或层。虽然在整个详细描述中可能不会通篇使用术语直接在…上、直接连接到…、或直接耦接到…，但是被示为直接在元件上、直接连接或直接耦接的元件能以此类方式提及。本申请的权利要求书(如果存在的话)可被修订以叙述在说明书中描述或者在附图中示出的示例性关系。
如在说明书和权利要求书中所使用的，除非根据上下文明确地指出特定情况，否则单数形式可包括复数形式。除了附图中所示的取向之外，空间相对术语(例如，在…上方、在…上面、在…之上、在…下方、在…下面、在…之下、在…之以下等等)旨在涵盖器件在使用或操作中的不同取向。在一些实施方式中，在…上面和在…下面的相对术语可分别包括竖直地在…上面和竖直地在…下面。在一些实施方式中，术语邻近能包括横向邻近或水平邻近。
一些实施方式可使用各种半导体处理和/或封装技术来实现。一些实施方式可使用与半导体衬底相关联的各种类型的半导体处理技术来实现，该半导体衬底包括但不限于，例如硅(Si)、砷化镓(GaAs)、氮化镓(GaN)、碳化硅(SiC)等。
虽然所描述的实施方式的某些特征已经如本文所述进行了说明，但是本领域技术人员现在将想到许多修改形式、替代形式、变化形式和等同形式。因此，应当理解，所附权利要求书旨在涵盖落入实施方式的范围内的所有此类修改形式和变化形式。应当理解，这些修改形式和变化形式仅仅以示例的方式呈现，而不是限制，并且可以进行形式和细节上的各种改变。除了相互排斥的组合以外，本文所述的装置和/或方法的任何部分可以任意组合进行组合。本文所述的实施方式能包括所描述的不同实施方式的功能、部件和/或特征的各种组合和/或子组合。

Claims (13)

1.一种半导体器件，其特征在于，包括：
源极区，所述源极区被配置为提供金属氧化物半导体场效应晶体管MOSFET的MOSFET源极的至少一部分以及结型栅场效应晶体管JFET的JFET源极的至少一部分；
JFET沟道区，所述JFET沟道区与所述源极区和所述MOSFET的MOSFET沟道区串联，并且设置在第一JFET栅极和第二JFET栅极之间；和
JFET漏极，所述JFET漏极至少部分地设置在所述MOSFET的栅极的栅极绝缘体和所述JFET沟道区的至少一部分之间，并且与所述第一JFET栅极和所述第二JFET栅极电接触。
2.根据权利要求1所述的半导体器件，其中，所述JFET沟道区在所述MOSFET的短路事件期间提供所述MOSFET的短路电流的夹断，并且其中，在所述JFET沟道中，掺杂浓度、宽度WJFET和长度L被配置为使所述夹断在指定的短路电流下发生。
3.根据权利要求1所述的半导体器件，其中，所述第一JFET栅极和所述第二JFET栅极电连接到所述源极区。
4.根据权利要求1所述的半导体器件，其中，所述第一JFET栅极设置在所述半导体器件的表面和所述JFET沟道区的至少一部分之间。
5.根据权利要求1所述的半导体器件，其中，所述JFET漏极至少部分地设置在所述半导体器件的表面处并且在所述第一JFET栅极和所述MOSFET沟道区之间。
6.根据权利要求1所述的半导体器件，其中，所述源极区的源极触点与所述源极区、所述第一JFET栅极和所述第二JFET栅极电接触。
7.一种半导体器件，其特征在于，包括：
金属氧化物半导体场效应晶体管MOSFET；和
结型栅场效应晶体管JFET，所述JFET与所述MOSFET的MOSFET沟道区串联，所述JFET具有第一JFET栅极和第二JFET栅极，所述第一JFET栅极和所述第二JFET栅极均短接到所述JFET的JFET源极，其中，所述第一JFET栅极设置在所述半导体器件的表面和所述JFET的JFET沟道区之间，并且所述JFET的JFET漏极设置在所述第一JFET栅极和所述MOSFET沟道区之间。
8.根据权利要求7所述的半导体器件，其中，所述JFET沟道区在所述MOSFET的短路事件期间提供所述MOSFET的短路电流的夹断。
9.根据权利要求7所述的半导体器件，其中，在所述JFET沟道区中，掺杂浓度、宽度WJFET和长度L被配置为使所述夹断在指定的短路电流下发生。
10.根据权利要求7所述的半导体器件，其中，所述JFET的漏极电流IDJFET在所述JFET的饱和漏极电压VDSAT下达到饱和电流IDSAT。
11.一种制备半导体器件的方法，其特征在于，所述方法包括：
在第二导电类型的外延层中形成第一导电类型的阱；
在所述阱内形成结型栅场效应晶体管JFET沟道区，所述JFET沟道区具有所述第二导电类型；
在所述JFET沟道区上形成第一JFET栅极，所述第一JFET栅极具有所述第一导电类型；
形成JFET源极区和JFET漏极区，所述JFET源极区和所述JFET漏极区具有所述第二导电类型，所述第一JFET栅极被设置在所述JFET源极区和所述JFET漏极区之间；
在所述JFET源极区和所述阱之间形成电触点，以提供所述阱的至少一部分作为所述JFET的电连接到所述JFET源极区的第二JFET栅极；
形成金属氧化物半导体场效应晶体管MOSFET的MOSFET源极触点，所述MOSFET源极触点电连接到所述JFET源极和所述第一JFET栅极，并且通过所述电触点电连接到所述第二JFET栅极；以及
形成所述MOSFET的MOSFET栅极，所述MOSFET栅极与所述JFET漏极、所述阱和所述外延层至少部分地交叠。
12.根据权利要求11所述的方法，其中，形成所述第一JFET栅极包括形成设置在所述JFET沟道区与所述半导体器件的表面之间的所述第一JFET栅极。
13.根据权利要求11所述的方法，其中，形成所述JFET沟道区包括用沿竖直方向变化的所述第二导电类型的掺杂分布来掺杂所述JFET沟道区。
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