CN110660854A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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Publication number
CN110660854A
CN110660854A CN201910126403.3A CN201910126403A CN110660854A CN 110660854 A CN110660854 A CN 110660854A CN 201910126403 A CN201910126403 A CN 201910126403A CN 110660854 A CN110660854 A CN 110660854A
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China
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layer
etch
gate
opening
gate structure
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林志昌
吴伟豪
余佳霓
苏焕杰
徐廷鋐
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体装置的制造方法，包括在半导体元件上方形成遮罩层，其中半导体元件包含：栅极结构；第一层，设置于栅极结构上方；以及层间介电质，设置于第一层的侧壁上，且其中遮罩层定义开口暴露出第一层的一部分和层间介电质的一部分；进行第一蚀刻工艺，以通过开口蚀刻第一层的一部分和层间介电质的一部分；在进行第一蚀刻工艺之后，在开口中形成一衬垫层；在形成衬垫层之后，进行第二蚀刻工艺，其中第二蚀刻工艺使开口向下延伸而穿过第一层和穿过栅极结构；以及在进行第二蚀刻工艺之后，以第二层填充开口。

Description

半导体装置的制造方法
技术领域
本公开实施例涉及半导体技术，且特别涉及半导体装置的制造方法。
背景技术
半导体集成电路(integrated circuit，IC)工业已经历了快速成长。在集成电路材料和设计上的技术进步产生了数代集成电路，每一代都比前一代具有更小且更复杂的电路。然而，这些进步增加了加工与制造集成电路的复杂性，且为了实现这些进步，需要在集成电路的加工和制造中进行相似的发展。在集成电路的发展史中，功能密度(即每一芯片区互连的装置数目)增加，同时几何尺寸(即制造过程中所产生的最小的组件)缩小。
缩小的几何尺寸导致半导体制造的挑战。举例来说，当几何尺寸持续缩小，较小的临界尺寸(critical dimensions，CD)和较高的深宽比可导致进行蚀刻工艺的困难。在一些情况中，蚀刻工艺可能无意或非刻意地蚀刻不应被蚀刻的过量的层。当此情况发生时，结果为降低装置效能或甚至装置失效。
因此，虽然现有的半导体装置及其制造方法通常已足够用于其预期目的，但是现有的半导体装置及其制造方法并非在各个方面都完全地令人满意。
发明内容
在一些实施例中，提供半导体装置的制造方法，此方法包含在半导体元件上方形成遮罩层，其中半导体元件包含：栅极结构；第一层，设置于栅极结构上方；以及层间介电质，设置于第一层的侧壁上，且其中遮罩层定义开口暴露出第一层的一部分和层间介电质的一部分；进行第一蚀刻工艺，以通过开口蚀刻第一层的一部分和层间介电质的一部分；在进行第一蚀刻工艺之后，在开口中形成一衬垫层；在形成衬垫层之后，进行第二蚀刻工艺，其中第二蚀刻工艺使开口向下延伸而穿过第一层和穿过栅极结构；以及在进行第二蚀刻工艺之后，以第二层填充开口。
在一些其他实施例中，提供半导体装置的制造方法，此方法包含形成半导体元件，半导体元件包含栅极结构，间隙壁位于栅极结构的侧壁上，第一层具有T形轮廓位于栅极结构上方，以及层间介电质位于第一层的侧壁上和间隙壁的侧壁上，其中间隙壁的上表面位于栅极结构的上表面上方；在半导体元件上方形成图案化遮罩层，图案化遮罩层定义开口暴露出第一层的一部分和层间介电质的一部分；对半导体元件进行第一蚀刻工艺，使开口向下延伸，其中第一蚀刻工艺移除第一层位于间隙壁的上表面上方的一部分；在进行第一蚀刻工艺之后，在开口中形成衬垫层；在形成衬垫层之后，进行第二蚀刻工艺以进一步使开口向下延伸而穿过第一层以及穿过栅极结构，进而将栅极结构分离为两个区段；以及在进行第二蚀刻工艺之后，在开口中形成电性绝缘材料。
在另外一些实施例中，提供半导体装置，半导体装置包含一层，此层包含鳍结构或介电沟槽隔离部件；第一栅极结构和第二栅极结构，设置于此层上方；间隙壁，设置于此层的侧壁上，其中间隙壁的上表面位于此层的上表面上方；衬垫，设置于间隙壁的上表面上方；以及电性绝缘材料，设置于此层上方以及第一栅极结构与第二栅极结构之间、间隙壁之间以及衬垫之间，其中电性绝缘材料提供在第一栅极结构与第二栅极结构之间提供电性隔离。
附图说明
根据以下的详细说明并配合附图可以更加理解本公开实施例。应注意的是，根据本产业的标准惯例，图示中的各种部件(feature)并未必按照比例绘制。事实上，可能任意的放大或缩小各种部件的尺寸，以做清楚的说明。
图1为例示性的鳍式场效晶体管(Fin Field-Effect Transistors，FinFET)装置的透视图。
图2A-6A为依据本公开各种实施例的制造半导体装置的各种阶段的上视图。
图2B-6B为依据本公开各种实施例的制造半导体装置的各种阶段的剖面示意图。
图2C-6C为依据本公开各种实施例的制造半导体装置的各种阶段的剖面示意图。
图7为依据本公开一些实施例的半导体装置的制造方法的流程图。
附图标记说明：
10、200 鳍式场效晶体管装置
12 磊晶成长材料
15N 型鳍式场效晶体管装置结构
25P 型鳍式场效晶体管装置结构
102 基底
104 鳍结构
105、230 间隙壁
108 隔离结构
110 栅极电极
112、114 硬遮罩
115 介电层
210、250 层
220 栅极结构
225、240、620、625、627、628 高度
235、275、535 厚度
270 层间介电层
300、520 开口
310 图案化硬遮罩层
320 图案化光阻层
330、340、530 尺寸
400、600 蚀刻工艺
410、610 蚀刻深度
500 沉积工艺
510 衬垫层
700 工艺
710 再填充材料
900 方法
910、920、930、940、950 步骤
具体实施方式
要了解的是以下的公开内容提供许多不同的实施例或范例，以实施提供的主体的不同部件。以下叙述各个构件及其排列方式的特定范例，以求简化公开内容的说明。当然，这些仅为范例并非用以限定本公开。例如，以下的公开内容叙述了将一第一部件形成于一第二部件之上或上方，即表示其包含了所形成的上述第一部件与上述第二部件是直接接触的实施例，亦包含了尚可将附加的部件形成于上述第一部件与上述第二部件之间，而使上述第一部件与上述第二部件可能未直接接触的实施例。此外，公开内容中不同范例可能使用重复的参考符号及/或用字。这些重复符号或用字为了简化与清晰的目的，并非用以限定各个实施例及/或所述外观结构之间的关系。
再者，为了方便描述附图中一元件或部件与另一(复数)元件或(复数)部件的关系，可使用空间相关用语，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及类似的用语。除了附图所示出的方位之外，空间相关用语也涵盖装置在使用或操作中的不同方位。举例来说，如果图中的装置被翻转，被描述为在其他元件或部件“下方”或“之下”的元件将被定位在其他元件或部件“上方”。因此，示例性术语“下方”可以涵盖上方和下方的方位。所述装置也可被另外定位(例如，旋转90度或者位于其他方位)，并对应地解读所使用的空间相关用语的描述。
再者，当用“大约”、“近似”及类似术语描述数字或数字范围时，此术语目的在涵盖合理范围中的数字，例如在所描述的数字的+/-10％之内，或本领域技术人员可理解的其他数值。举例来说，术语“约5nm”涵盖4.5nm至5.5nm的尺寸范围。
本公开实施例涉及在小的临界尺寸及/或高深宽比的情况中进行蚀刻工艺而不蚀刻不应被蚀刻的过量的层的方法，但不限于此。为了显示本公开实施例的各种方面，以下讨论鳍式场效晶体管的制造过程作为范例。在这方面，鳍式场效晶体管装置为鳍状的场效晶体管装置，鳍式场效晶体管装置在半导体工业越来越受欢迎。鳍式场效晶体管装置可为互补式金属氧化物半导体(complementary metal-oxide-semiconductor，CMOS)装置，互补式金属氧化物半导体装置包含P型金属氧化物半导体(P-type metal-oxide-semiconductor，PMOS)鳍式场效晶体管装置和N型金属氧化物半导体(N-type metal-oxide-semiconductor，NMOS)鳍式场效晶体管装置。以下公开将继续有一个或多个鳍式场效晶体管范例，以显示本公开各种实施例，但是可以理解的是，除了具体申明之外，本公开实施例不限于鳍式场效晶体管装置。
请参照图1，其显示例示性的鳍式场效晶体管装置10的透视图。鳍式场效晶体管装置10包含N型鳍式场效晶体管装置(NMOS)结构15和P型鳍式场效晶体管装置(PMOS)结构25。鳍式场效晶体管装置10包含基底102，基底102可由硅或其他半导体材料制成。替代地或另外地，基底102可包含其他元素半导体材料，例如锗。在一些实施例中，基底12由化合物半导体制成，例如碳化硅、砷化镓、砷化铟或磷化铟。在一些实施例中，基底102可由合金半导体制成，例如硅锗、碳化硅锗、磷化砷镓或磷化铟镓。在一些实施例中，基底102包含磊晶层。举例来说，基底102可包含覆盖块状(bulk)半导体的磊晶层。
鳍式场效晶体管装置10也包含一个或多个鳍结构104(例如Si鳍)在Z方向从基底102延伸，且间隙壁105在Y方向围绕鳍结构104。鳍结构104在X方向中伸长，且可选择性地包含锗(Ge)。鳍结构104可通过使用合适的工艺形成，例如光微影和蚀刻工艺。在一些实施例中，鳍结构104通过使用干蚀刻或等离子体蚀刻工艺从基底102蚀刻得到。在一些其他实施例中，鳍结构104可通过双重图案化微影(double-patterning lithography，DPL)工艺形成。双重图案化微影为通过将图案划分为两个交错的图案而在基底上构建图案的方法。鳍结构104也包含磊晶成长材料12，磊晶成长材料12(以及鳍结构104的一部分)可作为鳍式场效晶体管装置10的源极/漏极。
隔离结构108(例如浅沟槽隔离(shallow trench isolation，STI)结构)形成以围绕鳍结构104。在一些实施例中，隔离结构108围绕鳍结构104的下部，而鳍结构104的上部从隔离结构108突出，如图1所示。换句话说，鳍结构104的一部分埋置于隔离结构108中。隔离结构108防止电性干扰或串扰。
鳍式场效晶体管装置10还包含栅极堆叠结构，栅极堆叠结构包含栅极电极110和栅极电极110下方的栅极介电层(未显示)。栅极电极110可包含多晶硅或金属。金属包含氮化钽(TaN)、镍硅(NiSi)、钴硅(CoSi)、钼(Mo)、铜(Cu)、钨(W)、铝(Al)、钴(Co)、锆(Zr)、铂(Pt)或其他可应用的材料。栅极电极110可在栅极后制工艺(或栅极取代工艺)中形成。硬遮罩112和114可用于定义栅极电极110。介电层115也可形成于栅极电极110的侧壁上和硬遮罩112和114上方。
栅极介电层(未显示)可包含介电材料，例如氧化硅、氮化硅、氮氧化硅、有着高介电常数(high-k)的介电材料或前述的组合。高介电常数介电材料的范例包含氧化铪、氧化锆、氧化铝、二氧化铪-氧化铝合金、氧化铪硅、氧氮化铪硅、氧化铪钽、氧化铪钛、氧化铪锆、类似物或前述的组合。
在一些实施例中，栅极堆叠结构包含额外层，例如界面层、覆盖层、扩散/阻障层或其他可应用层。在一些实施例中，栅极堆叠结构形成于鳍结构104的中心部分上方。在一些其他实施例中，多个栅极堆叠结构形成于鳍结构104上方。在一些其他实施例中，栅极堆叠结构包含虚设栅极堆叠，且在进行高热预算工艺之后，金属栅极(metal gate，MG)取代虚设栅极堆叠。
栅极堆叠结构通过沉积工艺、光微影工艺和蚀刻工艺形成。蚀刻工艺包含化学气相沉积(chemical vapor deposition，CVD)、物理气相沉积(physical vapor deposition，PVD)、原子层沉积(atomic layer deposition，ALD)、高密度等离子体化学气相沉积(highdensity plasma CVD，HDPCVD)、金属有机化学气相沉积(metal organic CVD，MOCVD)、远端等离子体化学气相沉积(remote plasma CVD，RPCVD)、等离子体辅助化学气相沉积(plasmaenhanced CVD，PECVD)、电镀、其他合适的方法及/或前述的组合。光微影工艺包含光阻涂布(例如旋涂)、软烤、遮罩对准、曝光、曝光后烘烤、光阻显影、清洗、干燥(例如硬烤)。蚀刻工艺包含干蚀刻工艺或湿蚀刻工艺。或者，光微影工艺为通过其他合适的方法实现或取代，例如无遮罩光微影，电子束写入和离子束写入。
鳍式场效晶体管装置提供优于传统金属氧化物半导体场效晶体管(Metal-OxideSemiconductor Field Effect Transistor，MOSFET)装置(也被称为平面晶体管装置)的许多优点。这些优点可包含优选的芯片区域效率、改善的载子移动性以及与平面装置的制造过程相容的制造过程。因此，可期望设计使用鳍式场效晶体管装置用于集成电路芯片的一部分或整个集成电路芯片。
然而，制造鳍式场效晶体管可能仍具有挑战。举例来说，为了提供相邻鳍式场效晶体管装置的栅极结构之间的电性隔离，制造鳍式场效晶体管也涉及在栅极结构之间形成隔离结构。形成这些隔离结构的制造过程可被称为切割金属栅极(cut-metal-gate，CMG)工艺。作为切割金属栅极工艺的一部分，需进行蚀刻工艺以在相邻鳍式场效晶体管之间蚀刻沟槽。随着半导体部件尺寸持续缩小(导致较小的临界尺寸和较高的深宽比)，切割金属栅极蚀刻工艺可能需要具有高蚀刻偏压(etching bias)，其可导致在其他方法中的层间介电质(interlayer dielectric，ILD)的过度损失。层间介电质的过度损失可能降低装置效能或甚至导致装置失效。
为了降低层间介电质的过度损失，本公开实施例将蚀刻工艺分解为多个蚀刻工艺，并在多个蚀刻工艺之间形成额外的衬垫层。在至少一实施例中，多个蚀刻工艺包含两个蚀刻工艺。在第一蚀刻工艺期间，切割金属栅极的临界尺寸最初定义为较大，且深宽比最初很低，意味着在第一蚀刻工艺期间不需要高蚀刻偏压。因此，在第一蚀刻工艺期间不会发生过度的层间介电质损失。此后，相较于其他方法，衬垫层的形成帮助将切割金属栅极的临界尺寸降低至所期望的尺寸，且可以较小的切割金属栅极的临界尺寸进行第二蚀刻工艺。第二蚀刻工艺可能由于较小的临界尺寸和较高的深宽比而需要具有高蚀刻偏压，但是由于第二蚀刻工艺仅需蚀刻少量的材料，因此由高蚀刻偏压导致的任何层间介电质损失为可接受的。可以理解的是，被视为高蚀刻偏压的情况可能依据每个情况而变化，这可取决于一些因素，例如蚀刻气体组成、使用的蚀刻工具类型、被蚀刻的结构或材料、进入的离子类型、等向性或非等向性轮廓等。在一些实施例中，可将大于约200V的蚀刻偏压视为高蚀刻偏压。
以下将参考图2A-6A、图2B-6B、图2C-6C和图7更详细地讨论本公开实施例的各种方面。在这方面，图2A-6A显示在各种制造阶段的鳍式场效晶体管装置200的一部分的局部上视图，图2B-6B显示在各种制造阶段的鳍式场效晶体管装置200的一部分的局部剖面侧视图(在Y方向)，而图2C-6C显示在各种制造阶段的鳍式场效晶体管装置200的一部分的局部剖面侧视图(在垂直于Y方向的X方向)。更详细来说，图2B-6B的剖面侧视图由在鳍式场效晶体管装置200上沿Y方向切线M-M’(显示于第2A-6A图中)截取的剖面来得到，而图2C-6C的剖面侧视图由在鳍式场效晶体管装置200上沿X方向切线N-N’(显示于图2A-6A中)截取的剖面来得到。
请参照图2A、2B和2C，鳍式场效晶体管装置200包含层210。在一些实施例中，层210包含介电隔离结构，例如浅沟槽隔离(STI)。在一些其他实施例中，层210包含鳍结构，其也被称为混合鳍。在层210包含鳍结构的实施例中，可以理解的是，鳍结构形成于介电隔离结构(例如浅沟槽隔离)上方。
鳍式场效晶体管装置200包含栅极结构220(有时简称为栅极)，栅极结构220形成于层210上方。栅极结构220在Z方向中垂直地测量出高度225。在一些实施例中，栅极结构220包含高介电常数金属栅极(high-k metal gate，HKMG)。高介电常数金属栅极可在栅极取代工艺中形成，其中高介电常数栅极介电质和金属栅极电极取代虚设栅极介电质和虚设栅极电极。高介电常数介电材料为具有介电常数大于SiO2的介电常数，SiO2的介电常数约为4。在一实施例中，高介电常数栅极介电质包含氧化铪(HfO2)，氧化铪具有介电常数在约18与约40的范围中。在其他实施例中，高介电常数栅极介电质可包含ZrO2、Y2O3、La2O5、Gd2O5、TiO2、Ta2O5、HfErO、HfLaO、HfYO、HfGdO、HfAlO、HfZrO、HfTiO、HfTaO或SrTiO。
金属栅极电极形成于高介电常数介电质上方，且金属栅极电极可包含功函数金属组件和填充金属组件。功函数金属组件被配置为调整其对应的鳍式场效晶体管的功函数，以实现所期望的临界电压Vt。在各种实施例中，功函数金属组件可包含：TiAl、TiAlN、TaCN、TiN、WN或W或前述的组合。填充金属组件被配置作为功函数栅极结构的主要导电部分。在各种实施例中，填充金属组件可含有铝(Al)、钨(W)、铜(Cu)或前述的组合。
鳍式场效晶体管装置200还包含间隙壁230。如图2C所示，间隙壁230的一些区段形成于栅极结构220的侧壁上，而间隙壁230的其他区段形成于层210的上表面上方。间隙壁230包含介电材料，例如氮化硅(SiNx)、氮氧化硅(SiON)、氮碳氧化硅(SiOCN)或前述的组合。在一些实施例中，间隙壁230可通过沉积工艺，接着通过一个或多个蚀刻和研磨工艺来形成。每个间隙壁230具有厚度235。在一些实施例中，厚度235在约3nm与约15nm之间的范围中。每个间隙壁230也具有高度240，高度240是在Z方向从间隙壁230的最上表面到间隙壁230的最底表面测量得到。高度240大于栅极结构220的高度225，使得间隙壁230的上表面垂直地位于栅极结构220的上表面上方。在一些实施例中，间隙壁230的高度240在约20nm与约100nm之间的范围中。如下所述，由于第一蚀刻工艺将在到达间隙壁230的上表面时停止，因此间隙壁的高度240有效地定义第一蚀刻工艺的蚀刻深度。
鳍式场效晶体管装置200包含层250，层250形成于栅极结构220上方以及间隙壁230的一部分上方。层250也可被称为自对准接触(self-aligned contact，SAC)层。在一些实施例中，层250包含SiN、碳化系(SiC)、SiOCN或金属氧化物材料。从图2C可见层250具有T形。换句话说，层250的底部中间部分比层250的其他部分更向下延伸。描述层250的T形的另一方式为间隙壁230具有比栅极结构220更大的高度，使得层250与间隙壁230之间的界面位于层250与栅极结构220之间的界面上方。
在一些实施例中，层250的T形通过进行以下工艺实现：先形成虚设栅极结构，栅极间隙壁形成于虚设栅极结构的侧壁上。接着，进行栅极取代工艺，其中高介电常数金属栅极结构取代虚设栅极结构。对高介电常数金属栅极结构和栅极间隙壁进行回蚀刻工艺。当栅极间隙壁降低至高度240时，停止蚀刻栅极间隙壁。此后，在不再蚀刻栅极间隙壁之后，继续蚀刻高介电常数金属栅极结构，直到将高介电常数金属栅极结构蚀刻为栅极结构220。形成层250以代替移除的高介电常数金属栅极结构和移除的栅极间隙壁。在另一实施例中，在蚀刻高介电常数金属栅极结构之前，可蚀刻栅极间隙壁。在任何情况中，两种实施例导致间隙壁230的高度超过栅极结构220的高度。由于层250形成于栅极结构220和间隙壁230的上表面上，因此层250形成为具有T形轮廓。
鳍式场效晶体管装置200包含层间介电(ILD)层270。层间介电层270为最底部层间介电层，且可被称为ILD0层。层间介电层270位于层250的侧壁上以及间隙壁230的侧壁上。层间介电层270也位于间隙壁230的一部分上方。层间介电层270包含介电材料，例如在一些实施例中为低介电常数介电材料，或在一些其他实施例中为氧化硅。层间介电层270具有高度或厚度275。在一些实施例中，厚度275在约30nm与约200nm之间的范围中。相较于其他方法，本公开实施例帮助防止过度蚀刻层间介电层270，以下将更详细讨论。
图2A-2C显示定义切割金属栅极的制造的阶段。图2A以开口300显示切割金属栅极的上视图外形或轮廓。开口300通过图案化硬遮罩层310定义，图案化硬遮罩层310通过图案化光阻层320图案化。举例来说，硬遮罩材料(例如合适的介电材料)沉积于层250和层间介电层270上方，且光阻层(例如通过旋涂)形成于硬遮罩材料上方。接着，光阻层经历微影工艺，微影工艺可包含一个或多个步骤，例如曝光、曝光后烘烤、显影、清洗，以形成图案化光阻层320。图案化光阻层320定义切割金属栅极的开口300的上视轮廓。接着，硬遮罩材料通过图案化光阻层320图案化，且因此将切割金属栅极的开口300转移至图案化硬遮罩层310。
切割金属栅极的开口300具有在Y方向测量出的尺寸330以及在X方向测量出的尺寸340。尺寸330小于尺寸340，且因此可以说切割金属栅极的开口300的上视轮廓相似于在X方向上伸长的矩形。切割金属栅极的开口300的上视轮廓促进在后续工艺中“切割”栅极结构220(在上视图中，栅极结构220在Y方向上伸长)。
相较于其他方法，切割金属栅极的开口300在此可更大。切割金属栅极的开口300的较大尺寸允许有着较小蚀刻偏压的更宽松的蚀刻窗口。在一些实施例中，切割金属栅极的开口300的较大尺寸考虑到将形成的衬垫层的厚度。举例来说，尺寸330超过传统的切割金属栅极的开口约将形成的衬垫层的厚度的两倍，而尺寸340超过传统的切割金属栅极的开口约将形成的衬垫层的厚度的两倍。在一些实施例中，尺寸330在约21nm与约31nm之间的范围中，例如约26nm。相较之下，在某些技术节点中，传统切割金属栅极的开口的相应尺寸(在Y方向上测量)通常小于约15nm，但是可以理解的是，这个数字并非用以限制，且可在不同技术节点中变化。由于传统切割金属栅极的开口的Y方向尺寸定义切割金属栅极部件(例如隔离部件提供相邻栅极结构之间的电性隔离)的临界尺寸(CD)，可以说尺寸330等于切割金属栅极部件的临界尺寸和加倍的衬垫厚度的总和。如此一来，本公开实施例有效地扩大用于以下讨论的初始蚀刻工艺的切割金属栅极的临界尺寸，尽管切割金属栅极的最终临界尺寸将通过形成衬垫层而缩小至更期望的尺寸，以下将更详细讨论。
请参照图3A、3B和3C，例如通过光阻灰化或剥离工艺移除图案化光阻层320。使用图案化硬遮罩层310作为遮罩，进行蚀刻工艺400以通过切割金属栅极的开口300蚀刻在图案化硬遮罩层310下方的层，直到暴露出间隙壁230。在一些实施例中，蚀刻工艺400使用氯化物/氯基蚀刻剂，有着蚀刻偏压在约50V与约150V之间，且蚀刻时间/期间在约100秒与约300秒之间。蚀刻工艺400具有蚀刻深度410，蚀刻深度410为蚀刻掉层250的深度。由于蚀刻工艺当到达间隙壁230时停止，因此相较于传统切割金属栅极蚀刻工艺，蚀刻深度410更小。在一些实施例中，蚀刻深度410在约100nm与约180nm之间的范围中。在一些实施例中，蚀刻深度410与层间介电层270的厚度275的比例在约0.5：1与约0.9：1之间的范围中。此比例已被最佳化，因为假如此比例在此范围之外，则可能需要大量蚀刻来蚀刻具有高深宽比的小孔。因此，蚀刻的主要部分可能需要高蚀刻偏压来实现这样的小孔，这将使层间介电层270在蚀刻之后在其顶部遭受大的损失。
蚀刻工艺400的深宽比定义为蚀刻深度410与尺寸330的比例(410：330)，在一些实施例中，蚀刻工艺400的深宽比在约1.2：1与约7：1之间的范围中。相较于传统的切割金属栅极的蚀刻工艺可具有深宽比大于约20：1，此处的深宽比大幅降低。低深宽比的原因之一为相较于传统切割金属栅极的开口的较大的尺寸330。低深宽比的另一个原因为相较于传统切割金属栅极的开口的较小的蚀刻深度410。低深宽比以及较大的尺寸330缓和了与蚀刻工艺400相关的蚀刻偏压，这意味着可进行蚀刻工艺400而不会对层间介电层270造成过度损坏。相较之下，因为需要高蚀刻偏压来克服高深宽比和较小的切割金属栅极的临界尺寸，传统的切割金属栅极蚀刻工艺通常导致对层间介电层造成过度损坏(例如当通过切割金属栅极的开口向下蚀刻时，蚀刻过多的层间介电层)。
请参照图4A、4B和4C，进行衬垫沉积工艺500，以在切割金属栅极的开口300中以及层250和层间介电层270的暴露表面上方形成衬垫层510。由于衬垫层510部分地填充于开口300中，因此开口300缩小为较小的开口520，开口520在Y方向上测量为尺寸530。为了清楚起见，先前切割金属栅极的开口300和现在较小的开口520在图4A的上视图中以虚线显示。
衬垫层510具有厚度535。在一些实施例中，厚度535大致等于间隙壁230的厚度235，在其他实施例中(可以注意的是，此处的附图不一定按比例示出)，厚度535略小于厚度235(例如在厚度235的约80％与约100％之间)。衬垫层510的厚度535具体地被配置为将先前切割金属栅极的开口300的尺寸330缩小至约等于最终形成的切割金属栅极部件的尺寸。换句话说，现在较小的切割金属栅极的开口520的尺寸530大致等于切割金属栅极部件所期望的临界尺寸，在各种实施例中，尺寸530在约10nm与约70nm之间的范围中。在一些实施例中，厚度535在约3nm与约15nm之间的范围中。假如衬垫层510的厚度535被配置为太厚，此厚度可能干扰进行后续蚀刻工艺以“切割”栅极结构220。假如衬垫层510的厚度535被配置为太薄，此厚度可能不足以满足其缩小切割金属栅极的开口的临界尺寸及/或保护层间介电层270在后续蚀刻工艺中免受蚀刻的目的。
在一些实施例中，衬垫层510和间隙壁230具有不同的材料组成。在一些实施例中，衬垫层510和层间介电层270具有不同的材料组成。在一些实施例中，衬垫层510和层250具有不同的材料组成。作为非限制性的范例，衬垫层510可包含SiOx、SiNx、SiCN、SiON、SiOCN、AlOx、HfOx、LaOx、ZrOx或前述的组合。
请参照图5A、5B和5C，进行另一蚀刻工艺600以进一步使切割金属栅极的开口520垂直向下延伸，例如穿过层250以及穿过栅极结构220。在一些实施例中，蚀刻工艺600使用氯化物/氯基蚀刻剂，有着蚀刻偏压在约50V与约150V之间，且蚀刻时间/期间在约100秒与约300秒之间。换句话说，切割金属栅极的开口520现在“切开”栅极结构220或将其分离为两个不同的区段。
相较于蚀刻工艺400，蚀刻工艺600必须处理较小的切割金属栅极的开口520(即较小的切割金属栅极的临界尺寸)以及较高的深宽比，这是由于衬垫层510的存在。因此，蚀刻工艺600可能需要高蚀刻偏压。换句话说，由于较小的临界尺寸和较高的深宽比，蚀刻工艺600具有比蚀刻工艺400更大的蚀刻偏压。然而，蚀刻工艺600需要蚀刻掉的材料的总量很小，因为蚀刻工艺仅需要从衬垫层510的底部区段进行(在间隙壁230正上方)。
在一些实施例中，与蚀刻工艺600相关联的蚀刻深度610在约20nm与约100nm之间的范围中，蚀刻深度610显着地小于层间介电层270的厚度275。由于小的蚀刻深度，因此蚀刻工艺600的高蚀刻偏压不太可能对层间介电层270造成显着的损害。此外，由于衬垫层510位于层间介电层270的侧壁上，因此衬垫层510也可在蚀刻工艺600期间保护层间介电层270。作为蚀刻工艺的结果，层间介电层270的较小部分(接近顶部)可通过蚀刻工艺600蚀刻掉，这是可以容忍的。位于层间介电层270的侧壁上的衬垫层510的区段的顶部也被蚀刻掉，导致图5B显示的损失高度620(衬垫层510的损失高度)和图5C显示的损失高度625。换句话说，衬垫层510的高度减少了图5B所示的垂直高度620和图5C显示的垂直高度625。在一些实施例中，损失高度620在约20nm与约150nm之间的范围中，损失高度625大于损失高度620。这是因为在图4B-5B所示的剖面示意图中，从图案化硬遮罩层310向下蚀刻衬垫层510，而在图4C-5C所示的剖面示意图中，从层间介电层270向下蚀刻衬垫层510。因此，衬垫层510在第5B和5C图中的高度不相同，因为衬垫层510在图5B中高于在图5C中。在一些实施例中，虽然衬垫层510可仍保留在图5B中，衬垫层510在图5C中可完全被消耗。衬垫层510的剩下部分在图5B中具有衬垫高度627，而在图5C中具有衬垫高度628。在一些实施例中，衬垫高度627可在约5nm与约100nm之间的范围中，衬垫高度628可在约0nm与约90nm之间的范围中。在一些实施例中，衬垫高度628可完全被消耗。然而，在蚀刻之后，维持衬垫高度627以确保用于切割金属栅极的小尺寸(在Y方向上)。小尺寸有利于小的静态随机存取存储器(Static RandomAccess Memory，SRAM)和逻辑单元足迹。
请参照图6A、6B和6C，进行一个或多个工艺700以再开口520中形成再填充材料710。工艺700可包含沉积步骤，然后是研磨步骤。举例来说，沉积步骤将再填充材料710沉积于开口520中，而研磨步骤(例如化学机械研磨(chemical mechanical polishing，CMP))将层间介电层270和再填充材料710的上表面平坦化。在一些实施例中，再填充材料710可包含电性绝缘材料，例如SiOx、SiNx、SiCN、SiON、SiOCN、AlOx、HfOx、LaOx、ZrOx或前述的组合。可以理解的是，再填充材料710和衬垫层510可不必具有相同的材料组成。
再填充材料710形成于层210(其可为虚设鳍)的上表面上方，且再填充材料710的侧壁物理接触间隙壁230的侧壁、衬垫层510的侧壁和层间介电层270的侧壁的一部分。也可以说衬垫层510围绕再填充材料710的一部分。注意到在图6B和6C的剖面示意图中，再填充材料710也具有T形剖面轮廓。然而，由于损失高度620和625(以上参考图5B-5C讨论)的差异，因此在图6B和6C中的T形剖面轮廓不同。举例来说，在图6B中的再填充材料710的顶部(例如形成于衬垫层510上方的部分)比在图6C中的再填充材料710的顶部更薄。再填充材料710也可被称为切割金属栅极部件，如上所述，切割金属栅极部件用于提供相邻晶体管的栅极结构之间的电性隔离。
如上所述，因为小的切割金属栅极临界尺寸和切割金属栅极的高深宽比，因此传统切割金属栅极蚀刻工艺需要具有高蚀刻偏压。然而，因为在切割金属栅极形成期间，层间介电层被无意地蚀刻掉，高蚀刻偏压造成层间介电层的过度损失。此处，本公开实施例定义有着大尺寸的切割金属栅极的开口，并以两个蚀刻工艺来蚀刻切割金属栅极的开口。在切割金属栅极的临界尺寸较大(因为以较大的临界尺寸定义初始的切割金属栅极的开口)以及较低的深宽比(因为第一蚀刻工艺不需要一直蚀刻)时进行第一蚀刻工艺。因此，第一蚀刻工艺不需具有高蚀刻偏压，其意味着降低了层间介电质的损失。在进行第一蚀刻工艺之后，衬垫层形成于切割金属栅极的开口中，以将切割金属栅极的临界尺寸降低至所期望的小的切割金属栅极的临界尺寸。此后，进行第二蚀刻工艺。第二蚀刻工艺可具有高蚀刻偏压，但是由于第二蚀刻工艺仅需蚀刻少量(例如较小的蚀刻深度)，因此第二蚀刻工艺的高蚀刻偏压将不会导致层间介电层的过度损坏。如此一来，本公开实施例可实现小的切割金属栅极的临界尺寸，同时确保最小化任何(不期望的)层间介电质的损失。
图7为依据本公开各种方面的半导体装置的制造方法900的流程图。方法900包含步骤910，步骤910在半导体装置上方形成遮罩层。在一些实施例中，半导体装置包含鳍式场效晶体管。半导体装置包含：栅极结构，第一层设置于栅极结构上方，以及层间介电质(ILD)设置于第一层的侧壁上。遮罩层包含开口暴露出第一层的一部分和层间介电层的一部分。在一些实施例中，栅极结构在上视图中在第一方向上延伸，且开口在上视图中在第二方向上延伸，第二方向不同于第一方向。在一些实施例中，半导体装置还包含间隙壁设置于栅极结构的侧壁上，其中间隙壁的上表面位于栅极结构的上表面上方。在一些实施例中，第一层在剖面示意图中具有T形轮廓。
方法900包含步骤920，步骤920进行第一蚀刻工艺，以通过开口蚀刻第一层的一部分和层间介电质的一部分。
方法900包含步骤930，步骤930在进行第一蚀刻工艺之后，在开口中形成衬垫层。在一些实施例中，形成衬垫层的步骤包括形成衬垫的厚度等于或小于每个间隙壁的厚度。在一些实施例中，形成SiOx、SiNx、SiCN、SiON、SiOCN、AlOx、HfOx、LaOx、ZrOx或前述的组合作为衬垫层。
方法900包含步骤940，步骤940在形成衬垫层之后，进行第二蚀刻工艺。第二蚀刻工艺使开口向下延伸而穿过第一层以及穿过栅极结构。在一些实施例中，第二蚀刻工艺移除衬垫层的一部分但并非全部。在一些实施例中，第二蚀刻工艺具有比第一蚀刻工艺更大的蚀刻偏压。
方法900包含步骤950，步骤950在进行第二蚀刻工艺之后，以第二层填充开口。在一些实施例中，步骤950包括以电性绝缘材料作为第二层来填充开口。
可以理解的是，可在上述步骤910-950之前、期间或之后进行额外的工艺步骤，以完成半导体装置的制造。举例来说，方法900可包含在进行步骤910之前，形成半导体装置的源极/漏极，且在进行步骤950之后，形成接点/导通孔/金属线。可进行其他步骤，但是为了简单起见，此处不详细讨论。
基于以上讨论，可见本公开实施例提供优于传统鳍式场效晶体管装置及其制造方法的优点。然而，可以理解的是，其他实施例可提供额外的优点，并非所有优点都必须公开于此，且并非所有实施例都需要特别的优点。本公开实施例的优点之一为防止过度的层间介电质损失。这是因为以两步骤进行切割金属栅极的蚀刻工艺：有着较大切割金属栅极的临界尺寸和较低深宽比进行第一蚀刻步骤，且因此第一蚀刻步骤的蚀刻偏压可比传统切割金属栅极的蚀刻工艺更低。由于高蚀刻偏压为过度层间介电质损失的主要原因，此处第一蚀刻步骤较低的蚀刻偏压降低蚀刻期间的层间介电质的损失。当进行第二蚀刻步骤时，切割金属栅极的临界尺寸较小，且深宽比可较大，且因此第二蚀刻步骤可能需要比第一蚀刻步骤更高的蚀刻偏压(但是仍低于传统切割金属栅极的蚀刻工艺的蚀刻偏压)。然而，第二蚀刻步骤仍不会导致过度的层间介电质损失。这是因为第二蚀刻步骤仅需要蚀刻掉少量的材料(因为第一蚀刻步骤已蚀刻切割金属栅极的开口的大部分)。如此一来，第二蚀刻步骤导致的层间介电质损失一般为可接受的。本公开实施例的另一优点为可保留或维持尖端半导体技术节点所需的小的切割金属栅极的临界尺寸。举例来说，虽然一开始定义较大的切割金属栅极的开口(用于第一蚀刻步骤)，但是在进行第一蚀刻步骤之后以及在进行第二蚀刻步骤之前，本公开实施例形成衬垫层以将切割金属栅极的临界尺寸降低至所期望的尺寸。因此，第二蚀刻步骤仍可形成有着小的切割金属栅极的临界尺寸的切割金属栅极的开口。其他优点包含与现有的制造过程流程相容等。
本公开实施例的一方面涉及半导体装置的制造方法，此方法包含在半导体元件上方形成遮罩层，其中半导体元件包含：栅极结构；第一层，设置于栅极结构上方；以及层间介电质(ILD)，设置于第一层的侧壁上，且其中遮罩层定义开口暴露出第一层的一部分和层间介电质的一部分。此方法包含进行第一蚀刻工艺，以通过开口蚀刻第一层的一部分和层间介电质的一部分。此方法包含在进行第一蚀刻工艺之后，在开口中形成一衬垫层。此方法包含在形成衬垫层之后，进行第二蚀刻工艺，其中第二蚀刻工艺使开口向下延伸而穿过第一层和穿过栅极结构。此方法包含在进行第二蚀刻工艺之后，以一第二层填充开口。
在一些其他实施例中，其中栅极结构在上视图中沿第一方向延伸；以及开口在上视图中沿第二方向延伸，第二方向不同于第一方向。
在一些其他实施例中，其中第二蚀刻工艺移除衬垫层的一部分但并非全部。
在一些其他实施例中，其中第二蚀刻工艺具有比第一蚀刻工艺更大的蚀刻偏压。
在一些其他实施例中，其中填充步骤包含以电性绝缘材料作为第二层填充开口。
在一些其他实施例中，其中在进行第一蚀刻工艺之前，第一层在剖面示意图中具有T形轮廓。
在一些其他实施例中，其中在形成遮罩层之前，半导体装置还包含间隙壁设置于栅极结构的侧壁上，其中间隙壁的上表面位于栅极结构的上表面上方。
在一些其他实施例中，其中形成衬垫层的步骤包含形成衬垫层的厚度等于或小于每个间隙壁的厚度。
在一些其他实施例中，其中形成衬垫层的步骤包含形成SiOx、SiNx、SiCN、SiON、SiOCN、AlOx、HfOx、LaOx、ZrOx作为衬垫层。
在一些其他实施例中，其中半导体元件包含鳍式场效晶体管。
本公开实施例的一方面涉及半导体装置的制造方法，此方法包含形成半导体元件的步骤，半导体元件包含：栅极结构，间隙壁位于栅极结构的侧壁上，第一层具有T形轮廓位于栅极结构上方，以及层间介电质(ILD)位于第一层的侧壁上和间隙壁的侧壁上，其中间隙壁的上表面位于栅极结构的上表面上方。此方法包含在半导体元件上方形成图案化遮罩层，图案化遮罩层定义开口暴露出第一层的一部分和层间介电质的一部分。此方法包含对半导体元件进行第一蚀刻工艺，使开口向下延伸，其中第一蚀刻工艺移除第一层位于间隙壁的上表面上方的一部分。此方法包含在进行第一蚀刻工艺之后，在开口中形成衬垫层。此方法包含在形成衬垫层之后，进行第二蚀刻工艺以进一步使开口向下延伸而穿过第一层以及穿过栅极结构，进而将栅极结构分离为两个区段。此方法包含在进行第二蚀刻工艺之后，在开口中形成电性绝缘材料。
在一些其他实施例中，其中当形成图案化遮罩层时，栅极结构在上视图中沿第一方向伸长；以及开口在上视图中沿第二方向伸长，第二方向不同于第一方向。
在一些其他实施例中，其中第二蚀刻工艺比第一蚀刻工艺具有更大的蚀刻偏压。
在一些其他实施例中，其中第二蚀刻工艺减少衬垫层的高度。
在一些其他实施例中，其中形成衬垫层的厚度等于或小于每个间隙壁的厚度。
本公开实施例的另一方面涉及半导体装置，半导体装置包含一层，此层包含鳍结构或介电沟槽隔离部件；第一栅极结构和第二栅极结构，设置于此层上方；间隙壁，设置于此层的侧壁上，其中间隙壁的上表面位于此层的上表面上方；衬垫，设置于间隙壁的上表面上方；以及电性绝缘材料，设置于此层上方以及第一栅极结构与第二栅极结构之间、间隙壁之间以及衬垫之间，其中电性绝缘材料提供在第一栅极结构与第二栅极结构之间提供电性隔离。
在一些其他实施例中，其中电性绝缘材料在至少两个剖面示意图中具有不同的T形轮廓。
在一些其他实施例中，上述半导体装置还包含层间介电质(ILD)，其中间隙壁和衬垫设置于层间介电质与电性绝缘材料之间。
在一些其他实施例中，其中衬垫围绕电性绝缘材料的至少一部分。
在一些其他实施例中，其中衬垫的厚度等于或小于间隙壁的厚度。
前述内文概述了许多实施例的特征，使本技术领域中技术人员可以从各个方面更加了解本公开实施例。本技术领域中技术人员应可理解，且可轻易地以本公开实施例为基础来设计或修饰其他工艺及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中技术人员也应了解这些相等的结构并未背离本公开的公开构思与范围。在不背离本公开的公开构思与范围的前提下，可对本公开实施例进行各种改变、置换或修改。

Claims (1)

1.一种半导体装置的制造方法，包括：
在一半导体元件上方形成一遮罩层，其中该半导体元件包含：
一栅极结构；
一第一层，设置于该栅极结构上方；以及
一层间介电质，设置于该第一层的侧壁上，且其中该遮罩层定义一开口暴露出该第一层的一部分和该层间介电质的一部分；
进行一第一蚀刻工艺，以通过该开口蚀刻该第一层的一部分和该层间介电质的一部分；
在进行该第一蚀刻工艺之后，在该开口中形成一衬垫层；
在形成该衬垫层之后，进行一第二蚀刻工艺，其中该第二蚀刻工艺使该开口向下延伸而穿过该第一层和穿过该栅极结构；以及
在进行该第二蚀刻工艺之后，以一第二层填充该开口。
CN201910126403.3A 2018-06-28 2019-02-20 半导体装置的制造方法 Pending CN110660854A (zh)

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Family Cites Families (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US7425740B2 (en) 2005-10-07 2008-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for a 1T-RAM bit cell and macro
US7667271B2 (en) 2007-04-27 2010-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistors
US8048723B2 (en) 2008-12-05 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs having dielectric punch-through stoppers
US8776734B1 (en) 2008-05-19 2014-07-15 Innovative Environmental Solutions, Llc Remedial system: a pollution control device for utilizing and abating volatile organic compounds
US7910453B2 (en) 2008-07-14 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Storage nitride encapsulation for non-planar sonos NAND flash charge retention
US8629506B2 (en) * 2009-03-19 2014-01-14 International Business Machines Corporation Replacement gate CMOS
US8053299B2 (en) 2009-04-17 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabrication of a FinFET element
US8440517B2 (en) 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8497528B2 (en) 2010-05-06 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating a strained structure
US9245805B2 (en) 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
US8362575B2 (en) 2009-09-29 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling the shape of source/drain regions in FinFETs
US8610240B2 (en) 2009-10-16 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit with multi recessed shallow trench isolation
US8415718B2 (en) 2009-10-30 2013-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming epi film in substrate trench
US8395195B2 (en) 2010-02-09 2013-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Bottom-notched SiGe FinFET formation using condensation
US8310013B2 (en) 2010-02-11 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a FinFET device
US8399931B2 (en) 2010-06-30 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Layout for multiple-fin SRAM cell
US8729627B2 (en) 2010-05-14 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel integrated circuit devices
US8796759B2 (en) 2010-07-15 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) device and method of manufacturing same
US8367498B2 (en) 2010-10-18 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-like field effect transistor (FinFET) device and method of manufacturing same
US8487378B2 (en) 2011-01-21 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Non-uniform channel junction-less transistor
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US8618556B2 (en) 2011-06-30 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design and method of fabricating same
US8962400B2 (en) 2011-07-07 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ doping of arsenic for source and drain epitaxy
US8609518B2 (en) 2011-07-22 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Re-growing source/drain regions from un-relaxed silicon layer
US8841701B2 (en) 2011-08-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device having a channel defined in a diamond-like shape semiconductor structure
US8466027B2 (en) 2011-09-08 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide formation and associated devices
US8723272B2 (en) 2011-10-04 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US8723236B2 (en) 2011-10-13 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of manufacturing same
US8815712B2 (en) 2011-12-28 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for epitaxial re-growth of semiconductor region
US8887106B2 (en) 2011-12-28 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process
US8377779B1 (en) 2012-01-03 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing semiconductor devices and transistors
US8735993B2 (en) 2012-01-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET body contact and method of making same
US8742509B2 (en) 2012-03-01 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for FinFETs
US8847293B2 (en) 2012-03-02 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure for semiconductor device
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8836016B2 (en) 2012-03-08 2014-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods with high mobility and high energy bandgap materials
US8716765B2 (en) 2012-03-23 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US9171929B2 (en) 2012-04-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of semiconductor device and method of making the strained structure
US8680576B2 (en) 2012-05-16 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device and method of forming the same
US8729634B2 (en) 2012-06-15 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with high mobility and strain channel
US8736056B2 (en) 2012-07-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Device for reducing contact resistance of a metal
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8633516B1 (en) 2012-09-28 2014-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain stack stressor for semiconductor device
US8497177B1 (en) 2012-10-04 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US8809139B2 (en) 2012-11-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fin-last FinFET and methods of forming same
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US9093530B2 (en) 2012-12-28 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of FinFET
US8946793B2 (en) * 2013-02-05 2015-02-03 GlobalFoundries, Inc. Integrated circuits having replacement gate structures and methods for fabricating the same
US8853025B2 (en) 2013-02-08 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET/tri-gate channel doping for multiple threshold voltage tuning
US9093514B2 (en) 2013-03-06 2015-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Strained and uniform doping technique for FINFETs
US8826213B1 (en) 2013-03-11 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Parasitic capacitance extraction for FinFETs
US8943455B2 (en) 2013-03-12 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for layout verification for polysilicon cell edge structures in FinFET standard cells
US9214555B2 (en) 2013-03-12 2015-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer for FinFET channels
US9263275B2 (en) * 2013-03-12 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Interface for metal gate integration
US8963258B2 (en) 2013-03-13 2015-02-24 Taiwan Semiconductor Manufacturing Company FinFET with bottom SiGe layer in source/drain
US8796666B1 (en) 2013-04-26 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with strain buffer layer and methods of forming the same
US20150214331A1 (en) * 2014-01-30 2015-07-30 Globalfoundries Inc. Replacement metal gate including dielectric gate material
US9548303B2 (en) 2014-03-13 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices with unique fin shape and the fabrication thereof
US9449963B2 (en) * 2014-07-03 2016-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure with hard mask structure formed thereon and method for forming the same
KR102201092B1 (ko) * 2014-09-16 2021-01-11 삼성전자주식회사 반도체 장치 제조 방법
US9502418B2 (en) * 2014-10-02 2016-11-22 International Business Machines Corporation Semiconductor devices with sidewall spacers of equal thickness
KR102394938B1 (ko) * 2015-05-21 2022-05-09 삼성전자주식회사 반도체 소자 및 반도체 소자의 제조 방법
US9653466B2 (en) * 2015-08-04 2017-05-16 Qualcomm Incorporated FinFET device and method of making the same
US10796924B2 (en) * 2016-02-18 2020-10-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof by forming thin uniform silicide on epitaxial source/drain structure
US10177041B2 (en) * 2017-03-10 2019-01-08 Globalfoundries Inc. Fin-type field effect transistors (FINFETS) with replacement metal gates and methods
US10083874B1 (en) * 2017-03-23 2018-09-25 Globalfoundries Inc. Gate cut method
US10090169B1 (en) * 2017-03-31 2018-10-02 Globalfoundries Inc. Methods of forming integrated circuit structures including opening filled with insulator in metal gate
US9818836B1 (en) * 2017-04-13 2017-11-14 Globalfoundries Inc. Gate cut method for replacement metal gate integration
US10396206B2 (en) * 2017-07-07 2019-08-27 Globalfoundries Inc. Gate cut method
US10176995B1 (en) * 2017-08-09 2019-01-08 Globalfoundries Inc. Methods, apparatus and system for gate cut process using a stress material in a finFET device
US20190067115A1 (en) * 2017-08-23 2019-02-28 Globalfoundries Inc. Gate cut method for replacement metal gate
US10236213B1 (en) * 2018-03-12 2019-03-19 Globalfoundries Inc. Gate cut structure with liner spacer and related method
US10388771B1 (en) 2018-06-28 2019-08-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method and device for forming cut-metal-gate feature

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US10388771B1 (en) 2019-08-20
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US20200006531A1 (en) 2020-01-02
US10950713B2 (en) 2021-03-16

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