CN110491837A - 用于替换栅极流程的内部l间隔件 - Google Patents

用于替换栅极流程的内部l间隔件 Download PDF

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CN110491837A
CN110491837A CN201910718825.XA CN201910718825A CN110491837A CN 110491837 A CN110491837 A CN 110491837A CN 201910718825 A CN201910718825 A CN 201910718825A CN 110491837 A CN110491837 A CN 110491837A
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lining
nanometers
chamber
dielectric layer
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CN110491837B (zh
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切特·弗农·伦诺克斯
森秋·宋
布赖恩·K·柯克帕特里克
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Texas Instruments Inc
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Abstract

本申请案涉及用于替换栅极流程的内部L间隔件。通过移除牺牲栅极电介质层(110)及牺牲栅极(112)以形成栅极腔(128)而形成集成电路(100)。在所述栅极腔(128)中形成保形电介质第一衬里(132)且在所述第一衬里(132)上形成保形第二衬里(134)。第一蚀刻从所述栅极腔(128)的底部移除所述第二衬里(134)，而留下在所述栅极腔(128)的侧壁(114)上的所述第二衬里(134)的材料。第二蚀刻从所述栅极腔(128)的所述底部移除由所述第二衬里(134)暴露的所述第一衬里(132)，而留下在所述栅极腔(128)的所述底部上在所述栅极腔(128)的所述侧壁(114)上的所述第二衬里(134)下方的所述第一衬里(132)的材料。第三蚀刻从所述栅极腔(128)移除所述第二衬里(134)，而留下在所述栅极腔(128)中的所述第一衬里(132)的L形间隔件(148)。在所述栅极腔(128)中形成永久栅极电介质层(156)及替换栅极(160)。

Description

用于替换栅极流程的内部L间隔件
本申请是申请日为2014年9月10日、申请号为“201410458219.6”、发明名称为“用于替换栅极流程的内部L间隔件”的发明专利申请的分案申请。
技术领域
本发明涉及集成电路的领域。更特定来说，本发明涉及集成电路中的MOS晶体管。
背景技术
用于金属氧化物半导体(MOS)晶体管的替换栅极过程必须对抗越来越小的栅极长度及因此待填充的栅极腔的较高纵横比。具有数个保形层的替换栅极结构可尤其具挑战性。
发明内容
下文呈现简化发明内容以便提供对本发明的一或多个方面的基本理解。本发明内容并非本发明的扩展概述，且既不打算识别本发明的关键或紧要元件，也不打算记述其范围。而是，本发明内容的主要目的为以简化形式呈现本发明的一些概念作为稍后所呈现的更详细说明的前言。
一种含有MOS晶体管的集成电路通过形成由电介质材料环绕的牺牲栅极电介质层及牺牲栅极而形成。暴露所述牺牲栅极的顶部表面且移除所述牺牲栅极及所述牺牲栅极电介质层以形成栅极腔。在所述栅极腔中形成保形电介质第一衬里且在所述栅极腔中在所述第一衬里上形成保形第二衬里。各向异性第一蚀刻从所述栅极腔的底部移除所述第二衬里，而留下在所述栅极腔的侧壁上的所述第二衬里的材料。第二蚀刻从所述栅极腔的所述底部的区移除由所述第二衬里暴露的所述第一衬里，而留下在所述栅极腔的所述底部上在所述栅极腔的所述侧壁上的所述第二衬里下方的所述第一衬里的材料。第三蚀刻从所述栅极腔移除所述第二衬里，而留下在所述栅极腔中的所述第一衬里的L形间隔件。在所述栅极腔中形成永久栅极电介质层且在所述栅极腔中形成替换栅极。
附图说明
图1A到图1I是以连续制作阶段描绘的含有具有替换栅极的MOS晶体管的示范性集成电路的横截面。
图2A到图2F描绘用于集成电路的替代制作序列。
具体实施方式
参考附图描述本发明。所述图未按比例绘制且其仅经提供以图解说明本发明。下文参考用于说明的实例性应用来描述本发明的数个方面。应理解，陈述众多特定细节、关系及方法以提供对本发明的理解。然而，所属领域的技术人员将容易地认识到，可在不使用所述特定细节中的一或多者或者使用其它方法的情况下实践本发明。在其它例子中，未详细展示众所周知的结构或操作以避免使本发明模糊。本发明不受动作或事件的所图解说明排序限制，这是因为一些动作可以不同次序发生及/或与其它动作或事件同时发生。此外，未必需要所有所图解说明动作或事件来实施根据本发明的方法。
一种含有MOS晶体管的集成电路通过形成由电介质材料环绕的牺牲栅极电介质层及牺牲栅极而形成。暴露所述牺牲栅极的顶部表面且移除所述牺牲栅极及所述牺牲栅极电介质层以形成栅极腔。在所述栅极腔中形成保形电介质第一衬里且在所述栅极腔中在所述第一衬里上形成保形第二衬里。各向异性第一蚀刻从所述栅极腔的底部移除所述第二衬里，而留下在所述栅极腔的侧壁上的所述第二衬里的材料。第二蚀刻从所述栅极腔的所述底部的区移除由所述第二衬里暴露的所述第一衬里，而留下在所述栅极腔的所述底部上在所述栅极腔的所述侧壁上的所述第二衬里下方的所述第一衬里的材料。第三蚀刻从所述栅极腔移除所述第二衬里，而留下在所述栅极腔中的所述第一衬里的L形间隔件。在所述栅极腔中形成永久栅极电介质层且在所述栅极腔中形成替换栅极。形成具有所述栅极腔中的所述L形间隔件的所述MOS晶体管可有利地提供将在其中形成所述替换栅极的为较低纵横比栅极腔的较宽栅极腔，借此提供用于栅极替换过程的较多过程宽容度。
图1A到图1I是以连续制作阶段描绘的含有具有替换栅极的MOS晶体管的示范性集成电路的横截面。参考图1A，在衬底102中及其上形成集成电路100，衬底102为(例如)单晶硅晶片，但可为绝缘体上硅(SOI)晶片、具有不同晶体定向区域的混合定向技术(HOT)晶片或适用于制作集成电路100的其它衬底。
集成电路100包含用于第一MOS晶体管104的区及可能用于具有与第一MOS晶体管104相反的极性的第二MOS晶体管106的区。举例来说，第一MOS晶体管104可为p沟道MOS(PMOS)晶体管104且第二MOS晶体管106可为n沟道MOS(NMOS)晶体管106。第一MOS晶体管104与第二MOS晶体管106可由形成于衬底102的顶部表面处的场氧化物108横向隔离。场氧化物108可包含通过浅沟槽隔离(STI)过程形成的二氧化硅。
第一MOS晶体管104包含形成于衬底102的顶部表面处的第一牺牲栅极电介质层110。举例来说，第一牺牲栅极电介质层110可为通过衬底102的顶部表面的热氧化形成的2纳米到5纳米的二氧化硅。第一MOS晶体管104包含形成于第一牺牲栅极电介质层110上的第一牺牲栅极112。举例来说，第一牺牲栅极112可为30纳米到60纳米厚的多晶体硅(polycrystalline silicon)(通常称为多晶硅(polysilicon)。举例来说，第一牺牲栅极112可通过以下操作形成：在集成电路100的现有顶部表面上形成多晶硅层，在多晶硅层上方形成蚀刻掩模及在反应性离子蚀刻(RIE)过程中移除多晶硅以留下第一牺牲栅极112。第一MOS晶体管104可任选地包含邻接第一牺牲栅极112的横向表面的2纳米到30纳米厚的一或多个电介质材料层的第一侧壁114。第一侧壁114可通过以下操作形成：热氧化第一牺牲栅极112的横向表面以及在第一牺牲栅极112上方形成一或多个氮化硅及/或二氧化硅保形层，后续接着各向异性蚀刻以从第一牺牲栅极112及衬底102的水平表面移除氮化硅及/或二氧化硅层，而留下第一侧壁114。第一MOS晶体管104包含在衬底102中邻近于且叠置于第一牺牲栅极112下形成的第一源极/漏极区域116。第一源极/漏极区域116的横向尺寸可在将掺杂剂植入到衬底102中以形成第一源极/漏极区域116期间部分地由第一侧壁114的厚度确定。
第二MOS晶体管106包含形成于衬底102的顶部表面处的第二牺牲栅极电介质层118。举例来说，第二牺牲栅极电介质层118可与第一牺牲栅极电介质层110类似且与其同时形成。第二MOS晶体管106包含形成于第二牺牲栅极电介质层118上的第二牺牲栅极120。举例来说，第二牺牲栅极120可与第一牺牲栅极112类似且与其同时形成。第二MOS晶体管106可任选地包含邻接第二牺牲栅极120的横向表面的一或多个电介质材料层的第二侧壁122。第二侧壁122可以与第一侧壁114类似的方式形成，但可能具有不同层及/或不同厚度。第二MOS晶体管106包含在衬底102中邻近于且叠置于第二牺牲栅极120下形成的第二源极/漏极区域124。第二源极/漏极区域124的横向尺寸可在将掺杂剂植入到衬底102中以形成第二源极/漏极区域124期间部分地由第二侧壁122的厚度确定。
在衬底102上方形成保护性电介质层126。举例来说，保护性电介质层126可包含一或多个二氧化硅及/或氮化硅层。保护性电介质层126可进一步包含硬材料(例如氮化硅或碳氮化硅)的顶盖层(未展示)以提供用于后续移除过程的停止层。
举例来说，通过化学机械抛光(CMP)过程从第一牺牲栅极112及第二牺牲栅极120的顶部表面移除保护性电介质层126以便暴露第一牺牲栅极112及第二牺牲栅极120的顶部表面。
参考图1B，移除第一牺牲栅极112及第一牺牲栅极电介质层110以形成第一栅极腔128。同时，移除第二牺牲栅极120及第二牺牲栅极电介质层118以形成第二栅极腔130。举例来说，可使用借助四甲基氢氧化铵(TMAH)的水溶液的湿式蚀刻移除第一牺牲栅极112及第二牺牲栅极120。在移除第一牺牲栅极112及第二牺牲栅极120之后，可借助水缓冲氢氟酸的湿式蚀刻同时移除第一牺牲栅极电介质层110及第二牺牲栅极电介质层118。第一侧壁114及第二侧壁122的至少一部分在完成第一牺牲栅极112、第二牺牲栅极120、第一牺牲栅极电介质层110及第二牺牲栅极电介质层118的移除之后保持于适当位置中。
参考图1C，在保护性电介质层126的顶部表面上保形地形成电介质材料的第一衬里132，从而延伸到第一栅极腔128及第二栅极腔130中。第一衬里132在第一栅极腔128及第二栅极腔130的底部处接触衬底102。第一衬里132在第一侧壁114及第二侧壁122上为连续的且提供蚀刻停止层以在后续湿式蚀刻过程中保护第一侧壁114及第二侧壁122。举例来说，第一衬里132可为通过类似于原子层沉积(ALD)的多步骤顺序沉积过程形成以提供所要厚度控制及保形性的二氧化硅。第一衬里132的最小厚度可为1纳米。第一衬里132的最大厚度取决于第一MOS晶体管104及第二MOS晶体管106的所要栅极长度以及集成电路100中的晶体管之间的最小间隔件。在一个实例中，具有26纳米到30纳米的所要栅极长度的第一MOS晶体管104及第二MOS晶体管106的例子可具有带有1纳米到4纳米的厚度的第一衬里132的例子。在另一实例中，具有18纳米到22纳米的所要栅极长度的第一MOS晶体管104及第二MOS晶体管106的例子可具有带有1纳米到3纳米的厚度的第一衬里132的例子。在又一实例中，具有12纳米到16纳米的所要栅极长度的第一MOS晶体管104及第二MOS晶体管106的例子可具有带有1纳米到2.5纳米的厚度的第一衬里132的例子。
在第一衬里132上保形地形成不同于第一衬里132的电介质材料的第二衬里134，从而延伸到第一栅极腔128及第二栅极腔130中。举例来说，第二衬里134可为通过使用六氯乙硅烷及氨的等离子增强型化学气相沉积(PECVD)过程形成的氮化硅。用于形成第二衬里134的过程参数(例如压力、温度及形成时间)经选择以提供第二衬里134在第一衬里132的垂直表面上在第一栅极腔128及第二栅极腔130中的所要厚度。第二衬里134的最小厚度可为1纳米。第一衬里132与第二衬里134的总的最大厚度也取决于第一MOS晶体管104及第二MOS晶体管106的所要栅极长度以及集成电路100中的晶体管之间的最小间隔件。在上文所描述的第一情形中，具有26纳米到30纳米的所要栅极长度的第一MOS晶体管104及第二MOS晶体管106的例子可具有第一衬里132与第二衬里134的5纳米的总的最大厚度。在上文所描述的第二情形中，具有18纳米到22纳米的所要栅极长度的第一MOS晶体管104及第二MOS晶体管106的例子可具有第一衬里132与第二衬里134的4纳米的总的最大厚度。在上文所描述的第三情形中，具有12纳米到16纳米的所要栅极长度的第一MOS晶体管104及第二MOS晶体管106的例子可具有第一衬里132与第二衬里134的3.5纳米的总的最大厚度。
参考图1D，如图1D中所示意性地描绘，各向异性第一蚀刻过程136(例如使用氟原子团的RIE过程)从保护性电介质层126的顶部表面上方以及从第一栅极腔128及第二栅极腔130的底部移除第二衬里134，而留下在第一衬里132的垂直表面上在第一栅极腔128及第二栅极腔130中的第二衬里134。各向异性第一蚀刻过程136的过程参数(例如压力、功率及过蚀刻时间)经选择以便留下第一衬里132在衬底102上在第一栅极腔128及第二栅极腔130的底部处的所要厚度。
参考图1E，第二蚀刻过程138从保护性电介质层126的顶部表面以及从第一栅极腔128及第二栅极腔130的底部移除第一衬里132以暴露衬底102。第二蚀刻过程138留下在第一侧壁114的垂直表面上及在衬底102上在第一栅极腔128中的第二衬里134下方的第一衬里132。类似地，第二蚀刻过程138留下在第二侧壁122的垂直表面上及在衬底102上在第二栅极腔130中的第二衬里134下方的第一衬里132。举例来说，第二蚀刻过程138可为如图1E中所描绘使用缓冲氢氟酸的稀释水溶液的湿式蚀刻过程138。第二湿式蚀刻过程138的过程参数(例如温度、缓冲氢氟酸溶液的强度及蚀刻时间)经选择以提供第一衬里132的保持于衬底102上在第二衬里134下方的所要量。
参考图1F，化学氧化过程140形成在衬底102的顶部表面处在第一栅极腔128中的第一氧化硅层142及在衬底102的顶部表面处在第二栅极腔130中的第二氧化硅层144。举例来说，化学氧化过程140可在150℃下使用硫酸与过氧化氢的水混合物，或可替代地在85℃下使用氢氧化铵与过氧化氢的水混合物。
参考图1G，第三蚀刻过程146移除图1F的在第一栅极腔128及第二栅极腔130中的第二衬里134。第三蚀刻过程146留下在第一栅极腔128中的适当位置中的实质上全部第一衬里132作为衬底102上的第一L形间隔件148，且留下在第二栅极腔130中的适当位置中的实质上全部第一衬里132作为衬底102上的第二L形间隔件150。举例来说，第三蚀刻过程146可为如图1G中所描绘在150℃到160℃下使用磷酸的水溶液的湿式蚀刻过程146。第三蚀刻过程146的过程参数(例如温度、磷酸溶液的强度及蚀刻时间)经选择以提供衬底102上的第一L形间隔件148及第二L形间隔件150的所要厚度。第一氧化硅层142及第二氧化硅层144在第三蚀刻过程146期间保护衬底102。
参考图1H，举例来说，随后使用缓冲氢氟酸的非常稀释水溶液移除第一氧化硅层142及第二氧化硅层144。第一L形间隔件148的横向部分沿着衬底102的表面从第一L形间隔件148的垂直部分向内延伸至少1纳米的距离152。类似地，第二L形间隔件150的横向部分沿着衬底102的表面从第二L形间隔件150的垂直部分向内延伸至少1纳米的距离154。
参考图1I，在衬底102上及在第一栅极腔128中的第一L形间隔件148上形成第一永久栅极电介质层156。举例来说，第一永久栅极电介质层156可包含具有高电介质常数的一或多种电介质材料，例如氧化铪及/或氧化锆。在衬底102上及在第二栅极腔130中的第二L形间隔件150上形成第二永久栅极电介质层158。第二永久栅极电介质层158还可包含具有高电介质常数的电介质材料，且可与第一永久栅极电介质层156同时形成。
在第一栅极腔128中的第一永久栅极电介质层156上形成第一替换栅极160。第一替换栅极160可包含一或多个栅极材料层(例如氮化钛、多晶硅、钛及铝)以提供适用于第一MOS晶体管104的所要功函数。
在第二栅极腔130中的第二永久栅极电介质层158上形成第二替换栅极162。第二替换栅极162可包含一或多个栅极材料层(例如氮化钛、多晶硅、钛及铝)以提供适用于第二MOS晶体管106的所要功函数。第二替换栅极162的层可不同于第一替换栅极160的层，从而反映用于第一MOS晶体管104的所要功函数与用于第二MOS晶体管106的所要功函数之间的差。
第一永久栅极电介质层156及第一替换栅极160叠置于第一L形间隔件148的接触衬底102的横向部分上。第一L形间隔件148沿着垂直表面垂直延伸且邻接第一永久栅极电介质层156。类似地，第二永久栅极电介质层158及第二替换栅极162叠置于第二L形间隔件150的接触衬底102的横向部分上。第二L形间隔件150沿着垂直表面垂直延伸且邻接第二永久栅极电介质层158。
图2A到图2F描绘用于集成电路100的替代制作序列。在本实例中，形成第一MOS晶体管104的第一替换栅极160，同时遮挡第二MOS晶体管106的第二牺牲栅极120。随后，形成第二MOS晶体管的第二替换栅极162，同时遮挡第一MOS晶体管104的第一替换栅极160。参考图2A，在第二牺牲栅极120上方形成第一栅极块164。举例来说，第一栅极块164可为一或多个二氧化硅及/或氮化硅层。随后，移除图1A的第一牺牲栅极112及第一牺牲栅极电介质层110以形成第一栅极腔128。
参考图2B，在本实例中，针对第一MOS晶体管104，在保护性电介质层126的顶部表面上保形地形成第一衬里132，从而延伸到第一栅极腔128中及第一栅极块164上方。在本实例中，还针对第一MOS晶体管104，在第一衬里132上保形地形成第二衬里134，从而延伸到第一栅极腔128中及第一栅极块164上方。图1D的各向异性第一蚀刻过程136从保护性电介质层126及第一栅极块164的顶部表面上方以及从第一栅极腔128的底部移除第二衬里134，而留下在第一衬里132的垂直表面上在第一栅极腔128中及可能在第一栅极块164上的第二衬里134。
参考图2C，如参考图1E到图1I所描述，形成第一MOS晶体管104的第一替换栅极160。第一衬里132的其余材料可保持于第一栅极块164上，如图2C中所描绘。随后，在完成第一替换栅极160的形成之后，移除第一栅极块164。
参考图2D，在第一MOS晶体管104的第一替换栅极160上方形成第二栅极块166。可与图2A的第一栅极块164类似地形成第二栅极块166。随后，移除图2C的第二牺牲栅极120及第二牺牲栅极电介质层118以形成第二栅极腔130。
参考图2E，在保护性电介质层126的顶部表面上保形地形成第二MOS晶体管106的第三衬里168，从而延伸到第二栅极腔130中及第二栅极块166上方。在本实例中，还针对第二MOS晶体管106，在第三衬里168上保形地形成第四衬里170，从而延伸到第二栅极腔130中及第一栅极块164上方。第二MOS晶体管106的第三衬里168可具有与第一MOS晶体管104的第一衬里132相同的厚度或可具有不同厚度。类似地，第二MOS晶体管106的第四衬里170可具有与第一MOS晶体管104的第二衬里134相同的厚度或可具有不同厚度。
类似于图1D的各向异性第一蚀刻过程136的各向异性第一蚀刻过程从保护性电介质层126及第二栅极块166的顶部表面上方以及从第二栅极腔130的底部移除第四衬里170，而留下在第三衬里168的垂直表面上在第二栅极腔130中及可能在第二栅极块166上的第四衬里170。
参考图2F，如参考图1E到图1I所描述，形成第二MOS晶体管106的第二替换栅极162。第三衬里168的其余材料可保持于第二栅极块166上，如图2F中所描绘。随后，在完成第二替换栅极162的形成之后，移除第二栅极块166。
尽管上文已描述本发明的各种实施例，但应理解，所述实施例仅通过实例而非限制的方式呈现。可在不背离本发明的精神或范围的情况下根据本文中的揭示内容对所揭示实施例做出众多改变。因此，本发明的广度及范围不应受上文所描述的实施例中的任一者限制。而是，本发明的范围应根据所附权利要求书及其等效物来界定。

Claims (14)

1.一种形成集成电路的方法，其包括以下步骤：
提供包括半导体的衬底；
移除安置于所述衬底上的第一牺牲栅极及第一牺牲栅极电介质层以在用于具有第一极性的第一MOS晶体管的区中形成第一栅极腔，且移除安置于所述衬底上的第二牺牲栅极及第二牺牲栅极电介质层以在用于具有第二相反极性的第二MOS晶体管的区中形成第二栅极腔；
在保护性电介质层上方邻近于所述第一栅极腔及所述第二栅极腔形成电介质材料的第一衬里，所述第一衬里延伸到所述第一栅极腔及所述第二栅极腔中；
在所述第一衬里上形成不同电介质材料的第二衬里，所述第二衬里延伸到所述第一栅极腔及所述第二栅极腔中；
从所述第一栅极腔及所述第二栅极腔的底部移除所述第二衬里，而留下在所述第一衬里的垂直表面上在所述第一栅极腔及所述第二栅极腔中的所述第二衬里；
从所述保护性电介质层的顶部表面以及从所述第一栅极腔及所述第二栅极腔的底部移除所述第一衬里以便暴露所述衬底；
移除所述第一栅极腔及所述第二栅极腔中的所述第二衬里，而留下在所述第一栅极腔中的适当位置中的所述第一衬里作为第一L形间隔件且留下在所述第二栅极腔中的适当位置中的所述第一衬里作为第二L形间隔件；
在所述衬底及所述第一栅极腔中的所述第一L形间隔件上形成第一永久栅极电介质层；
在所述衬底及所述第二栅极腔中的所述第二L形间隔件上形成第二永久栅极电介质层；
在所述第一永久栅极电介质层上形成第一替换栅极，所述第一永久栅极电介质层及所述第一替换栅极叠置于所述第一L形间隔件的接触所述衬底的一部分上；及
在所述第二永久栅极电介质层上形成第二替换栅极，所述第二永久栅极电介质层及所述第二替换栅极叠置于所述第二L形间隔件的接触所述衬底的一部分上。
2.根据权利要求1所述的方法，其中所述第一衬里为二氧化硅。
3.根据权利要求1所述的方法，其中所述第二衬里为氮化硅。
4.根据权利要求1所述的方法，其进一步包括以下步骤：在所述从所述第一栅极腔及所述第二栅极腔的所述底部移除所述第一衬里的步骤之后且在所述移除所述第二衬里而留下在适当位置中的所述第一衬里作为第一L形间隔件及作为第二L形间隔件的步骤之前，在所述衬底的顶部表面处在所述第一栅极腔及所述第二栅极腔中形成氧化硅层。
5.根据权利要求1所述的方法，其中：
所述第一MOS晶体管的栅极长度为26纳米到30纳米；
所述第二MOS晶体管的栅极长度为26纳米到30纳米；且
所述第一衬里的厚度为1纳米到4纳米。
6.根据权利要求1所述的方法，其中：
所述第一MOS晶体管的栅极长度为18纳米到22纳米；
所述第二MOS晶体管的栅极长度为18纳米到22纳米；且
所述第一衬里的厚度为1纳米到3纳米。
7.根据权利要求1所述的方法，其中：
所述第一MOS晶体管的栅极长度为12纳米到16纳米；
所述第二MOS晶体管的栅极长度为12纳米到16纳米；且
所述第一衬里的厚度为1纳米到2.5纳米。
8.一种形成集成电路的方法，其包括以下步骤：
提供包括半导体的衬底；
在用于具有第一极性的第一MOS晶体管的区中形成安置于所述衬底上的第一牺牲栅极电介质层；
在用于具有第二相反极性的第二MOS晶体管的区中形成安置于所述衬底上的第二牺牲栅极电介质层；
在所述第一牺牲栅极电介质层上形成第一牺牲栅极；
在所述第二牺牲栅极电介质层上形成第二牺牲栅极；
在所述衬底上方邻近于所述第一牺牲栅极及所述第二牺牲栅极形成保护性电介质层；
在所述第二牺牲栅极上方形成第一栅极块；
移除所述第一牺牲栅极及所述第一牺牲栅极电介质层以在用于所述第一MOS晶体管的所述区中形成第一栅极腔；
在所述保护性电介质层上方邻近于所述第一栅极腔形成电介质材料的第一衬里，所述第一衬里延伸到所述第一栅极腔中；
在所述第一衬里上形成不同电介质材料的第二衬里，所述第二衬里延伸到所述第一栅极腔中；
从所述第一栅极腔的底部移除所述第二衬里，而留下在所述第一衬里的垂直表面上在所述第一栅极腔中的所述第二衬里；
从所述保护性电介质层的顶部表面及从所述第一栅极腔的所述底部移除所述第一衬里以便暴露所述衬底；
移除所述第一栅极腔中的所述第二衬里，而留下在所述第一栅极腔中的适当位置中的所述第一衬里作为第一L形间隔件；
在所述衬底及所述第一栅极腔中的所述第一L形间隔件上形成第一永久栅极电介质层；
在所述第一永久栅极电介质层上形成第一替换栅极，所述第一永久栅极电介质层及所述第一替换栅极叠置于所述第一L形间隔件的接触所述衬底的一部分上；及
移除所述第一栅极块。
9.根据权利要求8所述的方法，其进一步包括以下步骤：
在所述第一替换栅极上方形成第二栅极块；
移除所述第二牺牲栅极及所述第二牺牲栅极电介质层以在用于所述第二MOS晶体管的所述区中形成第二栅极腔；
在所述保护性电介质层上方邻近于所述第二栅极腔形成电介质材料的第三衬里，所述第三衬里延伸到所述第二栅极腔中；
在所述第三衬里上形成不同电介质材料的第四衬里，所述第四衬里延伸到所述第二栅极腔中；
从所述第二栅极腔的底部移除所述第四衬里，而留下在所述第三衬里的垂直表面上在所述第二栅极腔中的所述第四衬里；
从所述保护性电介质层的所述顶部表面及从所述第二栅极腔的所述底部移除所述第三衬里以便暴露所述衬底；
移除所述第二栅极腔中的所述第四衬里，而留下在所述第二栅极腔中的适当位置中的所述第三衬里作为第二L形间隔件；
在所述衬底及所述第二栅极腔中的所述第二L形间隔件上形成第二永久栅极电介质层；
在所述第二永久栅极电介质层上形成第二替换栅极，所述第二永久栅极电介质层及所述第二替换栅极叠置于所述第二L形间隔件的接触所述衬底的一部分上；及
移除所述第二栅极块。
10.根据权利要求9所述的方法，其中：
所述第一衬里为二氧化硅；
所述第二衬里为氮化硅；
所述第三衬里为二氧化硅；且
所述第四衬里为氮化硅。
11.根据权利要求9所述的方法，其进一步包括以下步骤：
在所述从所述第一栅极腔的所述底部移除所述第一衬里的步骤之后且在所述移除所述第二衬里而留下在适当位置中的所述第一衬里作为第一L形间隔件的步骤之前，在所述衬底的顶部表面处在所述第一栅极腔中形成氧化硅层；及
在所述从所述第二栅极腔的所述底部移除所述第四衬里的步骤之后且在所述移除所述第四衬里而留下在适当位置中的所述第三衬里作为第二L形间隔件的步骤之前，在所述衬底的顶部表面处在所述第二栅极腔中形成氧化硅层。
12.根据权利要求9所述的方法，其中：
所述第一MOS晶体管的栅极长度为26纳米到30纳米；
所述第二MOS晶体管的栅极长度为26纳米到30纳米；
所述第一衬里的厚度为1纳米到4纳米；且
所述第三衬里的厚度为1纳米到4纳米。
13.根据权利要求9所述的方法，其中：
所述第一MOS晶体管的栅极长度为18纳米到22纳米；
所述第二MOS晶体管的栅极长度为18纳米到22纳米；且
所述第一衬里的厚度为1纳米到3纳米；且
所述第三衬里的厚度为1纳米到3纳米。
14.根据权利要求9所述的方法，其中：
所述第一MOS晶体管的栅极长度为12纳米到16纳米；
所述第二MOS晶体管的栅极长度为12纳米到16纳米；且
所述第一衬里的厚度为1纳米到2.5纳米；且
所述第三衬里的厚度为1纳米到2.5纳米。
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