CN110310933B - 半导体装置及半导体装置的制造方法 - Google Patents
半导体装置及半导体装置的制造方法 Download PDFInfo
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- CN110310933B CN110310933B CN201810907422.5A CN201810907422A CN110310933B CN 110310933 B CN110310933 B CN 110310933B CN 201810907422 A CN201810907422 A CN 201810907422A CN 110310933 B CN110310933 B CN 110310933B
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- semiconductor device
- semiconductor chip
- metal fiber
- heat dissipation
- semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 245
- 238000004519 manufacturing process Methods 0.000 title abstract description 23
- 238000000034 method Methods 0.000 title abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 93
- 239000002184 metal Substances 0.000 claims abstract description 93
- 239000000835 fiber Substances 0.000 claims abstract description 82
- 229920005989 resin Polymers 0.000 claims abstract description 82
- 239000011347 resin Substances 0.000 claims abstract description 82
- 230000017525 heat dissipation Effects 0.000 claims abstract description 41
- 238000007789 sealing Methods 0.000 claims abstract description 41
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims description 32
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 230000004048 modification Effects 0.000 description 36
- 238000012986 modification Methods 0.000 description 36
- 230000000052 comparative effect Effects 0.000 description 27
- 238000005304 joining Methods 0.000 description 19
- 238000010438 heat treatment Methods 0.000 description 15
- 238000007747 plating Methods 0.000 description 15
- 229910000679 solder Inorganic materials 0.000 description 12
- 239000010949 copper Substances 0.000 description 11
- 239000000853 adhesive Substances 0.000 description 10
- 230000001070 adhesive effect Effects 0.000 description 10
- 230000007613 environmental effect Effects 0.000 description 8
- 230000008646 thermal stress Effects 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 239000002390 adhesive tape Substances 0.000 description 5
- 239000002245 particle Substances 0.000 description 4
- 238000005245 sintering Methods 0.000 description 4
- 238000001721 transfer moulding Methods 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000001723 curing Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 244000043261 Hevea brasiliensis Species 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229920001577 copolymer Polymers 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000013035 low temperature curing Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920003052 natural elastomer Polymers 0.000 description 1
- 229920001194 natural rubber Polymers 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000005060 rubber Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229920003051 synthetic elastomer Polymers 0.000 description 1
- 239000005061 synthetic rubber Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
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- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
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- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Abstract
本发明的实施方式提供具有散热性能良好的封装的半导体装置及半导体装置的制造方法。本发明的实施方式的半导体装置具备第1半导体芯片、散热构件和密封树脂,上述散热构件被设置于上述第1半导体芯片的一个面上且与上述第1半导体芯片连接,所述密封树脂将上述第1半导体芯片及上述散热构件密封。上述散热构件包含交缠的金属纤维和热固化性树脂。
Description
关联申请
本申请享受以日本专利申请2018-53249号(申请日:2018年3月20日)作为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及半导体装置及半导体装置的制造方法。
背景技术
半导体装置的功能和性能的提高显著,输出的大电流化和高电压化等也在进展。因此,存在半导体装置的热损耗也变大的倾向。就这样的半导体装置而言,其封装的散热性能也需要提高。
发明内容
实施方式提供具有散热性能良好的封装的半导体装置及半导体装置的制造方法。
实施方式的半导体装置具备第1半导体芯片、散热构件和密封树脂,所述散热构件被设置于上述第1半导体芯片的一个面上且与上述第1半导体芯片连接,所述密封树脂将上述第1半导体芯片及上述散热构件密封。上述散热构件包含交缠的金属纤维和热固化性树脂。
附图说明
图1(a)是例示出第1实施方式的半导体装置的仰视图。图1(b)是图1(a)的AA线处的截面图。
图2是比较例的半导体装置的相当于图1(a)的AA线的位置处的截面图。
图3(a)~图3(c)是例示出第1实施方式的变形例的半导体装置的相当于图1(a)的AA线的位置处的截面图。
图4是例示出第2实施方式的半导体装置的相当于图1(a)的AA线的位置处的截面图。
图5(a)~图5(e)是表示图4的半导体装置的制造流程的概略的相当于图1(a)的AA线的位置处的截面图。
图6是例示出第2实施方式的变形例的半导体装置的相当于图1(a)的AA线的位置处的截面图。
图7(a)~图7(e)是表示图6的半导体装置的制造流程的概略的相当于图1(a)的AA线的位置处的截面图。
图8(a)~图8(d)是比较例的半导体装置的相当于图1(a)的AA线的位置处的截面图。
图9(a)~图9(g)是表示图8(b)的半导体装置的制造流程的概略的相当于图1(a)的AA线的位置处的截面图。
图10(a)~图10(f)是表示图8(d)的半导体装置的制造流程的概略的相当于图1(a)的AA线的位置处的截面图。
图11(a)是第3实施方式的半导体装置的相当于图1(a)的AA线的位置处的截面图。图11(b)是比较例的半导体装置的相当于图1(a)的AA线的位置处的截面图。
图12(a)是第3实施方式的变形例的半导体装置的相当于图1(a)的AA线的位置处的部分截面图。图12(b)是比较例的半导体装置的相当于图1(a)的AA线的位置处的部分截面图。
图13(a)是例示出第4实施方式的半导体装置的仰视图。图13(b)是图13(a)的BB线处的截面图。图13(c)是图13(a)的BB线处的截面图。
图14(a)是例示出比较例的半导体装置的仰视图。图14(b)是图14(a)的CC线处的截面图。图14(c)是图14(a)的CC线处的截面图。
图15(a)是例示出第4实施方式的变形例的半导体装置的正视图。图15(b)是例示出第4实施方式的变形例的半导体装置的侧视图。
图16(a)是例示出第5实施方式的半导体装置的俯视图。图16(b)是图16(a)的DD线处的截面图。
图17(a)是例示出第5实施方式的变形例的半导体装置的立体图。图17(b)是图17(a)的EE线处的截面图。
图18(a)是例示出第5实施方式的其他变形例的半导体装置的仰视图。图18(b)是图18(a)的FF线处的截面图。
具体实施方式
以下,一边参照附图对本发明的实施方式一边进行说明。
另外,附图是示意性或概念性的图,各部分的厚度与宽度的关系、部分间的大小的比率等不一定限于与现实的情况相同。另外,即使是表示相同部分的情况下,根据附图而彼此的尺寸或比率有时也不同地被表示。
另外,在本申请说明书和各图中,对于与关于已经叙述的图在之前叙述的要素同样的要素,标注相同的符号而适当省略详细的说明。
(第1实施方式)
图1(a)是例示出本实施方式的半导体装置的仰视图。图1(b)是图1(a)的AA线处的截面图。
如图1(a)及图1(b)中所示的那样,本实施方式的半导体装置10具备半导体芯片11、散热器12和密封树脂18。半导体装置10进一步具备虚设芯片13、接合构件14、基板15、接合线16和连接端子17。该例的半导体装置10是带散热器的BGA(Ball Grid Array,球栅阵列)封装。作为带散热器的封装,并不限于BGA,也可以适用于LGA(Land Grid Array,平面栅格阵列)、SOP(Small Outline Package,小外形封装)、QFP(Quad Flat Package,方型扁平式封装)、QFN(Quad For Non-lead package,方形无引线封装)、DFN(Dual For Non-leadpackage,双引线封装)等中。
以下,包含X轴及与X轴正交的Y轴的平面设定为与半导体芯片11的第1面11a大致平行的面。Z轴与X轴及Y轴正交。例如,在以下所示的截面图中,Z轴的正方向为图中的上方。
散热器12隔着虚设芯片13按照变得与第1面11a大致平行的方式被设置于半导体芯片11的第1面11a一侧。第1面11a为半导体芯片11的一个面,是设置有连接接合线16的一端的连接垫的面。
虚设芯片13是不具有任何功能的、例如由硅(Si)等形成的芯片。虚设芯片13按照变得与第1面11a平行的方式被设置。在XY俯视下,虚设芯片13的面积被设定为小于半导体芯片11的面积,其外周包含在第1面11a的外周中。半导体芯片11的连接垫按照将虚设芯片13的外周的外侧围绕的方式设置。
虚设芯片13使用粘接构件13a被连接在半导体芯片11的第1面11a上。虚设芯片13是在使连接于第1面11a的接合线16按照向Z轴的正方向变凸的方式成型为环状的情况下,为了按照接合线16的环状的部分不与散热器12接触的方式保留半导体芯片11与散热器12之间的距离而设置的间隔物。
在半导体芯片11与散热器12之间,也可以设置具有与半导体芯片11不同功能的半导体芯片来代替虚设芯片13。
散热器12例如是具有半导体芯片11的面积以上的面积的大致方形的片材构件。在XY俯视下,散热器12的面积例如大于半导体芯片11的面积,在XY俯视下,散热器12的外周将半导体芯片11的外周全部包含在内。
散热器12由包含含有铜(Cu)或Cu合金的金属纤维和热固化性树脂的金属纤维片材(以下也仅称为金属纤维片材)形成。金属纤维是例如纤维直径为1μm~20μm左右、纤维长度为1mm~10mm左右等的具有高长宽比的金属材料交缠而成的。所谓交缠表示金属纤维彼此缠绕的状态。关于金属纤维,从低热电阻或高导电率的观点出发,Cu的含有率优选为100%,但Cu的含有率也可以低于100%。
热固化性树脂被含浸于金属纤维中。热固化性树脂例如为热固化性的粘接剂,优选具有导电性。在热固化性粘接剂的情况下,作为橡胶成分,可以使用丙烯腈-丁二烯共聚物(NBR)等合成橡胶或天然橡胶。作为粘合剂树脂,可以使用环氧树脂或酚醛树脂等。在环氧树脂的情况下,作为固化温度可以设定为100℃左右~160℃左右。另外,通过使用各种金属粉等作为导电性填料,能够提高导电性。
散热器12为使含浸有热固化性树脂的金属纤维交缠而成的金属纤维片材,如后面详细叙述的那样,通过将金属纤维片材切成规定的形状及大小而形成。
像这样,散热器12包含热固化性树脂。因此,在虚设芯片13上载置散热器12后,通过进行加热,散热器12能够与虚设芯片13连接。
半导体芯片11介由接合构件14被连接于基板15上。接合构件14例如为银(Ag)糊剂。被设置于第1面11a上的连接垫介由接合线16与基板15上的连接垫电连接。基板15上的连接垫通过设置于基板15上及基板15内的布线而与连接端子17电连接。连接端子17例如为钎焊球。
为了保护包含半导体芯片11的内部结构免受外部环境伤害,半导体装置10用密封树脂18密封。在该例中,除了基板15的侧面、下表面及连接端子17以外,密封树脂18将整体密封。
对于本实施方式的半导体装置10的效果,一边与比较例的半导体装置比较一边进行说明。
图2是比较例的半导体装置的相当于图1(a)的AA线的位置处的截面图。
如图2中所示的那样,比较例的半导体装置110具有半导体芯片11、散热器112和密封树脂18。散热器112是由块状的Cu或Cu合金形成的片材。在比较例的情况下,散热器112介由虚设芯片13被连接于半导体芯片11上。散热器112介由粘接构件13b与虚设芯片13连接。虚设芯片13介由粘接构件13a与半导体芯片11连接。即,虚设芯片13需要在其两面上涂布粘接构件13a、13b。在例如为了粘接而使用粘接胶带的情况下,在虚设芯片13的两面预先贴附粘接胶带。
另外,在比较例的情况下,在填充密封树脂18的情况下,需要使散热器112与密封树脂18充分地密合。因此,散热器112例如需要预先对其各面实施粗化处理。
与此相对,在本实施方式的半导体装置10中,由于散热器12包含交缠的金属纤维,所以对于散热器12的各面来说,被所交缠的金属纤维实质性粗面化。因此,与密封树脂18的连接面积变广,密合性提高。由于可抑制散热器12与密封树脂18因将半导体装置10安装于装置等上的情况的热应力而剥离,所以能够使耐环境性等可靠性提高。
进而,在本实施方式的半导体装置10中,由于散热器12的与密封树脂18的连接面被实质性粗面化,与密封树脂的连接面积增大,所以热电阻降低,散热性能提高。
另外,在本实施方式的半导体装置10中,由于散热器12包含热固化性树脂,所以不用另外设置粘接构件,通过施加热处理即可与虚设芯片13连接。因此,能够削减粘接剂或粘接胶带,同时能够削减在虚设芯片13的两面涂布粘接剂的工序的一部分。
(变形例)
散热器由于能够设定为任意的形状或厚度,所以可以根据必要的散热性能来设计散热器。另外,通过变更散热器的构成,能够进一步削减构件。
图3(a)~图3(c)是例示出本变形例的相当于图1(a)的AA线的位置处的截面图。
上述的实施方式的构成也可以适用于带散热器的QFN、DFN、QFP、SOP等中。图3(a)~图3(c)是适用于QFN(或DFN)的例子。
如图3(a)中所示的那样,半导体装置10a具备半导体芯片11和散热器12。在半导体芯片11与散热器12之间设置有虚设芯片13,半导体芯片11与虚设芯片13通过粘接胶带等粘接构件13a而被连接。散热器12通过含浸于散热器12中的热固化性树脂而与虚设芯片13连接。在该例中,半导体芯片11的第1面11a的相反侧的面例如介由Ag糊剂等接合构件14而与模具衬垫(die pad)15a连接。半导体芯片11上的电极垫介由接合线16而与作为平导线(flat lead)的连接端子17a电连接。
如图3(b)中所示的那样,虚设芯片13也可以与散热器12b置换。即,半导体装置10b具备半导体芯片11和散热器12、12b。散热器12b被设置于半导体芯片11与散热器12之间。散热器12b作为保留半导体芯片11与散热器12之间的Z轴方向的距离而防止接合线16与散热器12接触的间隔物发挥功能。散热器12、12b均由金属纤维片材形成。金属纤维片材包含热固化性树脂。因此,与虚设硅置换后的散热器12b与半导体芯片11的第1面11a可以不使用粘接胶带等而通过进行加热处理来进行。
另外,由于散热器12b包含Cu等金属纤维,所以与硅(Si)等虚设芯片13相比热导率高,从半导体芯片11到散热器12为止的热电阻降低,散热性能进一步提高。
如图3(c)中所示的那样,在半导体装置10c中,没有设置虚设芯片等,在半导体芯片11上直接连接有散热器12c。散热器12c的与XY平面平行的面的外周按照包含在半导体芯片11的第1面11a的外周中的方式被设定。更具体而言,散热器12c的外周被连接于比配置于第1面11a上的连接垫更靠内侧。散热器12的与XY平面平行的面的面积被设定为小于半导体芯片11的面积。
由金属纤维片材形成的散热器可以任意地设定其厚度。因此,如该变形例那样,可以将散热器12c的厚度设定为上述的实施方式或变形例的散热器及虚设芯片的合计厚度左右。因此,散热器12c能够避免与接合线16接触。
像这样操作,在变形例中,与比较例的情况相比能够降低构成要素的数目。通过使如该变形例那样的散热器12c的厚度变厚,还能够降低散热器12c的热电阻,提高封装的散热性能。
上述内容中,在半导体芯片11与模具衬垫15a的连接中,也可以将Ag糊剂等接合构件与散热器中使用的金属纤维片材置换。
(第2实施方式)
在将半导体芯片与模具衬垫连接的情况下,通过在半导体芯片与模具衬垫之间使用含浸有热固化性树脂的金属纤维片材来代替使用Ag糊剂等接合构件,能够使散热性能提高。
图4是例示出本实施方式的半导体装置的相当于图1(a)的AA线的位置处的截面图。
如图4中所示的那样,本实施方式的半导体装置210具备半导体芯片11、接合构件214和模具衬垫15a。接合构件214被设置于半导体芯片11与模具衬垫15a之间。半导体芯片11在背面(第2面)11b介由接合构件214与模具衬垫15a连接。
接合构件214包含金属纤维片材。金属纤维片材含浸有热固化性树脂。金属纤维片材与上述的其它实施方式和其变形例的散热器同样地构成。即,金属纤维片材包含含有Cu或Cu合金的交缠的金属的纤维、且含浸有热固化性树脂。
由于接合构件214以交缠的状态包含使用了Cu等高热传导金属材料的金属纤维,所以热导率高,因此能够减小半导体装置210的热电阻。由于金属纤维片材不包含铅(Pb),所以半导体装置210可以制成无Pb的封装。由于接合构件214的热固化性树脂能够在较低温度下固化,所以能够减轻半导体装置210的制造时的热应力,能够提高半导体装置210的耐环境性。
图5(a)~图5(e)是例示出图4的半导体装置的制造工序的截面图。
如图5(a)中所示的那样,准备引线框15LF。引线框15LF包含成为模具衬垫15a的部分和成为连接端子17a的部分。
如图5(b)中所示的那样,对于半导体芯片11及接合构件214来说,由贴附于金属纤维片材214SH上的半导体晶片11WF被单片化。例如,在金属纤维片材214SH上载置半导体晶片11WF,从半导体晶片11WF的侧被加热。由此,金属纤维片材214SH与半导体晶片11WF连接。之后,半导体芯片11在背面贴附有接合构件214的状态下被切取而被单片化。
单片化后的半导体芯片11及接合构件214被载置于引线框15LF的成为模具衬垫的部分上。
例如,接合构件214的厚度被设定为100μm左右,但金属纤维片材214SH及接合构件214的厚度并不限定于此,根据封装的散热性能而设定。
如图5(c)中所示的那样,通过从引线框15LF侧进行加热至热固化性树脂的固化温度而使热固化性树脂固化,从而将半导体芯片11与引线框15LF的模具衬垫部分连接。
如图5(d)中所示的那样,将半导体芯片11上的连接垫介由接合线16与引线框15LF的成为连接端子的部分连接。
如图5(e)中所示的那样,通过传递模塑等而填充密封树脂,将引线框15LF切断。
图6是例示出本变形例的半导体装置的相当于图1(a)的AA线的位置处的截面图。
如上述的其它实施方式的情况中说明的那样,含浸有热固化性树脂的金属纤维片材可以任意地设定厚度。在第2实施方式中,通过使切取金属纤维片材而形成的接合构件的厚度变厚,能够进一步降低热电阻。
如图6中所示的那样,半导体装置210a具备接合构件214a。接合构件214a被设置于半导体芯片11与模具衬垫15a之间。接合构件214a由具有充分厚度的金属纤维片材切取而使用。接合构件214a的厚度例如比半导体芯片11的厚度厚。通过使接合构件214a厚度充分厚,能够实现所期望的低热电阻(瞬态热电阻)。例如,接合构件214a的厚度可以设定为500μm左右。
另外,接合构件214a的与XY平面平行的面的面积也可以任意地设定。在该例中,接合构件214a的面积被设定为大于半导体芯片11的面积。因此,能够降低接合构件214a的热电阻,能够进一步提高半导体装置210a的散热性能。
图7(a)~图7(e)是例示出图6的半导体装置的制造工序的截面图。
如图7(a)中所示的那样,准备引线框15LF。该引线框15LF也可以与第2实施方式的情况的引线框15LF相同。
如图7(b)中所示的那样,所切取的接合构件214a被载置于引线框15LF的模具衬垫部分上。接合构件214a及引线框15LF通过加热而将接合构件214a与引线框15LF暂时连接。所谓暂时连接是指为了在下一工序以后将接合构件214a与引线框15LF连接而暂时地固定。
这里,如图7(b)的右图中所示的那样,接合构件214a由含浸有热固化性树脂的金属纤维片材214aSH切取成规定的形状。金属纤维片材214aSH例如被设定为第2实施方式的情况的5倍左右的厚度(500μm)。与XY平面平行的面的面积被设定为大于半导体芯片11的面积。
如图7(c)中所示的那样,在接合构件214a上载置半导体芯片11,通过加热而将半导体芯片11、接合构件214a及引线框15LF分别相互连接。
如图7(d)中所示的那样,将半导体芯片11与连接端子17a用接合线16连接。
如图7(e)中所示的那样,通过传递模塑等而填充树脂,将引线框15LF切断。
像这样,在本变形例中,通过适当地设定接合构件214a的厚度及面积,能够容易地降低封装的热电阻。
像这样,在本实施方式及其变形例的半导体装置210、210a中,主要的工序数可以设定为5个工序。
对于本实施方式及变形例的半导体装置的效果,一边与比较例的半导体装置比较一边进行说明。
图8(a)~图8(d)是比较例的半导体装置的相当于图1(a)的AA线的位置处的截面图。
如图8(a)中所示的那样,在比较例的半导体装置210s中,在半导体芯片11与模具衬垫15a之间具有接合构件214s。接合构件214s为一般所使用的接合构件,为Ag糊剂等。由于Ag糊剂的热导率低,所以半导体装置210s的热电阻变高,散热性能低。
如图8(b)中所示的那样,半导体装置210s1具有金属板211s。将具有Cu等高热导率的金属板211s设置于半导体芯片11与模具衬垫15a之间。金属板211s介由接合构件214us与半导体芯片11连接,介由接合构件214bs与模具衬垫15a连接。
金属板211s作为散热器发挥功能。即,通过将对于半导体芯片11的发热为低热电阻的金属板211s追加到热的传导经路中,从而使散热性能提高。
如图8(c)中所示的那样,半导体装置210s2具有接合构件214sh。在该比较例的接合构件214sh中,通过增加接合构件中的热传导粒子、例如Ag粒子的含量,从而接合构件214sh的热电阻降低。
如图8(d)中所示的那样,半导体装置210s3具有接合构件214ss。接合构件214ss是通过将Ag粒子等热传导粒子进行烧结处理(sintering)而使热导率提高、降低了热电阻的构件。
就接合构件214sh、214ss那样的具有高热导率的接合构件而言,对于与半导体芯片或模具衬垫的连接处理需要高温的加热处理。
图9(a)~图9(g)是表示图8(b)的半导体装置的制造流程的概略的相当于图1(a)的AA线的位置处的截面图。
如图9(a)中所示的那样,准备引线框15LF,如图9(b)中所示的那样,在引线框15LF的模具衬垫部分涂布接合构件214bs。
如图9(c)中所示的那样,在接合构件214bs上载置金属板211s,如图9(d)中所示的那样,在金属板211s上涂布接合构件214us。
如图9(e)中所示的那样,在接合构件214us上载置半导体芯片11。
如图9(f)中所示的那样,将半导体芯片11与成为连接端子的部分之间利用接合线16而连接。
如图9(g)中所示的那样,通过传递模塑等而填充树脂,将引线框15LF切断。
像这样,在附带用于低热电阻化的金属板211s的封装的情况下,因追加金属板211s而工序数增加,主要的工序变成7个工序。
图10(a)~图10(f)是表示图8(d)的半导体装置的制造流程的相当于图1(a)的AA线的位置处的截面图。
如图10(a)中所示的那样,准备引线框15LF,如图10(b)中所示的那样,在引线框15LF的模具衬垫部分涂布接合构件214ss1。
如图10(c)中所示的那样,在接合构件214ss1上载置半导体芯片11后,如图10(d)中所示的那样,进行用于低热电阻化的烧结处理,获得热导率得以改善的接合构件214ss。烧结处理为长时间的高温固化处理,例如,在Ag糊剂的情况下,在不活泼性气体气氛中、250℃下进行90分钟左右。
如图10(e)中所示的那样,将半导体芯片11与成为连接端子的部分之间利用接合线16而连接,如图10(f)中所示的那样,通过传递模塑等而填充树脂,将引线框15LF切断。
像这样,在比较例的情况下,由于为了低热电阻化而追加了Ag糊剂的烧结处理,所以主要工序数变成6个工序。在Ag糊剂的烧结工序中,需要进行高温长时间的加热处理,制造的产量降低。
与此相对,在本实施方式及其变形例中,通过使用由金属纤维片材形成的接合构件214,能够将主要工序数削减为5个工序。为了低热电阻化,与需要6个工序或7个工序的比较例的情况相比能够缩短制造工序。
在本实施方式及变形例的半导体装置中,接合构件214由金属纤维片材形成。因此,通过金属纤维的高热传导性,能够容易地实现低热电阻化。热电阻值也通过适当地设定接合构件214的面积及厚度而能够容易地实现所期望的值。
另外,由于接合构件214的金属纤维不包含Pb,所以半导体装置210、210a能够设定为无Pb。
接合构件214包含热固化性树脂。由于热固化性树脂具有低温固化特性,所以通过短时间的热处理能够将半导体芯片11与模具衬垫15a连接。因此,能够降低半导体装置的制造时的热应力,提高耐环境性等。
(第3实施方式)
含浸有热固化性树脂的金属纤维片材也可以形成为引线框状而作为模具衬垫或连接端子使用。
图11(a)是本实施方式的半导体装置的相当于图1(a)的AA线的位置处的截面图。图11(b)是比较例的半导体装置的相当于图1(a)的AA线的位置处的截面图。
如图11(a)中所示的那样,半导体装置310具备半导体芯片11和模具衬垫315。半导体芯片11被连接于模具衬垫315上。模具衬垫315通过与连接端子317一起将由含浸有热固化性树脂的金属片材切取的引线框切断而形成。
由于模具衬垫315包含金属纤维,所以为低热电阻。通过调整模具衬垫315的厚度,能够实现所期望的低热电阻值。
另外,由于模具衬垫315包含热固化性树脂,所以能够在不使用接合构件、且不进行长时间的加热处理的情况下连接半导体芯片11。由于金属纤维不包含Pb,所以半导体装置310可以设定为无Pb。
进而,模具衬垫315及连接端子317的表面被金属纤维实质性粗面化,能够提高与密封树脂18的密合性。通过模具衬垫315及连接端子317与密封树脂18的密合性提高,即使是向装置中的安装时的热应力等也不易产生剥离等不良情况,能够提高耐环境性等。
如图11(b)中所示的那样,在比较例的半导体装置310s中,半导体芯片11介由接合构件314s被连接于例如包含Cu的模具衬垫315s上。在接合构件314s为Ag糊剂等的情况下,热电阻高,半导体装置310s的散热性能低。通过将Ag糊剂变更为软钎料等,可改善热电阻,但存在无Pb化困难的情况。
另外,在比较例的半导体装置310s中,模具衬垫315s及连接端子317s具有切口部315bs、317bs。切口部315bs、317bs遍及各自的外周而设置于模具衬垫315s及连接端子317s的下表面侧、即与搭载有半导体芯片11的面相反侧的面的侧。在填充有密封树脂的情况下,由于密封树脂18蔓延至切口部315bs、317bs中,所以使模具衬垫315s及连接端子317s与密封树脂18的密合性提高。通过模具衬垫315s及连接端子317s与密封树脂18的密合性提高,从而防止模具衬垫315s及连接端子317s从密封树脂18脱落。
但是,由于这样的切口部315bs、317bs通过将引线框进行蚀刻而形成,所以需要处理时间,成为高成本化的主要原因。
在本实施方式的半导体装置310中,由于模具衬垫315及连接端子317由金属纤维片材形成,所以模具衬垫315及连接端子317的面被金属纤维实质性粗面化,与密封树脂的密合性提高。因此,能够在不对金属纤维片材实施特殊的加工的情况下实现与密封树脂的密合性高的半导体装置310。
另外,模具衬垫315可以通过含浸于金属纤维中的热固化性树脂而不介由接合构件与半导体芯片11连接。因此,能够使半导体装置310的制造工序比比较例的情况简化。
(变形例)
图12(a)是本变形例的半导体装置的相当于图1(a)的AA线的位置处的部分截面图。图12(b)是比较例的半导体装置的相当于图1(a)的AA线的位置处的截面图。
在该变形例中,在模具衬垫及连接端子的一部分上设置有含浸有热固化性树脂的金属纤维片材。
如图12(a)中所示的那样,本变形例的半导体装置310a具备模具衬垫315a、连接端子317a和密封树脂18。在模具衬垫315a及连接端子317a的表面分别设置有镀层315b、317b。在模具衬垫315a的镀层315b与密封树脂18之间设置有金属纤维层319。在连接端子317a的镀层317b与密封树脂18之间也设置有金属纤维层319。金属纤维层319是含浸有热固化性树脂的金属纤维片材的层。
在本变形例中,按照具有镀层315b的模具衬垫315a及具有镀层317b的连接端子317a与密封树脂18充分地密合的方式,在这些连接部分上设置有金属纤维层319。金属纤维层319没有被设置于连接端子317a中的为了与外部电路连接而露出的部分上。
在连接端子317a的向外部露出的部分上,例如从基材的表面侧起依次层叠有镍(Ni)、钯(Pd)及金(Au)的镀层317b。通过形成高稳定的金属的镀层315b、317b层,即使是包含助焊剂等的外部环境也能够实现高可靠性的连接状态。
金属纤维层319在例如预先与密封树脂连接的部分,被选择性地贴附于模具衬垫315a及连接端子317a的表面。在连接端子317a的露出到外部部分上,没有贴附金属纤维层319,Au等金属镀层露出。
如图12(b)中所示的那样,比较例的半导体装置310sa在模具衬垫315a及连接端子317a的整面上在初期实施了例如Ni、Pd、Au的多层镀覆,但在与密封树脂18连接的部分,为了确保与密封树脂的密合性而被粗化至Ni层左右。因此,变成在模具衬垫315a及连接端子317a的表面形成有被粗化的镀层315c、317c。在与密封树脂18的连接部分中,通过被粗化的镀层315c、317c来确保密合性,但由于连接端子317a的露出面的镀层317c也被粗化,所以可能因长时间曝露于外部环境中而产生连接强度或软钎料润湿性等的劣化。
在本变形例中,通过选择性地设置金属纤维层319,模具衬垫315a及连接端子317a能够确保与密封树脂18的密合性,并且维持用于外部连接的镀层317b。
因此,模具衬垫315a及连接端子317a不会因用于与外部电路连接的基板安装时等的热应力而与密封树脂18剥离,能够使耐环境性提高。模具衬垫315a及连接端子317a通过与密封树脂18的连接面积扩大,从而可期待向密封树脂18的热传导提高、有助于热电阻的提高。
另外,在露出到外部的连接端子317a的表面,高稳定的镀层317b露出,通过镀层317b,与形成于外部电路的基板上的连接焊盘(connection land)等也能够以高可靠性连接。
(第4实施方式)
在具有外部露出电极的半导体装置中,通过将金属纤维片材贴附于外部露出电极上,能够降低基板安装时的热电阻。
图13(a)是例示出本实施方式的半导体装置的仰视图。图13(b)及图13(c)是图13(a)的BB线处的截面图。
在图13(b)及图13(c)中,与半导体装置410一起还一并示出了安装半导体装置410的基板430。
如图13(a)~图13(c)中所示的那样,半导体装置410在底面设置有追加的露出电极411。追加的露出电极411被贴附于兼作模具衬垫的露出电极415的露出面上。追加的露出电极411的外周按照将露出电极415的外周包含在内的方式设置。追加的露出电极411的面积按照变得大于露出电极415的与XY平面平行的面的面积的方式被设定。
在露出电极415上,介由接合构件414而设置有半导体芯片11。接合构件414例如可以是软钎料,也可以是金属纤维片材。
半导体装置410可以通过描绘于基板430上的布线图案432而与外部电路连接。基板430为PCB(Printed Circuit Board,印刷电路板),在基板430上,除了布线图案432以外还设置有散热图案431。散热图案431具有大于布线图案432的面积。散热图案431也可以在基板430上的任一处与任一布线图案432连接。
基板430由例如聚酰亚胺系树脂、玻璃环氧、各种陶瓷等绝缘材料形成。散热图案431及布线图案432是在基板430上或以基板430通过蚀刻等而形成的Cu等良导体。
该例的散热图案431与追加的露出电极411的外周形状及面积相匹配地设置。在布线图案432中设置有焊盘(land),在焊盘上施加有预备的软钎料433。
半导体装置410在散热图案431上直接连接有追加的露出电极411。与连接端子417通过软钎料433而连接。
对于本实施方式的半导体装置的效果,一边与比较例的半导体装置比较一边进行说明。
图14(a)是例示出比较例的半导体装置的仰视图。图14(b)及图14(c)是图14(a)的CC线处的截面图。
如图14(a)~图14(c)中所示的那样,比较例的半导体装置410s具有露出电极415,露出到外部。在露出电极415上,隔着接合构件414而设置有半导体芯片11。
在基板430s上,设置有散热图案431s及布线图案432。在散热图案431s及布线图案432上,均施加有预备的软钎料433。
半导体装置410s的露出电极415及连接端子417介由软钎料433,分别与散热图案431s及布线图案432连接。软钎料433可以根据其润湿性而稍微扩展,但难以扩展至充分地将散热经路扩大的程度。因此,由于散热图案431s的面积无法充分大于露出电极415的面积,所以就比较例的半导体装置410s而言,由散热图案431s的扩大带来的散热性能提高不能说是充分的。
与此相对,在本实施方式的情况下,在露出电极415与散热图案431之间设置有追加的露出电极411,追加的露出电极411的外周形状及面积可以充分大于露出电极415。由于追加的露出电极411由金属纤维片材形成,热导率高,所以安装于基板430上的半导体装置410能够实现低的热电阻。因此,在将半导体装置410安装于基板430上的情况下,能够使散热图案431的外周形状及面积大于露出电极415,能够使基板安装时的半导体装置410的散热性能提高。
(变形例)
图15(a)是例示出本变形例的半导体装置的正视图。图15(b)是例示出本变形例的半导体装置的侧视图。
在具有露出电极的半导体装置中,并不限于表面安装封装,也可以适用于SIP(Single Inline Package,单列直插式封装)、ZIP(Zigzag Inline Package,交错直插式封装)等引线插入类型的封装。
如图15(a)及图15(b)中所示的那样,半导体装置410a具备本体410a1和追加的散热片411a。追加的散热片411a被贴附于兼作模具衬垫的散热片415a上。追加的散热片411a的外周将散热片415a的外周包含在内,追加的散热片411a的面积大于散热片415a的面积。追加的散热片411a在本体的安装时被设置于散热片415a与筐体440的壁面440a之间。
追加的散热片411a由金属纤维片材形成。追加的散热片411a通过金属纤维片材的热固化性树脂与本体410a1的散热片415a连接。
半导体装置410a通过追加的散热片411a的热固化性树脂与壁面440a连接。为了提高振动时的连接强度,例如也可以通过贯通本体410a1、追加的散热片411a及筐体440的螺栓和螺母等紧固而固定。
半导体装置410a的连接端子417a被插入至基板430的焊盘孔(land hole)中而被软钎焊。
另外,也可以将追加的散热片自身作为筐体440的壁面使用。
像这样,即使是独立安装型的半导体装置的情况下,也可以通过在本体的散热片415a与壁面440a之间设置追加的散热片411a,从而降低半导体装置410a的热电阻,使散热性能提高。
在可以将半导体装置410a的壁面440a上的螺旋夹省略的情况下,通过对追加的散热片411a的热固化性树脂进行加热,从而半导体装置410a能够容易地被安装到筐体440上。
(第5实施方式)
图16(a)是例示出第5实施方式的半导体装置的俯视图。图16(b)是图16(a)的DD线处的截面图。
如图16(a)及图16(b)中所示的那样,本实施方式的半导体装置510具备半导体芯片11和布线构件516。半导体装置510进一步具备模具衬垫515及连接端子517a、517b。
布线构件516由含浸有热固化性树脂的金属纤维片材形成。布线构件516的一端516t1与半导体芯片11的连接垫连接。布线构件516在一端516t1与另一端516t2之间向Z轴的负方向弯曲。布线构件516的另一端516t2与连接端子517a连接。模具衬垫515及连接端子517的下表面包含于同一平面内。半导体芯片11介由接合构件514在第1面11a的相反的面(第2面11b)与模具衬垫515连接。接合构件514由含浸有热固化性树脂的金属纤维片材形成。
半导体芯片11的另一连接垫介由接合线16与连接端子517b电连接。
半导体芯片11是例如具有MOFET(Metal-Oxide-Semiconductor Field-EffectTransistor,金属-氧化物半导体场效应晶体管)那样的背面电极的分立元件。在半导体芯片11为MOSFET的情况下,模具衬垫515成为漏极电极,连接端子517a成为源极端子,连接端子517b成为栅极端子。
在本实施方式的半导体装置510中,由于布线构件516包含热固化性树脂,所以在与半导体芯片11或连接端子517a的连接中不需要高温的软钎料接合工艺,可以在低温下进行加热压接。
另外,由于布线构件516包含金属纤维,所以能够实现高的导电率,半导体装置510的低损耗化成为可能。
由于布线构件516的表面被金属纤维实质性粗面化,所以通过与密封树脂18的密合性提高,从而耐环境性提高,并且散热性能提高。
由于在半导体芯片11与模具衬垫515的连接中也使用由金属纤维片材形成的接合构件514,所以能够在低温下封装装配。因此,就半导体装置410而言,能够将制造线简化。
在半导体装置410的制造中,由于不使用软钎料和Pb,所以能够容易地设定为无Pb。
(变形例1)
图17(a)是例示出本变形例的半导体装置的立体图。图17(b)是图17(a)的EE线处的截面图。
在图17(a)中,将密封树脂的部分抽象而示意性地进行表示。
如图17(a)及图17(b)中所示的那样,在本变形例的半导体装置510a中,布线构件516a并列地使用了多根。半导体芯片11通过接合构件514与模具衬垫515连接。接合构件514例如为软钎料或金属纤维片材。各布线构件516a通过一端516at1与半导体芯片11上的连接垫连接,通过另一端516at2与连接端子517a连接。
布线构件516a由含浸有热固化性树脂的金属纤维片材形成。通过多个布线构件516a,能够降低半导体芯片11与连接端子517a之间的直流电阻值。因此,在半导体装置510a中,能够增大输出的电流容量,降低电力损耗。
与上述的其它实施方式的情况同样地,由于布线构件516a包含热固化性树脂,所以通过低温的加热处理,能够与半导体芯片11及连接端子517a连接。因此,能够降低制造时的热应力而使半导体装置510a的耐环境性提高。
(变形例2)
图18(a)是例示出本变形例的半导体装置的仰视图。图18(b)是图18(a)的FF线处的截面图。
在图18(b)中,还一并示出了安装半导体装置510b的基板530。
如图18(a)及图18(b)中所示的那样,在本变形例中,半导体装置510b具备半导体芯片11和多个布线构件516b。半导体芯片11的第1面11a朝向下方、即Z轴的负方向。布线构件516b通过一端516bt1与第1面11a连接。如后述那样,另一端516bt2作为与外部电路的连接端子发挥功能。布线构件516b的根数例如优选设定为3根以上的多根。布线构件516b也可以如该例那样按照将第1面11a的外周部分围绕的方式设置。
布线构件516b通过一端516bt1与第1面11a上的连接垫连接,在一端516bt1与另一端516bt2之间朝向Z轴的负方向弯曲。全部布线构件516b的另一端516bt2的底面包含于与同一XY平面平行的面中。
布线构件516b由含浸有热固化性树脂的金属纤维片材形成。一端516bt1通过加热处理与设置于第1面11a上的连接垫连接。
另一端516bt2通过加热处理与用于连接外部电路的设置于基板530上的布线图案531的焊盘连接。
在本实施方式的半导体装置510b中,具备由金属纤维片材形成的多根的布线构件516b。多根布线构件516b通过一端516bt1与半导体芯片11连接,通过另一端516t2与基板530连接。因此,布线构件516形成从半导体芯片11散热的经路,能够高效地向基板530散热。
利用布线构件516b的热固化性树脂,能够在低温下容易地与半导体芯片11及基板530连接,能够降低半导体装置510的制造时的热应力。
在布线构件516b中,实现了利用金属纤维进行的粗面化,与密封树脂的密合性提高。另外,由于能够将布线构件516b的另一端516t2通过低温的加热处理而进行基板安装,所以基板安装时的热应力降低,能够防止树脂剥离等,能够提高耐环境性。
根据以上说明的实施方式,能够实现具有散热性能提高的封装的半导体装置及半导体装置的制造方法。
以上,对本发明的几个实施方式进行了说明,但这些实施方式是作为例子提出的,并不意图限定发明的范围。这些新型的实施方式可以以其他各种方式实施,在不脱离发明的主旨的范围内,可以进行各种省略、置换、变更。这些实施方式和其变形包含于发明的范围和主旨中,同时包含于权利要求书中记载的发明及其等价物的范围内。另外,上述的各实施方式可以相互组合而实施。
Claims (3)
1.一种半导体装置,其具备:
基板或引线框;
第1半导体芯片,其具有第1面和与所述第1面相反一侧的第2面,所述第1面在外周具有连接垫;
接合构件,其将所述第1半导体芯片的所述第2面连接于所述基板或引线框上;
连接构件,其将所述第1半导体芯片的所述第1面的连接垫与所述基板或引线框电连接;
间隔物,其配置于所述第1半导体芯片的第1面上且具有小于所述第1半导体芯片的面积的面积;
散热构件,其配置于所述间隔物上且具有大于所述第1半导体芯片的面积的面积;和
密封树脂,其将所述第1半导体芯片、所述间隔物、所述连接构件及所述散热构件密封,
所述间隔物由金属纤维片材形成且确保所述第1半导体芯片与所述散热构件之间的距离,该金属纤维片材包含金属纤维和热固化性树脂,
所述散热构件由金属纤维片材形成且表面形成为粗面,该金属纤维片材包含交缠的金属纤维和热固化性树脂。
2.根据权利要求1所述的半导体装置,其中,所述散热构件的外周在XY俯视下将所述第1半导体芯片的外周全部包含在内。
3.根据权利要求1所述的半导体装置,其中,所述间隔物由金属纤维片材形成,该金属纤维片材包含所述金属纤维和所述热固化性树脂,其外周在XY俯视下包含在所述第1面的外周中。
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JP2016143815A (ja) * | 2015-02-04 | 2016-08-08 | 住友ベークライト株式会社 | パワーモジュール用放熱樹脂シート、その製造方法、パワーモジュールおよびその製造方法 |
WO2017061307A1 (ja) * | 2015-10-08 | 2017-04-13 | 住友ベークライト株式会社 | 放熱フィン、放熱フィンの製造方法、および放熱フィンを備える半導体パッケージ |
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US10840166B2 (en) | 2020-11-17 |
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