CN110310928A - 封装方法 - Google Patents

封装方法 Download PDF

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Publication number
CN110310928A
CN110310928A CN201810469635.4A CN201810469635A CN110310928A CN 110310928 A CN110310928 A CN 110310928A CN 201810469635 A CN201810469635 A CN 201810469635A CN 110310928 A CN110310928 A CN 110310928A
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Prior art keywords
packaging method
conducting
apertures
electronic component
connection pad
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CN201810469635.4A
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CN110310928B (zh
Inventor
林平平
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Delta Electronics International Singapore Pte Ltd
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Delta Electronics International Singapore Pte Ltd
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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Abstract

本公开是提供一种电子元件的封装方法，利用本公开的封装方法，电子元件可利用背磨工艺以进行研磨，因此，电子元件的厚度可被减少至小于或等于50μm，而本公开的封装方法可实现超薄的厚度及缩小功率模块的体积，此外，本公开的封装方法可不须利用光蚀刻工艺，而是利用钻孔工艺及研磨工艺形成导接垫，因此，本公开的封装方法可实现降低成本以及实现导接垫具有均匀厚度的优势。

Description

封装方法
技术领域
本公开涉及一种封装方法，特别涉及一种电子元件的封装方法。
背景技术
近年来，电子装置设计朝向小尺寸、轻薄及易于携带的趋势发展。再者，随着电子工业技术的日益进步，电子装置的内部电路已逐渐朝向模块化发展，换言之，复数个电子元件是整合在单一电子模块中。举例而言，功率模块(power module)为广泛使用的电子模块之一，功率模块可包括例如但不限于直流-直流转换器(DC to DC converter)、直流-交流转换器(DC to AC converter)或交流-直流转换器(AC to DC converter)。于复数个电子元件(例如集成电路芯片、电容器、电阻器、电感器、变压器、二极管及晶体管)整合为一功率模块之后，功率模块便可安装于主板或系统电路板上。
目前，嵌入式封装结构因具有例如较小覆盖区域(smaller footprint)、较扁平(lower profile)、较高电源密度及效能(higher power density and performance)、较佳热管理(better thermal management)、较低电源噪声(lower electrical noise)以及易于大规模生产制造等诸多优点而广泛地被应用。
然而，传统嵌入式封装结构具有一些缺点。举例来说，传统嵌入式封装结构不包含被动元件时的厚度通常大于350μm，因此很难缩减功率模块的体积大小。此外，重布线层(re-distribution layer,RDL)是形成于嵌入式封装结构的电子元件上的一额外金属层，而使得电子元件的导接端可于其他位置导接，传统嵌入式封装结构是以光蚀刻(photolithography)的方法形成重布线层，故传统嵌入式封装的方法易造成成本增加。此外，电镀铜(electrolytic copper plating)的工艺容易造成传统嵌入式封装的重布线层的厚度不均匀。
因此，实有必要提供一种改良的封装方法，以解决上述现有技术所面临的问题。
发明内容
本公开的目的在于提供一种封装方法，利用背磨工艺研磨电子元件，以达到超薄厚度以及缩小功率模块的体积，此外，本公开的封装方法可略过使用光蚀刻工艺以降低成本并可避免重布线层的厚度不均匀。
为达上述目的，本公开的一较广义实施方式为提供一种封装方法，其包括如下步骤。首先，提供第一载体。形成第一热剥离材料于第一载体上。提供至少一电子元件及至少一导热部件贴附于第一热剥离材料上，其中至少一电子元件包含至少一导接端。接着，形成第一绝缘层于电子元件的第一表面以及导热部件的第一表面上。移除第一载体及第一热剥离材料。接着，提供第二载体。形成第二热剥离材料于第二载体上。将偕同电子元件及导热部件的第一绝缘层贴附于第二热剥离材料。接着，研磨部分的电子元件的第二表面、部分的导热部件的第二表面以及部分的第一绝缘层的至少其中之一。接着，形成第二绝缘层于电子元件的第二表面及导热部件的第二表面上。移除第二载体及第二热剥离材料。接着，形成复数个第一开孔于第一绝缘层上。接着，经由对应的复数个第一开孔形成复数个第二开孔，其中，导接端及导热部件的第一表面经由复数个第二开孔而暴露。接着，经由复数个第二开孔形成第一金属层，第一金属层设置于导接端及导热部件的第一表面上。接着，形成复数个第三开孔于第二绝缘层上。接着，经由复数个第三开孔形成复数个第四开孔，其中导热部件的第二表面经由第四开孔而暴露。接着，形成第二金属层于复数个第四开孔中，第二金属层设置于导热部件的第二表面上。接着，研磨部分的第一金属层以形成至少一第一导接垫及至少一第二导接垫，研磨部分的第二金属层以形成至少一第三导接垫。
本领域技术人员于阅读以下的详细说明及附图后，将会对本公开上述内容有更进一步的认识及理解。
附图说明
图1A至1Q为本公开的第一实施例的电子元件的封装方法的截面结构示意图。
图2A至2Q为本公开的第二实施例的电子元件的封装方法的截面结构示意图。
附图标记说明：
1：功率模块
11：第一载体
12：第一热剥离材料
13：电子元件
131：第一表面
132：第二表面
133：导接端
14：导热部件
141：第一表面
142：第二表面
15：第一绝缘层
151：第一开孔
152：第二开孔
16：第二热剥离材料
17：第二载体
18：第二绝缘层
181：第三开孔
182：第四开孔
191：第一金属层
192：第二金属层
193：第一导接垫
194：第二导接垫
195：第三导接垫
21：第一保护层
22：第二保护层
23：被动元件
具体实施方式
体现本公开特征与优点的一些实施例将在后段的说明中详细叙述。应理解的是本公开能够在不同的实施方式上具有各种的变化，其皆不脱离本公开的范围，且其中的说明及附图在本质上是当作说明之用，而非用以限制本公开。例如，若是本公开以下的内容叙述了将一第一特征设置于一第二特征之上或上方，即表示其包含了所设置的上述第一特征与上述第二特征是直接接触的实施例，亦包含了尚可将附加的特征设置于上述第一特征与上述第二特征之间，而使上述第一特征与上述第二特征可能未直接接触的实施例。另外，本公开中不同实施例可能使用重复的参考符号及/或标记。这些重复为了简化与清晰的目的，并非用以限定各个实施例及/或所述外观结构之间的关系。
再者，为了方便描述附图中一元件或特征部件与另一(复数)元件或(复数)特征部件的关系，可使用空间相关用语，例如“在...之下”、“下方”、“较下部”、“上方”、“较上部”及类似的用语等。除了附图所示出的方位之外，空间相关用语用以涵盖使用或操作中的装置的不同方位。所述装置也可被另外定位(例如，旋转90度或者位于其他方位)，并对应地解读所使用的空间相关用语的描述。此外，当将一元件称为“连接到”或“耦合到”另一元件时，其可直接连接至或耦合至另一元件，或者可存在介入组件。尽管本公开的广义范围的数值范围及参数为近似值，但尽可能精确地在具体实例中陈述数值。另外，可理解的是，虽然「第一」、「第二」、「第三」等用词可被用于权利要求中以描述不同的元件，但这些元件并不应被这些用语所限制，在实施例中相应描述的这些元件是以不同的元件符号来表示。这些用语是为了分别不同组件。例如：第一元件可被称为第二元件，相似地，第二元件也可被称为第一元件而不会脱离实施例的范围。如此所使用的用语「及/或」包含了一或多个列出的相关事物的任何或全部的组合。此外，数值范围或参数固有地含有在各别测试测量中存在的误差。并且，如本文中出现用语”大约”或”实质上”一般意指在一给定值或范围的10％、5％、1％或0.5％内。另一选择为，用语“大约”或”实质上”意味所属领域的技术人员可接受的误差内。除在操作/工作实例中以外，或除非明确规定，否则本文中所公开的所有数值范围、量、值及百分比(例如角度、时间持续、温度、操作条件、量比及其类似者的那些百分比等)应被理解为在所有实施例中由用语”大约”或”实质上”来修饰。相应地，除非相反地指示，否则本公开及随附权利要求中陈述的数值参数为可视需要变化的近似值。例如，每一数值参数应至少根据所述的有效数字的数字且借由应用普通舍入原则来解释。范围可在本文中表达为从一个端点到另一端点或在两个端点之间。本文中所公开的所有范围包括端点，除非另有规定。
图1A至1Q为本公开的第一实施例的电子元件的封装方法的截面结构示意图。
首先，如图1A所示，实施黏晶(die bond)工艺，并提供第一载体11，第一热剥离材料12形成并贴附于第一载体11上，提供至少一电子元件13以及至少一导热部件14贴附于第一热剥离材料12上。于一实施例中，电子元件13的厚度H1可为但不限为大于或等于125μm。电子元件13具有第一表面131及第二表面132，其中电子元件13的第一表面131相对于电子元件13的第二表面132。导热部件14具有第一表面141及第二表面142，其中导热部件14的第一表面141相对于导热部件14的第二表面142，电子元件13的第二表面132及导热部件14的第二表面142与第一热剥离材料12相接触。此外，电子元件13包含至少一导接端133，导接端133设置于电子元件13的第一表面131。在一实施例中，导接端133是以铜、铝、银、金或任何适当的金属材料所构成。
在一些实施例中，封装方法提供复数个导热部件14，其中电子元件13设置于复数个导热部件14之间或被复数个导热部件14所围绕。
在一些实施例中，封装方法提供复数个电子元件13，其中复数个电子元件13设置于复数个导热部件14之间。
电子元件13可为主动元件或是被动元件。电子元件13例如但不限于集成电路(Integrated Circuit，IC)芯片、整合性功率元件、金属氧化物半导体场效晶体管(MOSFET)、高电子迁移率晶体管(HEMT)、绝缘闸双极性晶体管(Insulated-gate bipolartransistor，IGBT)、二极管(Diode)、电容器、电阻器、电感器或保险丝。电子元件13的导接端133的数目可依据电子元件13的种类及架构而定，例如图1A所示，电子元件13示例可为集成电路芯片，根据该集成电路芯片的架构，电子元件13具有三个导接端133。
在一实施例中，第一热剥离材料12为一热剥离胶膜。电子元件13设置于两个相邻的导热部件14之间。在一些实施例中，导热部件14可由金属导线架实现，在另一些实施利中，导热部件14亦可由具良好导热特性的印刷电路板或陶瓷基板(ceramic substrate)实现。
接着，如图1B所示，进行层压(lamination)工艺，第一绝缘层15形成于电子元件13的第一表面131及导热部件14的第一表面141上，以覆盖电子元件13的导接端133及导热部件14。于一实施例中，第一绝缘层15可为例如但不限于树脂或其他具高热传导系数的适当绝缘材料所形成，例如Ajinomoto绝缘增层膜(Ajinomoto build-up film,ABF)。
接着，如图1C所示，移除第一载体11及第一热剥离材料12，因此，暴露出电子元件13的第二表面132及导热部件14的第二表面142。
接着，如图1D所示，提供第二载体17，并将第二热剥离材料16形成于第二载体17上，接着，将偕同电子元件13及导热部件14的第一绝缘层15贴附于第二热剥离材料16。
接着，如图1E所示，进行背磨(back grinding)工艺，研磨部分的电子元件13的第二表面132、部分的导热部件14的第二表面142以及部分的第一绝缘层15的至少其中之一直到电子元件13达一特定的厚度H2。在一实施例中，背磨工艺是研磨部分的电子元件13的第二表面132、部分的导热部件14的第二表面142以及部分的第一绝缘层15。在一实施例中，当研磨部分的电子元件13，电子元件13的特定的厚度H2可为小于或等于50μm。在一实施例中，背磨工艺可由机械研磨方式实施。
接着，如图1F所示，进行层压工艺，第二绝缘层18形成于电子元件13的第二表面132及导热部件14的第二表面142上，部分的第二绝缘层18接触并连接于部分的第一绝缘层15。在一实施例中，第一绝缘层15及第二绝缘层18是可由相同的材料所形成，故第一绝缘层15及第二绝缘层18可为一体成形结构，因此，电子元件13及导热部件14设置于第一绝缘层15及第二绝缘层18之间。在一实施例中，第二绝缘层18可为例如但不限于树脂或其他具高热传导系数的适当绝缘材料所形成，例如Ajinomoto绝缘增层膜(Ajinomoto build-upfilm,ABF)。
接着，如图1G所示，移除第二载体17及第二热剥离材料16，因此，暴露出第一绝缘层15，而电子元件13及导热部件14嵌设于第一绝缘层15及第二绝缘层18的结合处。
接着，如图1H所示，复数个第一开孔151形成于第一绝缘层15上，其中复数个第一开孔151根据电路图的设计图形而形成，复数个第一开孔151相对于电子元件13的导接端133及/或导热部件14的第一表面141的位置设置。于一实施例中，复数个第一开孔151经由钻孔工艺所形成。于一实施例中，钻孔工艺可为激光钻孔工艺。
接着，如图1I所示，复数个第二开孔152(即为盲孔)形成于第一绝缘层15上，且复数个第二开孔152经由对应的第一开孔151形成，复数个第二开孔152设置于对应的第一开孔151及对应的电子元件13的导接端133之间，且/或复数个第二开孔152设置于对应的第一开孔151及对应的导热部件14之间，而电子元件13的导接端133及导热部件14的第一表面141经由对应的第二开孔152而暴露。在一实施例中，第二开孔152的尺寸小于对应的第一开孔151的尺寸。在一实施例中，复数个第二开孔152经由钻孔工艺所形成。在一实施例中，钻孔工艺可为激光钻孔工艺。在一实施例中，用以钻出复数个第二开孔152的激光的能量大于用以钻出复数个第一开孔151的激光的能量。
接着，如图1J所示，进行溅镀工艺，第一金属层191经由复数个第二开孔152及复数个第一开孔151形成，因此，第一金属层191设置于电子元件13的导接端133及导热部件14的第一表面141上，此外，第一金属层191设置于第一绝缘层15上。在一实施例中，第一金属层191经由沉积一金属层而形成，该金属层可为例如但不限为铜层、钛钨/铜(TiW/Cu)层、镍镉/铜(NiCr/Cu)层或其组合，并于前述图1I所示的最终结构上所构成。
接着，如图1K所示，复数个第三开孔181形成于第二绝缘层18上，复数个第三开孔181根据电路图的设计图形而形成，复数个第三开孔181相对于导热部件14的第二表面142设置。在一些实施例中，复数个第三开孔181相对于导热部件14的第二表面142及电子元件13的第二表面132设置。在一实施例中，复数个第三开孔181由钻孔工艺所形成。在一实施例中，钻孔工艺可为激光钻孔工艺。
接着，如图1L所示，复数个第四开孔182(即为盲孔)形成于第二绝缘层18上，且复数个第四开孔182经由对应的第三开孔181形成，复数个第四开孔182设置于对应的第三开孔181及对应的导热部件14的第二表面141之间，而导热部件14的第二表面142经由对应的第四开孔182而暴露。在一实施例中，第四开孔182的尺寸小于对应的第三开孔181的尺寸。在一实施例中，复数个第四开孔182经由钻孔工艺而形成。在一实施例中，钻孔工艺可为激光钻孔工艺。在一实施例中，用以钻出复数个第四开孔182的激光的能量大于用以钻出复数个第三开孔181的激光的能量。
接着，如图1M所示，进行溅镀工艺，第二金属层192形成于复数个第四开孔182及复数个第三开孔181中，因此，第二金属层192设置于导热部件14的第二表面142上。在一实施例中，第二金属层192经由沉积一金属层而形成，该金属层可为例如但不限于铜层、钛钨/铜(TiW/Cu)层、镍镉/铜(NiCr/Cu)层或其组合，并于前述图1L所示的最终结构上所构成。
接着，如图1N所示，进行研磨工艺，研磨部分的第一金属层191以形成至少一第一导接垫193以及至少一第二导接垫194，第一导接垫193相对且相接触于导接端133，第二导接垫194相对且相接触于导热部件14的第一表面141。在一实施例中，形成复数个第一导接垫193，其中至少一第一导接垫193相对且相接触于对应的电子元件13的导接端133。
接着，如图1O所示，进行研磨工艺，研磨部分的第二金属层192以形成至少一第三导接垫195，第三导接垫195相对且相接触于导热部件14的第二表面142。
接着，如图1P所示，形成第一保护层21并接触于至少部分的第一导接垫193及部分的第二导接垫194，第一保护层21是用以避免第一导接垫193及第二导接垫194的氧化，且暴露出未被第一保护层21覆盖的部分的第二导接垫194。形成第二保护层22并接触于部分的第三导接垫195，第二保护层22是用以避免第三导接垫195的氧化，且暴露出未被第二保护层22覆盖的部分的第三导接垫195。在一实施例中，第一保护层21及第二保护层22的至少其中之一可为例如但不限于树脂或其他具高热传导系数的适当绝缘材料所形成。在一实施例中，第一保护层21及第二保护层22由树脂或任何其他合适的绝缘材料所形成。与此同时，本封装方法制成了嵌入式封装结构的功率模块1。
接着，如图1Q所示，提供被动元件23并设置于第一保护层21上，因此，部分的被动元件23耦接于第二导接垫194，部分的被动元件23耦接于第一导接垫193，其中与第一导接垫193耦接的部分的被动元件23相对且接触于对应的电子元件13的导接端133及对应的导热部件14的第一表面141。接着，提供电路板(未图示)于第二保护层22上，电路板与第三导接垫195相耦接，因此，嵌入式封装结构的功率模块1设置于电路板上。
图2A至2Q为本公开的第二实施例的电子元件的封装方法的截面结构示意图。于本实施例中，封装方法的组成部分及元件相似于前述第一实施例的封装方法的组成部分及元件，其中相同元件符号代表相同的元件，于此不再赘述。如图2A至2Q所示，本实施例的封装方法提供复数个电子元件13，复数个电子元件13设置于复数个导热部件14之间，换言之，至少两个电子元件13设置于相邻两个导热部件14之间。在一实施例中，图1A至1Q的步骤相似于图2A至2Q的步骤，故于此不再赘述。
综上所述，本公开的实施例提供一种电子元件的封装方法，利用本公开的实施例的封装方法，电子元件可利用背磨工艺以进行研磨，因此，电子元件的厚度可被减少至小于或等于50μm，而本公开的封装方法可实现超薄的厚度及缩小功率模块的体积，此外，本公开的封装方法可略过光蚀刻工艺，而利用钻孔工艺及研磨工艺形成导接垫，因此，本公开的封装方法可实现降低成本以及实现导接垫具有均匀厚度的优势。

Claims (13)

1.一种封装方法，包含步骤：
提供一第一载体；
形成一第一热剥离材料于该第一载体上；
提供至少一电子元件及至少一导热部件贴附于该第一热剥离材料上，其中该至少一电子元件包含至少一导接端；
形成一第一绝缘层于该电子元件的一第一表面以及该导热部件的一第一表面上；
移除该第一载体及该第一热剥离材料；
提供一第二载体；
形成一第二热剥离材料于该第二载体上；
将偕同该电子元件及该导热部件的该第一绝缘层贴附于该第二热剥离材料；
研磨部分的该电子元件的一第二表面、部分的该导热部件的一第二表面以及部分的该第一绝缘层的至少其中之一；
形成一第二绝缘层于该电子元件的该第二表面及该导热部件的该第二表面上；
移除该第二载体及该第二热剥离材料；
形成复数个第一开孔于该第一绝缘层上；
经由对应的该复数个第一开孔形成复数个第二开孔，其中该导接端及该导热部件的该第一表面经由该复数个第二开孔而暴露；
经由该复数个第二开孔形成一第一金属层，该第一金属层设置于该导接端及该导热部件的该第一表面上；
形成复数个第三开孔于该第二绝缘层上；
经由该复数个第三开孔形成复数个第四开孔，其中该导热部件的该第二表面经由该第四开孔而暴露；
形成一第二金属层于该复数个第四开孔中，该第二金属层设置于该导热部件的该第二表面上；
研磨部分的该第一金属层以形成至少一第一导接垫及至少一第二导接垫；以及
研磨部分的该第二金属层以形成至少一第三导接垫。
2.如权利要求1所述的封装方法，其中该至少一第一导接垫相对且相接触于该电子元件的该导接端，该至少一第二导接垫相对且相接触于该导热部件的该第一表面，以及该至少一第三导接垫相对且相接触于该导热部件的该第二表面。
3.如权利要求1所述的封装方法，其中该封装方法还包含步骤：
形成一第一保护层于至少部分的该至少一第一导接垫及部分的该至少一第二导接垫上；以及
形成一第二保护层于部分的该至少一第三导接垫上，其中暴露出未被该第一保护层覆盖的部分的该至少一第二导接垫，且暴露出未被该第二保护层覆盖的部分的该至少一第三导接垫。
4.如权利要求3所述的封装方法，其中该封装方法还包含步骤：提供一被动元件并设置于该第一保护层上，其中部分的该被动元件耦接于该至少一第二导接垫。
5.如权利要求3所述的封装方法，其中该封装方法还包含步骤：提供一电路板于该第二保护层上，其中该电路板与该至少一第三导接垫相耦接。
6.如权利要求3所述的封装方法，其中该第一保护层及该第二保护层的至少其中之一包含一树脂、一绝缘材或一前述的结合物。
7.如权利要求1所述的封装方法，其中该第一绝缘层及该第二绝缘层的至少其中之一包含一树脂、一Ajinomoto绝缘增层膜(Ajinomoto Build-upFilm,ABF)或一前述的结合物。
8.如权利要求1所述的封装方法，其中该至少一电子元件的该至少一导接端设置于该至少一电子元件的该第一表面。
9.如权利要求1所述的封装方法，其中该封装方法提供复数个导热部件，其中该至少一电子元件设置于该复数个导热部件之间或被该复数个导热部件所围绕。
10.如权利要求9所述的封装方法，其中该封装方法提供复数个电子元件，其中该复数个电子元件设置于该复数个导热部件之间。
11.如权利要求1所述的封装方法，其中该电子元件被研磨至一特定厚度，其中该电子元件的该特定厚度小于或等于50μm。
12.如权利要求1所述的封装方法，其中该第一金属层及该第二金属层的至少其中之一具有铜或含铜材料。
13.如权利要求1所述的封装方法，其中该复数个第一开孔、该复数个第二开孔、该复数个第三开孔及该复数个第四开孔的至少其中之一由钻孔工艺所形成。
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