CN110164839A - 一种高密度线路嵌入转移的扇出型封装结构与方法 - Google Patents
一种高密度线路嵌入转移的扇出型封装结构与方法 Download PDFInfo
- Publication number
- CN110164839A CN110164839A CN201910446516.1A CN201910446516A CN110164839A CN 110164839 A CN110164839 A CN 110164839A CN 201910446516 A CN201910446516 A CN 201910446516A CN 110164839 A CN110164839 A CN 110164839A
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric layer
- wiring
- line
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000003780 insertion Methods 0.000 title claims abstract description 35
- 230000037431 insertion Effects 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000012546 transfer Methods 0.000 title claims abstract description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 54
- 229910052802 copper Inorganic materials 0.000 claims abstract description 42
- 239000010949 copper Substances 0.000 claims abstract description 42
- 238000004806 packaging method and process Methods 0.000 claims abstract description 19
- 238000007731 hot pressing Methods 0.000 claims abstract description 15
- 238000007747 plating Methods 0.000 claims abstract description 10
- 239000003292 glue Substances 0.000 claims description 19
- 230000008018 melting Effects 0.000 claims description 12
- 238000002844 melting Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000007711 solidification Methods 0.000 claims description 10
- 230000008023 solidification Effects 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 230000007704 transition Effects 0.000 claims description 7
- 238000011161 development Methods 0.000 claims description 6
- 241000196324 Embryophyta Species 0.000 claims description 5
- 238000005260 corrosion Methods 0.000 claims description 5
- 230000007797 corrosion Effects 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 238000005538 encapsulation Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000013461 design Methods 0.000 claims description 3
- 241000218202 Coptis Species 0.000 claims description 2
- 235000002991 Coptis groenlandica Nutrition 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 239000007787 solid Substances 0.000 claims description 2
- 238000004080 punching Methods 0.000 claims 1
- 238000002360 preparation method Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000004744 fabric Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (6)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910446516.1A CN110164839B (zh) | 2019-05-27 | 2019-05-27 | 一种高密度线路嵌入转移的扇出型封装结构与方法 |
PCT/CN2020/092384 WO2020238914A1 (zh) | 2019-05-27 | 2020-05-26 | 一种高密度线路嵌入转移的扇出型封装结构及其制作方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910446516.1A CN110164839B (zh) | 2019-05-27 | 2019-05-27 | 一种高密度线路嵌入转移的扇出型封装结构与方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110164839A true CN110164839A (zh) | 2019-08-23 |
CN110164839B CN110164839B (zh) | 2020-01-31 |
Family
ID=67629250
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910446516.1A Active CN110164839B (zh) | 2019-05-27 | 2019-05-27 | 一种高密度线路嵌入转移的扇出型封装结构与方法 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN110164839B (zh) |
WO (1) | WO2020238914A1 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111755350A (zh) * | 2020-05-26 | 2020-10-09 | 甬矽电子(宁波)股份有限公司 | 封装结构制作方法和封装结构 |
WO2020238914A1 (zh) * | 2019-05-27 | 2020-12-03 | 广东工业大学 | 一种高密度线路嵌入转移的扇出型封装结构及其制作方法 |
CN113725087A (zh) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | 芯片封装结构的制作方法 |
CN113725086A (zh) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | 芯片封装结构的制作方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102522366A (zh) * | 2011-11-25 | 2012-06-27 | 北京大学深圳研究生院 | 一种集成电路芯片重新布线的压印方法 |
CN202839599U (zh) * | 2012-08-23 | 2013-03-27 | 江阴长电先进封装有限公司 | 一种芯片嵌入式三维圆片级封装结构 |
US20160351509A1 (en) * | 2015-06-01 | 2016-12-01 | Rf Micro Devices, Inc. | Wafer level fan-out with electromagnetic shielding |
US20170243845A1 (en) * | 2016-02-19 | 2017-08-24 | Qualcomm Incorporated | Fan-out wafer-level packages with improved topology |
CN208768159U (zh) * | 2018-06-29 | 2019-04-19 | 宁波舜宇光电信息有限公司 | 线路板组件、感光组件及摄像模组 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4902558B2 (ja) * | 2007-01-31 | 2012-03-21 | 三洋電機株式会社 | 半導体モジュールの製造方法 |
US8659154B2 (en) * | 2008-03-14 | 2014-02-25 | Infineon Technologies Ag | Semiconductor device including adhesive covered element |
US8604600B2 (en) * | 2011-12-30 | 2013-12-10 | Deca Technologies Inc. | Fully molded fan-out |
US8623699B2 (en) * | 2010-07-26 | 2014-01-07 | General Electric Company | Method of chip package build-up |
US9721799B2 (en) * | 2014-11-07 | 2017-08-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with reduced via hole width and reduced pad patch and manufacturing method thereof |
CN110164839B (zh) * | 2019-05-27 | 2020-01-31 | 广东工业大学 | 一种高密度线路嵌入转移的扇出型封装结构与方法 |
-
2019
- 2019-05-27 CN CN201910446516.1A patent/CN110164839B/zh active Active
-
2020
- 2020-05-26 WO PCT/CN2020/092384 patent/WO2020238914A1/zh active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102522366A (zh) * | 2011-11-25 | 2012-06-27 | 北京大学深圳研究生院 | 一种集成电路芯片重新布线的压印方法 |
CN202839599U (zh) * | 2012-08-23 | 2013-03-27 | 江阴长电先进封装有限公司 | 一种芯片嵌入式三维圆片级封装结构 |
US20160351509A1 (en) * | 2015-06-01 | 2016-12-01 | Rf Micro Devices, Inc. | Wafer level fan-out with electromagnetic shielding |
US20170243845A1 (en) * | 2016-02-19 | 2017-08-24 | Qualcomm Incorporated | Fan-out wafer-level packages with improved topology |
CN208768159U (zh) * | 2018-06-29 | 2019-04-19 | 宁波舜宇光电信息有限公司 | 线路板组件、感光组件及摄像模组 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020238914A1 (zh) * | 2019-05-27 | 2020-12-03 | 广东工业大学 | 一种高密度线路嵌入转移的扇出型封装结构及其制作方法 |
CN113725087A (zh) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | 芯片封装结构的制作方法 |
CN113725086A (zh) * | 2020-03-27 | 2021-11-30 | 矽磐微电子(重庆)有限公司 | 芯片封装结构的制作方法 |
CN113725086B (zh) * | 2020-03-27 | 2024-02-27 | 矽磐微电子(重庆)有限公司 | 芯片封装结构的制作方法 |
CN113725087B (zh) * | 2020-03-27 | 2024-02-27 | 矽磐微电子(重庆)有限公司 | 芯片封装结构的制作方法 |
CN111755350A (zh) * | 2020-05-26 | 2020-10-09 | 甬矽电子(宁波)股份有限公司 | 封装结构制作方法和封装结构 |
Also Published As
Publication number | Publication date |
---|---|
WO2020238914A1 (zh) | 2020-12-03 |
CN110164839B (zh) | 2020-01-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110164839A (zh) | 一种高密度线路嵌入转移的扇出型封装结构与方法 | |
US7838967B2 (en) | Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips | |
EP3422398A1 (en) | Silicon substrate embedded, fan-out, 3d package structure | |
US8273601B2 (en) | Method of fabricating multi-chip package structure | |
CN102098876B (zh) | 用于电路基板的制造工艺 | |
KR100721489B1 (ko) | 회로 장치 및 그 제조 방법 | |
CN101183668B (zh) | 电解电镀形成突起电极的半导体装置及其制造方法 | |
JP5942823B2 (ja) | 電子部品装置の製造方法、電子部品装置及び電子装置 | |
KR20040014432A (ko) | 일체식 열 싱크 및 복합 층을 구비한 초소형 전자 패키지 | |
US11335648B2 (en) | Semiconductor chip fabrication and packaging methods thereof | |
US20160133537A1 (en) | Semiconductor package with embedded component and manufacturing method thereof | |
KR100551576B1 (ko) | 반도체 장치 및 그 제조방법 | |
TWI413210B (zh) | 電子裝置封裝及製造方法 | |
CN109003959B (zh) | 一种焊线预成型的高导热封装结构及其制造方法 | |
US7745260B2 (en) | Method of forming semiconductor package | |
CN107195617A (zh) | 基于不同高度铜柱的三维封装结构及其制造方法 | |
CN107104091B (zh) | 一种半埋入线路基板结构及其制造方法 | |
KR20110129446A (ko) | 반도체 소자용 기판의 제조 방법 및 반도체 장치 | |
CN110797267A (zh) | 一种倒装芯片封装中具有互连结构的底填方法 | |
JP2002527906A (ja) | 電子モジュール、特に多層金属配線層を有するマルチチップ・モジュールおよびその製造方法 | |
JP5479959B2 (ja) | はんだバンプを有する配線基板の製造方法、はんだボール搭載用マスク | |
CN104659021A (zh) | 一种三维圆片级扇出PoP封装结构及其制造方法 | |
US20070267730A1 (en) | Wafer level semiconductor chip packages and methods of making the same | |
US11948899B2 (en) | Semiconductor substrate structure and manufacturing method thereof | |
US20230136778A1 (en) | Semiconductor substrate structure and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20240227 Address after: Room A107, Research Building A, Neifo High tech Think Tank Center, Nanhai Software Technology Park, Shishan Town, Nanhai District, Foshan City, Guangdong Province, 528000 Patentee after: Guangdong fozhixin microelectronics technology research Co.,Ltd. Country or region after: China Address before: 510006 No. 100 West Ring Road, University of Guangdong, Guangzhou Patentee before: GUANGDONG University OF TECHNOLOGY Country or region before: China |