CN110120334A - 半导体装置的制造方法和半导体装置 - Google Patents

半导体装置的制造方法和半导体装置 Download PDF

Info

Publication number
CN110120334A
CN110120334A CN201811561987.9A CN201811561987A CN110120334A CN 110120334 A CN110120334 A CN 110120334A CN 201811561987 A CN201811561987 A CN 201811561987A CN 110120334 A CN110120334 A CN 110120334A
Authority
CN
China
Prior art keywords
film
semiconductor device
containing metal
antireflection
passivating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811561987.9A
Other languages
English (en)
Inventor
佐久间哲也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ablic Inc
Original Assignee
Ablic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ablic Inc filed Critical Ablic Inc
Publication of CN110120334A publication Critical patent/CN110120334A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02551Group 12/16 materials
    • H01L21/02554Oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • H01L21/0276Photolithographic processes using an anti-reflective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865Selective removal of parts of the layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/03001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03009Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/0347Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/05186Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05567Disposition the external layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3512Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

提供半导体装置的制造方法和半导体装置,即使在使用防反射膜高精度地进行金属膜的构图的情况下,也可防止发生伴随存在防反射膜而在不同种类的金属之间产生的局部电池效应,可防止防反射膜在THB试验等中发生腐蚀,可靠性高。具有如下工序:形成包含第一含金属膜以及层叠在该第一含金属膜上的由与第一含金属膜不同的第二含金属膜构成的防反射膜的导电膜;对导电膜进行构图;在构图后的导电膜的侧面形成侧壁保护膜;在形成有侧壁保护膜的状态下蚀刻去除构图后的导电膜中的防反射膜;以覆盖第一含金属膜和侧壁保护膜的方式形成钝化膜;以及在钝化膜形成使第一含金属膜的上表面的一部分露出的开口部。

Description

半导体装置的制造方法和半导体装置
技术领域
本发明涉及半导体装置的制造方法和半导体装置,特别涉及在覆盖导电膜的钝化膜上具有使由该导电膜构成的焊盘(Bonding pad)等的上表面露出的开口部的半导体装置的制造方法和半导体装置。
背景技术
在半导体装置中,一般而言,将铝(Al)等金属膜构图为焊盘形状,在覆盖该金属膜的钝化膜形成开口部,利用在该开口部上露出的焊盘部进行与外部的电连接。
在对铝膜等金属膜进行构图时的光刻工序中,需要预先在金属膜上形成氮化钛(TiN)膜等防反射膜,以防止由于对抗蚀剂进行曝光时的光的反射引起的晕影(halation)并且高精度地进行期望的构图。因此,在构图后的焊盘的上表面上残留有防反射膜。在覆盖该焊盘的钝化膜形成开口部的情况下,接着钝化膜也去除防反射膜,以使金属膜的上表面在开口部内露出。由于防反射膜在以这样的方式形成的开口部的内侧面处露出,因此,氮化钛膜等防反射膜与铝膜等金属膜的界面在开口部内露出。
这样,当如氮化钛膜和铝膜这样的不同种类金属的界面在开口部内露出时,在之后进行的切割工序等浸入水溶液中的工序中,由于不同种类的金属之间产生的局部电池效应,离子化倾向较高的金属膜(铝膜)从与离子化倾向比其低的防反射膜(氮化钛膜)的界面溶解,焊盘产生缺陷部,并且,溶解后的金属膜(铝膜)的反应生成物(氢氧化铝)附着于焊盘的表面。
为了解决这样的问题,例如,在专利文献1中提出了如下方法:预先在由氮化钛膜构成的防反射膜形成比焊盘部用的开口部大的开口,然后,形成覆盖整个面的钝化膜(或者,与焊盘相同的铝膜),在该钝化膜(或者铝膜)上形成焊盘部用的开口部,由此,使得如氮化钛膜和铝膜这样的不同种类金属的界面不在开口部内露出。
此外,在专利文献1中,作为另一方法,还提出了如方法:在将金属膜与防反射膜的层叠膜构图为焊盘形状之后,形成覆盖焊盘以外的区域的光抗蚀剂图案,将该光抗蚀剂图案作为掩模,将金属膜上的防反射膜全部蚀刻去除,然后,进行钝化膜的形成和开口部的形成,由此,使得不形成不同种类金属的界面(参照专利文献1的图6~10)。
此外,在专利文献1中,作为又一方法,还提出了如下方法:在对第1钝化膜和防反射膜同时进行构图而形成使铝膜等金属膜的上表面露出的开口部之后,在整个面上形成第2钝化膜,然后,通过溅射蚀刻将第2钝化膜蚀刻至金属膜的上表面露出,由第2钝化膜覆盖开口部的内侧面,由此,使得不同种类金属的界面不在开口部内露出(参照专利文献1的图17~22)。
此外,如上所述,当在覆盖焊盘的钝化膜上所形成的开口部的内侧面处露出防反射膜时,在THB试验等伴随高温高湿度环境下的偏压施加的长期可靠性试验中,还产生防反射膜被氧化而发生腐蚀的问题。
为了解决这样的问题,例如,在专利文献2中,与专利文献1的上述第一个的方法同样还提出了如下方法:预先在防反射膜形成比焊盘部用的开口部大的开口,然后,形成覆盖整个面的钝化膜,在该钝化膜形成焊盘部用的开口部,由此,使得防反射膜不在开口部内侧面处露出。
专利文献1:日本特开2006-303452号公报
专利文献2:日本特许第5443827号
但是,在专利文献1所示的上述第一个的方法中,为了在防反射膜上形成比焊盘部用的开口部大的开口,需要追加光刻工序,存在由于掩模增加、工序增加而成本增加的问题。
在专利文献1所示的上述第二个的方法中,也需要追加光刻工序。并且,在该第二个的方法中,还产生如图7所示的问题。
图7的(a)示出了如下状态:在层间绝缘膜201上层叠势垒金属层211、金属膜212和防反射膜213,将该层叠膜构图为焊盘221和布线222的形状,形成有在焊盘221上具有开口252的光抗蚀剂图案251。势垒金属层211和防反射膜213利用由包含相同的金属的膜、例如、氮化钛等形成。
在以这样的方式将光抗蚀剂图案251形成为在焊盘221上具有开口252的情况下,如专利文献1的图7所示,使光抗蚀剂图案的开口与焊盘的端部完全对准是非常困难的,通常,如图7的(a)所示,产生焊盘221与光抗蚀剂图案251的开口252之间的位置对准偏差。因此,在将该光抗蚀剂图案251作为掩模将焊盘221上的防反射膜213蚀刻去除的情况下,如图7的(b)所示,防反射膜213的上表面处于被光抗蚀剂图案251覆盖一部分的状态,因此,在焊盘221的金属膜212的上表面上残留有防反射膜213。此外,防反射膜213和势垒金属层211是包含相同金属的膜,在焊盘221与光抗蚀剂图案251之间的间隙中露出势垒金属层211,因此,在防反射膜213的蚀刻中,势垒金属层211也被蚀刻,导致形成槽口Nt。
当残留防反射膜213时,之后在整个面上形成钝化膜,当在该钝化膜形成了使焊盘221的上表面露出的开口部时,最后可能导致金属膜212与防反射膜213的界面在开口部的内侧面处露出。此外,当在形成有槽口Nt的状态下在整个面上形成了钝化膜时,在槽口Nt的部分上未形成钝化膜,由此,在钝化膜上容易产生裂纹等导致可靠性下降。
此外,在专利文献1所示的上述第三个的方法中,在通过溅射蚀刻将第2钝化膜蚀刻至金属膜的上表面露出时,需要充分的过蚀刻,以使在焊盘的上表面上不残留第2钝化膜。因此,第1钝化膜也被蚀刻,导致该第1钝化膜的膜厚变薄,有可能对可靠性带来不良影响。
并且,针对认为专利文献2能够解决的伴随高温高湿度环境下的偏压施加的长期可靠性试验中的防反射膜的腐蚀的问题,即使防反射膜不在焊盘部用的开口部的内侧面处露出,在因某些原因而在钝化膜上存在微小裂纹等水分浸入路径的情况下,水分从该部分浸入,其结果,残留的防反射膜也有可能发生腐食。由此,可靠性并不充分。
发明内容
因此,本发明的目的在于提供一种即使在使用防反射膜高精度地进行金属膜的构图的情况下,也能够在不追加光刻工序的情况下防止伴随存在防反射膜而在不同种类的金属之间产生的局部电池效应的发生并且能够防止在伴随高温高湿度环境下的偏压施加的长期可靠性试验中防反射膜发生腐蚀的、可靠性高的半导体装置的制造方法和半导体装置。
本发明的半导体装置的制造方法的特征在于具有以下工序:形成包含第一含金属膜以及层叠在该第一含金属膜上的防反射膜的导电膜,其中所述防反射膜由与所述第一含金属膜不同的第二含金属膜构成;对所述导电膜进行构图;在构图后的所述导电膜的侧面形成侧壁保护膜;在形成有所述侧壁保护膜的状态下蚀刻去除构图后的所述导电膜中的所述防反射膜;以覆盖所述第一含金属膜和所述侧壁保护膜的方式形成钝化膜;以及在所述钝化膜形成使所述第一含金属膜的上表面的一部分露出的开口部。
根据本发明,由于在构图后的导电膜的侧面形成有侧壁保护膜的状态下去除防反射膜,因此,无需追加用于去除防反射膜的光刻工序。此外,由于去除构图后的防反射膜,所以不形成第一含金属膜和作为防反射膜的第二含金属膜的不同种类金属的界面本身,因此,能够防止产生电池效应。并且,即使在导电膜在第一含金属膜的下层包含势垒金属层的情况下,通过在导电膜的侧面形成有侧壁保护膜,也能够防止在去除防反射膜时势垒金属层被蚀刻而产生槽口。因此,能够获得可靠性高的半导体装置。
附图说明
图1是示出本发明的一个实施方式的半导体装置的制造工序的一个工序的剖视图。
图2是示出接着图1的本发明的一个实施方式的半导体装置的制造工序的一个工序的剖视图。
图3是示出接着图2的本发明的一个实施方式的半导体装置的制造工序的一个工序的剖视图。
图4是示出接着图3的本发明的一个实施方式的半导体装置的制造工序的一个工序的剖视图。
图5是示出接着图4的本发明的一个实施方式的半导体装置的制造工序的一个工序的剖视图。
图6是示出接着图5的本发明的一个实施方式的半导体装置的制造工序的一个工序的剖视图。
图7是用于说明现有的半导体装置的制造工序中的问题的剖视图。
标号说明
1、201:层间绝缘膜;10:导电膜;11、211:势垒金属层;12、212:金属膜;13、213:防反射膜;21、221:焊盘;22、222:布线;31:绝缘膜;32:侧壁保护膜;41:钝化膜;42:开口部;251:光抗蚀剂图案;252:开口。
具体实施方式
以下,参照附图说明用于实施本发明的方式。
图1~图6是用于说明本发明的一个实施方式的半导体装置的制造工序的剖视图。
如图1所示,通过溅射等依次沉积势垒金属层11、由铝构成的金属膜(也称作“第一含金属膜”)12、由氮化钛构成的防反射膜(也称作“第二含金属膜”)13,形成具有不同种类金属的层叠构造的导电膜(也称作“布线层”)10,该势垒金属层11是在半导体衬底(未图示)上所形成的层间绝缘膜1上依次层叠氮化钛和钛而形成的。然后,在该导电膜10上通过光刻工序形成光抗蚀剂图案(未图示),将该光抗蚀剂图案作为掩模,对导电膜10进行构图,由此,形成焊盘21和布线22。
接着,如图2所示,以覆盖构图后的导电膜10、即、焊盘21和布线22的上表面和侧面的方式,利用CVD法在整个面上形成绝缘膜31,该绝缘膜31在整个面上由氧化硅膜构成。
接下来,如图3所示,通过各向异性的干蚀刻,对绝缘膜31进行回蚀。直到防反射膜13的上表面露出为止,进行该回蚀。由此,在焊盘21和布线22的侧壁上形成侧壁保护膜32。
在形成有侧壁保护膜32的状态下,如图4所示,通过干蚀刻或者基于过氧化氢溶液等药液的蚀刻来去除防反射膜13。这时,势垒金属层11由与构成防反射膜13的氮化钛膜相同的包含钛的膜构成,但由于利用由氧化硅膜构成的侧壁保护膜32保护焊盘21和布线22的侧壁,因此,能够不蚀刻势垒金属层11而完全去除防反射膜13。因此,能够防止在导电膜10上形成槽口。
接着,如图5所示,以覆盖包含金属膜12的上表面和侧壁保护膜32的表面在内的整个面的方式,例如通过CVD法形成由氧化硅膜与氮化硅膜的层叠膜构成的钝化膜41。这时,由于在焊盘21上未形成有槽口,因此,能够防止产生未形成有钝化膜41的部分。并且,由于利用侧壁保护膜32缓和了焊盘21和布线22的阶梯差形状,因此,还能够获得以良好的覆盖范围沉积钝化膜41的效果。因此,能够防止在钝化膜上容易产生裂纹等问题,能够提高可靠性。
接下来,如图6所示,通过光刻工序形成在焊盘21上具有开口的光抗蚀剂图案(未图示),将该光抗蚀剂图案作为掩模,对钝化膜41进行构图,在焊盘21的一部分上形成开口部42。由此,在开口部42露出的焊盘21的上表面成为焊盘部。这里,在图2所示的工序中事先去除了防反射膜13,因此,防反射膜13不会在开口部42的内侧面处露出,所以能够防止电池效应的发生。
一般而言,使用防反射膜进行金属膜的构图是为了高精度地进行期望的构图的,即、为了实现细微的布线宽度、布线间隔的,因此,在本实施方式中,布线22的宽度、焊盘21与布线22的间隔以及未图示的布线与布线的间隔(均称作布线间隔)非常窄,例如,布线宽度为1μm以下,布线间隔为1μm以下。
但是,即使采用如这样细微的布线宽度、布线间隔,根据本实施方式,也能够使用防反射膜13高精度地对金属膜12进行构图,并且,能够防止电池效应的发生,并且,能够以良好的覆盖范围形成钝化膜41,而不会在焊盘21的下端形成槽口。因此,根据本实施方式,能够获得可靠性高的半导体装置。
以上,对本发明的实施方式进行了说明,但本发明并不受上述实施方式限定,当然能够在不脱离本发明的宗旨的范围内进行各种变更。
例如,在上述实施方式中,示出了通过干蚀刻或者基于过氧化氢溶液等药液的蚀刻来去除防反射膜13的例子,但不限于此,也可以是,以与绝缘膜31的回蚀时连续的方式,进行蚀刻直到金属膜12露出为止,去除防反射膜13。
此外,在上述实施方式中,示出了侧壁保护膜是氧化硅膜的例子,但也可以替代氧化硅膜,采用氮化硅膜。
并且,在上述实施方式中,示出了第一含金属膜是铝且第二含金属膜(防反射膜)是氮化钛的例子,但第一含金属膜也可以是铝合金,第二含金属膜也可以是钛。
此外,在上述实施方式中,示出了钝化膜是氧化硅膜与氮化硅膜的层叠膜的例子,但也可以采用氧化硅膜或者氮化硅膜的单层膜。

Claims (12)

1.一种半导体装置的制造方法,其特征在于,具有以下工序:
形成包含第一含金属膜以及层叠在该第一含金属膜上的防反射膜的导电膜,其中所述防反射膜由与所述第一含金属膜不同的第二含金属膜构成;
对所述导电膜进行构图;
在构图后的所述导电膜的侧面形成侧壁保护膜;
在形成有所述侧壁保护膜的状态下蚀刻去除构图后的所述导电膜中的所述防反射膜;
以覆盖所述第一含金属膜和所述侧壁保护膜的方式形成钝化膜;以及
在所述钝化膜形成使所述第一含金属膜的上表面的一部分露出的开口部。
2.根据权利要求1所述的半导体装置的制造方法,其特征在于,
形成所述侧壁保护膜的工序包含以下工序:
形成对构图后的所述导电膜的上表面和侧面进行覆盖的绝缘膜;以及
对所述绝缘膜进行回蚀,直至所述防反射膜的上表面露出为止。
3.根据权利要求2所述的半导体装置的制造方法,其特征在于,
在对所述绝缘膜进行回蚀的工序中,蚀刻去除所述防反射膜。
4.根据权利要求1所述的半导体装置的制造方法,其特征在于,
所述侧壁保护膜是氧化硅膜或者氮化硅膜。
5.根据权利要求1至4中的任意一项所述的半导体装置的制造方法,其特征在于,
所述第一含金属膜是铝或者铝合金,所述第二含金属膜是氮化钛或者钛。
6.根据权利要求5所述的半导体装置的制造方法,其特征在于,
所述导电膜在所述第一含金属膜的下层还包含由钛、氮化钛或者二者的层叠膜构成的势垒金属层。
7.根据权利要求1所述的半导体装置的制造方法,其特征在于,
所述钝化膜是氧化硅膜、氮化硅膜或者二者的层叠膜。
8.一种半导体装置,其特征在于,具有:
由含金属膜构成的焊盘和布线,它们在同一布线层中以1μm以下的间隔相邻设置;
侧壁保护膜,其设置在所述焊盘和所述布线各自的侧面;以及
钝化膜,其覆盖所述焊盘及所述布线各自的上表面和所述侧壁保护膜的表面,具有使所述焊盘的上表面的一部分露出的开口部,
所述钝化膜直接接触于所述焊盘及所述布线各自的上表面。
9.根据权利要求8所述的半导体装置,其特征在于,
所述侧壁保护膜是氧化硅膜或者氮化硅膜。
10.根据权利要求8或9所述的半导体装置,其特征在于,
所述含金属膜是铝或者铝合金。
11.根据权利要求8或9所述的半导体装置,其特征在于,
在所述含金属膜的下层还包含由钛、氮化钛或者二者的层叠膜构成的势垒金属层。
12.根据权利要求8所述的半导体装置,其特征在于,
所述钝化膜是氧化硅膜、氮化硅膜或者二者的层叠膜。
CN201811561987.9A 2018-02-05 2018-12-20 半导体装置的制造方法和半导体装置 Pending CN110120334A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018018424A JP7032159B2 (ja) 2018-02-05 2018-02-05 半導体装置の製造方法および半導体装置
JP2018-018424 2018-02-05

Publications (1)

Publication Number Publication Date
CN110120334A true CN110120334A (zh) 2019-08-13

Family

ID=67475190

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811561987.9A Pending CN110120334A (zh) 2018-02-05 2018-12-20 半导体装置的制造方法和半导体装置

Country Status (5)

Country Link
US (1) US10892163B2 (zh)
JP (1) JP7032159B2 (zh)
KR (1) KR20190095095A (zh)
CN (1) CN110120334A (zh)
TW (1) TW201941258A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111725436A (zh) * 2020-06-09 2020-09-29 武汉华星光电半导体显示技术有限公司 基板及其制备方法、显示面板

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5443827A (en) 1977-09-16 1979-04-06 Sintokogio Ltd Mold making machine
JP3638778B2 (ja) * 1997-03-31 2005-04-13 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
JP2001217246A (ja) 2000-02-04 2001-08-10 Toshiba Corp 半導体装置及びその製造方法
JP4623949B2 (ja) 2003-09-08 2011-02-02 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP2006303452A (ja) 2005-03-25 2006-11-02 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP5443827B2 (ja) 2009-05-20 2014-03-19 ルネサスエレクトロニクス株式会社 半導体装置
TWI371998B (en) * 2009-11-03 2012-09-01 Nan Ya Printed Circuit Board Printed circuit board structure and method for manufacturing the same
JP2014165276A (ja) 2013-02-22 2014-09-08 Seiko Instruments Inc 半導体装置
JP6300533B2 (ja) 2014-01-15 2018-03-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111725436A (zh) * 2020-06-09 2020-09-29 武汉华星光电半导体显示技术有限公司 基板及其制备方法、显示面板

Also Published As

Publication number Publication date
KR20190095095A (ko) 2019-08-14
JP2019135751A (ja) 2019-08-15
TW201941258A (zh) 2019-10-16
US20190244808A1 (en) 2019-08-08
JP7032159B2 (ja) 2022-03-08
US10892163B2 (en) 2021-01-12

Similar Documents

Publication Publication Date Title
US5631499A (en) Semiconductor device comprising fine bump electrode having small side etch portion and stable characteristics
KR100658547B1 (ko) 반도체 장치 및 그 제조 방법
KR100388590B1 (ko) 반도체 장치
EP1440470B1 (en) Method of wire bonding a microelectronic die
CA1304831C (en) Integrated circuit having laser-alterable metallization layer
CN110120334A (zh) 半导体装置的制造方法和半导体装置
JPH04192333A (ja) 半導体装置
CN211428157U (zh) 一种改善半导体器件可靠性的结构
JPS6112047A (ja) 半導体装置の製造方法
KR100568794B1 (ko) 반도체 소자의 금속 배선 형성 방법
JP3726529B2 (ja) 半導体装置
JPH02144921A (ja) 半導体装置
TW405216B (en) Manufacturing the metal contact lines on a semiconductor wafer
KR100220796B1 (ko) 반도체 기판의 범프 에어리어 형성방법
KR100290910B1 (ko) 반도체소자의 배선 형성방법
JP3329148B2 (ja) 配線形成方法
US7682958B2 (en) Method for producing an integrated circuit including a fuse element, a fuse-memory element or a resistor element
JPH10233395A (ja) 半導体装置の配線およびその製造方法
CN116154055A (zh) 抗老化led芯片的制作方法
JPS62171144A (ja) バンブ形成法
JP2000012586A (ja) 電極バンプの形成方法
JPH04264733A (ja) 集積回路装置のバンプ電極用下地膜の形成方法
JPS61141157A (ja) 半導体素子の製造方法
JPS624352A (ja) 半導体記憶装置
JPS6133257B2 (zh)

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20190813