CN110073467A - 用于提供低k间隔物的方法 - Google Patents
用于提供低k间隔物的方法 Download PDFInfo
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- CN110073467A CN110073467A CN201780077978.XA CN201780077978A CN110073467A CN 110073467 A CN110073467 A CN 110073467A CN 201780077978 A CN201780077978 A CN 201780077978A CN 110073467 A CN110073467 A CN 110073467A
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Abstract
提供了一种形成具有间隔物的半导体器件的方法。在特征的侧面上形成SiCO间隔物。在所述SiCO间隔物的第一部分上形成保护性覆盖物,其中所述SiCO间隔物的所述侧壁的第二部分未被所述保护性覆盖物覆盖。对所述SiCO间隔物的未被所述保护性覆盖物覆盖的所述第二部分提供转变工艺,这改变了所述SiCO间隔物的未被所述保护性覆盖物覆盖的所述第二部分的物理性质,其中所述保护性覆盖物保护所述SiCO间隔物的所述第一部分不受所述转变工艺的影响。
Description
相关申请的交叉引用
本申请要求2016年12月16日提交的美国申请No.15/381,594的优先权权益,其通过引用并入本文以用于所有目的。
技术领域
本公开涉及一种用于在半导体晶片上形成半导体器件的方法。更具体地,本公开涉及提供具有低介电常数的间隔物。
在形成半导体器件中,侧壁间隔物形成在特征的侧面上。侧壁间隔物可能导致寄生电容。
发明内容
为了实现前述内容并且根据本公开的目的,提供了一种形成具有间隔物的半导体器件的方法。在特征的侧面上形成SiCO间隔物。在所述SiCO间隔物的第一部分上形成保护性覆盖物,其中所述SiCO间隔物的所述侧壁的第二部分未被所述保护性覆盖物覆盖。对所述SiCO间隔物的未被所述保护性覆盖物覆盖的所述第二部分提供转变工艺,从而改变所述SiCO间隔物的未被所述保护性覆盖物覆盖的所述第二部分的物理性质,其中所述保护性覆盖物保护所述SiCO间隔物的所述第一部分不受所述转变工艺的影响。
在另一表现形式中,提供了一种用于形成具有间隔物的半导体器件的方法。在特征的侧面上形成SiCO间隔物。在所述SiCO间隔物的顶部和侧壁的一部分上形成保护帽,其中所述SiCO间隔物的所述侧壁的底部部分未被所述保护帽覆盖。对所述SiCO间隔物的所述侧壁的未被所述保护帽覆盖的所述部分提供转变工艺,这降低了所述SiCO间隔物的所述侧壁的未被所述保护帽覆盖的所述部分的k值,其中所述保护帽保护所述SiCO间隔物的所述侧壁的被覆盖部分不受所述转变工艺的影响。
本发明的这些特征和其它特征将在下面在本发明的详细描述中并结合以下附图进行更详细的描述。
附图说明
在附图中以实施例而非限制的方式示出了本公开,并且附图中相似的附图标记表示相似的元件,其中:
图1是一种实施方案的高阶流程图。
图2A-图2H是根据一种实施方案处理的叠层的示意性横截面图。
具体实施方式
现在将参考附图中所示的几个优选实施方案来详细描述本发明。在下面的描述中,阐述了许多具体细节以便提供对本发明的彻底理解。然而,对于本领域技术人员显而易见的是,本发明可以在没有这些具体细节中的一些或全部的情况下实施。在其他情况下,未详细描述公知的工艺步骤和/或结构,以免不必要地使本发明不清楚。
图1是一种实施方案的高阶流程图。在该实施方案中,在特征的侧面上形成硅碳氧化物(SiCO)间隔物(步骤104)。在SiCO间隔物的侧壁的部分和顶部上形成保护帽,其中SiCO间隔物的侧壁的底部部分未被保护帽覆盖(步骤108)。对SiCO间隔物的侧壁的未被保护帽覆盖的暴露部分提供转变工艺,这降低了SiCO间隔物的侧壁的暴露部分的k值,其中保护帽保护SiCO间隔物的侧壁的被覆盖的部分不受转变工艺的影响(步骤112)。去除保护帽(步骤116)。覆盖SiCO间隔物的侧壁的未被保护帽覆盖的暴露的底部部分(步骤120)。将SiCO间隔物的顶部暴露于蚀刻或CMP工艺(步骤124)。
实施例
在该实施例中,在特征的侧面上形成SiCO间隔物(步骤104)。图2A是具有带有特征208的衬底204的叠层200的示意性剖视图。在该实施例中,这些特征具有多晶栅极(polygate)的底部212和栅极盖的顶部216。SiCO间隔物220形成在特征208的侧面上。可以使用不同的方法在特征208的侧面上形成SiCO间隔物220。在一实施例中,可以在特征208和衬底上形成共形SiCO层。可以蚀刻掉共形SiCO层的水平表面,留下SiCO间隔物220。在特征208和间隔物220上沉积旋涂硬掩模(SOH)224。部分蚀刻SOH 224以暴露特征208和间隔物220的顶部。图2B是在SOH 224已被部分蚀刻以暴露特征208和间隔物220的顶部之后的叠层的示意性剖视图。
在SiCO间隔物220的侧壁的部分和顶壁上以及在特征208的顶部上方形成保护帽,其中SiCO间隔物的侧壁的底部部分未被保护帽覆盖(步骤108)。在该实施例中,通过沉积共形保护层来形成帽。在一实施例中,通过使5-30sccm的CH4或CH3F和100-200sccm的Ar流过处理室来提供帽形成气体,同时将室压保持在3mTorr至5mTorr之间。通过向室提供100瓦至600瓦的RF功率,将帽形成气体转变成等离子体。使该过程持续10至30秒,这导致形成共形保护层。图2C是在SiCO间隔物220的侧壁的部分和顶壁上以及在特征208的顶部上形成共形保护层228之后的叠层200的示意性剖视图。共形保护层228在SOH层224的顶部上形成。去除共形保护层228的在SOH层224的顶部上的部分和SOH层224。用于去除共形保护层228的在SOH层224的顶部上的部分和SOH层224的配方使去除气体N2和H2或H2和CO2或N2和O2以50至200sccm流动,同时保持20毫托至60毫托的压强。通过向室提供300至1000瓦的RF功率,使去除气体形成等离子体。使该过程持续30至120秒,直到除去SOH 224和共形保护层228的某些部分。图2D是在去除保护层的一部分和SOH层之后的叠层200的示意性剖视图。保护层的剩余部分在SiCO间隔物220的侧壁的部分和顶部之上以及在特征208的顶部上方形成保护帽232。SiCO间隔物224的侧壁的底部部分未被保护帽232覆盖。
对SiCO间隔物的侧壁的未被保护帽覆盖的暴露部分提供转变工艺,这降低了SiCO间隔物的侧壁的暴露部分的k值,其中保护帽保护SiCO间隔物的侧壁的覆盖部分不受转变工艺的影响(步骤112)。用于提供转变工艺的配方的实施例将2000至4000sccm O2和500sccm N2的转变气体流入处理室,同时保持1至2托的压强和200℃至300℃的温度。通过向室提供3000至4000瓦的RF功率,使转变气体形成等离子体。使该工艺持续30至60秒直到通过降低暴露部分的k值,使SiCO间隔物的暴露部分转变。图2E是在提供转变工艺之后的叠层200的示意性剖视图。已经处理SiCO间隔物220的侧壁的底部236以降低SiCO间隔物的介电k值。在该实施例中,k值从4.9降低到4.4。
去除保护帽(步骤116)。用于去除保护帽的配方的实施例使5至20sccm CF4或SF6和150sccm He的帽去除气体流动,同时保持5至30mTorr的压强。通过向室提供300至1000瓦的RF功率,使帽去除气体形成为等离子体。处理时间基于保护帽的厚度。图2F是在去除保护帽之后的叠层200的示意性剖视图。
可以在这些步骤之前或之后或之间提供附加步骤以进一步处理叠层。例如,在形成SiCO间隔物之后并且在形成保护帽之前,可以在特征之间形成源区和漏区。在去除保护帽之后的工艺的实施例中,可以沉积介电层以填充间隔物之间的空间。沉积的介电层使得SiCO间隔物的侧壁的未被保护帽覆盖的暴露的底部部分被覆盖(步骤120)。在一实施例中,可以使用可流动的亚大气压化学气相沉积或原子层沉积的氧化物来沉积所沉积的介电层。图2G是在沉积介电层240以填充侧壁间隔物之间的空间之后的叠层200的示意性剖视图。SiCO间隔物的顶部暴露于蚀刻或化学机械抛光(CMP)工艺(步骤124)。图2H是在SiCO间隔物的顶部经过CMP工艺之后的叠层200的示意性剖视图。自对准触点可以电连接到特征的顶部。
该实施例利用通过暴露于各种基于等离子体的化学物质来改变单前体活化自由基化学(SPARC)膜的性质的能力,例如使得这样的膜对于蚀刻相互作用和稀释的氢氟酸(dHF)湿润清洁不太稳健,同时降低介电k值。
在该实施例中,保护帽保护侧壁间隔物的顶部部分不受转变工艺的影响,这降低了侧壁间隔物的未受保护的下部部分的k值。结果,侧壁间隔物的顶部保持其较高的碳含量和耐蚀刻性。在该实施例中,侧壁的底部部分可以暴露于降低k值并且使得侧壁的底部部分不太耐蚀刻的转变工艺,使得侧壁的底部部分比侧壁的受保护部分较易受湿HF或等离子体蚀刻的影响。因为侧壁的底部部分抗蚀刻性较差,所以沉积介电层以保护侧壁的底部部分并进一步形成器件。
由加利福尼亚州弗里蒙特的Lam Research Corp.制造的激励室可用于沉积SiCO侧壁。
优选地,SiCO侧壁间隔物最初具有介于4.7和4.9之间(包括4.7和4.9)的介电常数k。转变工艺将介电常数k降低至少0.4。结果,经转变的SiCO侧壁具有小于4.5的介电常数。结果,介电常数降低了约8%至10%。因此寄生电容降低了约8%至10%。
在其他实施方案中,可以保护侧壁间隔物的其他部分而不是顶部免受转变工艺的影响,同时侧壁间隔物的其他部分而不是底部可以暴露于转变工艺。这些实施方案可用于解决多个集成设计。其他实施方案可以使用其他转变工艺步骤来降低侧壁间隔物的k值。例如,代替使用基于O2的灰化,可以使用基于形成气体的灰化。形成气体是气体氢气和氮气。这种气体可以由N2和H2或NH3或NH4OH或这些气体的组合形成。在其他实施方案中,可以使用其他转变工艺来改变侧壁间隔物的其他物理特性,而不是降低k值。
寄生电容是高级finfet器件中的关键性能限制器。接触电容的栅极是7nm节点及以上的总有效电容的主要驱动因素。在7nm节点,寄生电容占有效电容的约40%。因此,寄生电容的显著降低将导致有效电容的显著降低。
虽然已经根据几个优选实施方案描述了本发明,但是存在落在本发明的范围内的改变、修改、置换和各种替代等同方案。还应当注意,存在实现本发明的方法和装置的许多替代方式。因此,以下所附权利要求旨在被解释为包括落在本发明的真实精神和范围内的所有这样的改变、修改、置换和各种替代等同方案。
Claims (20)
1.一种形成具有间隔物的半导体器件的方法,其包括:
在特征的侧面上形成SiCO间隔物;
在所述SiCO间隔物的第一部分上形成保护性覆盖物,其中所述SiCO间隔物的所述侧壁的第二部分未被所述保护性覆盖物覆盖;以及
对所述SiCO间隔物的未被所述保护性覆盖物覆盖的所述第二部分提供转变工艺,从而改变所述SiCO间隔物的未被所述保护性覆盖物覆盖的所述第二部分的物理性质,其中所述保护性覆盖物保护所述SiCO间隔物的所述第一部分不受所述转变工艺的影响。
2.根据权利要求1所述的方法,其中所述SiCO间隔物的所述第一部分是所述SiCO间隔物的顶部和所述SiCO间隔物的所述侧壁的顶部部分,并且其中所述SiCO间隔物的所述第二部分是所述SiCO间隔物的所述侧壁的底部部分,并且其中所述保护性覆盖物形成保护帽。
3.根据权利要求2所述的方法,其中所述转变工艺将所述SiCO间隔物的所述第二部分的k值降低至少0.4。
4.根据权利要求3所述的方法,其还包括在提供所述转变工艺之后去除所述保护帽。
5.根据权利要求4所述的方法,其还包括覆盖所述SiCO间隔物的经过所述转变工艺的所述第二部分。
6.根据权利要求5所述的方法,其中所述覆盖所述SiCO间隔物的经过所述转变工艺的所述第二部分包括用介电层填充所述SiCO间隔物之间的空间。
7.根据权利要求6所述的方法,其还包括将所述SiCO间隔物的所述顶部暴露于蚀刻或化学机械抛光(CMP)。
8.根据权利要求7所述的方法,其中所述转变工艺包括将所述SiCO间隔物的未被所述保护帽覆盖的所述第二部分暴露于由包含氧气的气体或由形成气体形成的等离子体。
9.根据权利要求8所述的方法,其中所述形成所述保护帽包括:
在所述SiCO间隔物之间提供牺牲层,其中所述SiCO间隔物的所述顶部暴露;
在所述SiCO间隔物的所述顶部上方和所述牺牲层的顶部上方沉积保护层;以及
去除在所述牺牲层的所述顶部上方的所述保护层的部分和所述牺牲层。
10.根据权利要求2所述的方法,其中所述形成所述保护帽包括:
在所述SiCO间隔物之间提供牺牲层,其中所述SiCO间隔物的所述顶部暴露;
在所述SiCO间隔物的所述顶部上方和所述牺牲层的顶部上方沉积保护层;以及
去除在所述牺牲层的所述顶部上方的所述保护层的部分和所述牺牲层。
11.根据权利要求1所述的方法,其中所述转变工艺将所述SiCO间隔物的所述第二部分的k值降低至少0.4。
12.根据权利要求1所述的方法,其还包括在提供所述转变工艺之后去除所述保护性覆盖物。
13.根据权利要求1所述的方法,其还包括覆盖所述SiCO间隔物的经过所述转变工艺的所述第二部分。
14.根据权利要求1所述的方法,其还包括使所述SiCO间隔物的所述第一部分暴露于蚀刻或化学机械抛光(CMP)。
15.根据权利要求1所述的方法,其中所述转变工艺包括使所述SiCO间隔物的未被所述保护性覆盖物覆盖的所述第二部分暴露于由包含氧气的气体或由形成气体形成的等离子体。
16.一种用于形成具有间隔物的半导体器件的方法,其包括:
在特征的侧面上形成SiCO间隔物;
在所述SiCO间隔物的顶部和侧壁的一部分上形成保护帽,其中所述SiCO间隔物的所述侧壁的底部部分未被所述保护帽覆盖;以及
对所述SiCO间隔物的所述侧壁的未被所述保护帽覆盖的所述部分提供转变工艺,这降低了所述SiCO间隔物的所述侧壁的未被所述保护帽覆盖的所述部分的k值,其中所述保护帽保护所述SiCO间隔物的所述侧壁的被覆盖部分不受所述转变工艺的影响。
17.根据权利要求15所述的方法,其中所述转变工艺将所述SiCO间隔物的所述侧壁的未被所述保护帽覆盖的所述部分的所述k值降低至少0.4。
18.根据权利要求16所述的方法,其还包括在提供所述转变工艺之后去除所述保护帽。
19.根据权利要求17所述的方法,其还包括通过用介电层填充所述SiCO间隔物之间的空间来覆盖所述SiCO间隔物的所述侧壁的经过所述转变工艺的所述部分。
20.根据权利要求18所述的方法,其中所述转变工艺包括将所述SiCO间隔物的未被所述保护帽覆盖的所述第二部分暴露于由包含氧气的气体或由形成气体形成的等离子体。
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040222182A1 (en) * | 2003-05-09 | 2004-11-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for multiple spacer width control |
US20080090370A1 (en) * | 2006-10-12 | 2008-04-17 | Dyer Thomas W | Post-silicide spacer removal |
US20100267238A1 (en) * | 2009-04-20 | 2010-10-21 | Advanced Micro Devices, Inc. | Methods for fabricating finfet semiconductor devices using planarized spacers |
US20120171833A1 (en) * | 2010-12-31 | 2012-07-05 | Institute of Microelectronic Chinese Academy of Sc | Method for manufacturing semiconductor device |
US20130252430A1 (en) * | 2012-03-22 | 2013-09-26 | Tokyo Electron Limited | Method for reducing damage to low-k gate spacer during etching |
US20150145073A1 (en) * | 2013-11-26 | 2015-05-28 | Taiwan Semiconductor Manufacturing Company Limited | Low-k dielectric sidewall spacer treatment |
CN105895527A (zh) * | 2015-02-13 | 2016-08-24 | 台湾积体电路制造股份有限公司 | 具有数据存储结构的半导体结构及其制造方法 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10234735A1 (de) * | 2002-07-30 | 2004-02-12 | Infineon Technologies Ag | Verfahren zum vertikalen Strukturieren von Substraten in der Halbleiterprozesstechnik mittels inkonformer Abscheidung |
US7115974B2 (en) * | 2004-04-27 | 2006-10-03 | Taiwan Semiconductor Manfacturing Company, Ltd. | Silicon oxycarbide and silicon carbonitride based materials for MOS devices |
JP2007096002A (ja) | 2005-09-29 | 2007-04-12 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法および半導体装置 |
US7667263B2 (en) * | 2007-02-07 | 2010-02-23 | International Business Machines Corporation | Semiconductor structure including doped silicon carbon liner layer and method for fabrication thereof |
KR20100127668A (ko) * | 2009-05-26 | 2010-12-06 | 주식회사 하이닉스반도체 | 수직형 트랜지스터의 매몰 비트 라인 형성 방법 |
CN102110651B (zh) | 2009-12-29 | 2014-01-29 | 中国科学院微电子研究所 | 一种半导体器件及其制造方法 |
US8039386B1 (en) * | 2010-03-26 | 2011-10-18 | Freescale Semiconductor, Inc. | Method for forming a through silicon via (TSV) |
DE102010028462B4 (de) | 2010-04-30 | 2015-06-11 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verspannungsgedächtnistechnik mit geringerer Randzonenkapazität auf der Grundlage von Siliziumnitrid in MOS-Halbleiterbauelementen |
US9287385B2 (en) | 2011-09-01 | 2016-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-fin device and method of making same |
US8574978B1 (en) * | 2012-04-11 | 2013-11-05 | United Microelectronics Corp. | Method for forming semiconductor device |
US10832904B2 (en) * | 2012-06-12 | 2020-11-10 | Lam Research Corporation | Remote plasma based deposition of oxygen doped silicon carbide films |
US10297442B2 (en) * | 2013-05-31 | 2019-05-21 | Lam Research Corporation | Remote plasma based deposition of graded or multi-layered silicon carbide film |
KR102050779B1 (ko) * | 2013-06-13 | 2019-12-02 | 삼성전자 주식회사 | 반도체 소자 및 이의 제조 방법 |
JP6218459B2 (ja) * | 2013-07-02 | 2017-10-25 | キヤノン株式会社 | 除振装置、除振方法、リソグラフィ装置及びデバイスの製造方法 |
US9378975B2 (en) | 2014-02-10 | 2016-06-28 | Tokyo Electron Limited | Etching method to form spacers having multiple film layers |
US9171736B2 (en) | 2014-03-03 | 2015-10-27 | Tokyo Electron Limited | Spacer material modification to improve K-value and etch properties |
US9202751B2 (en) * | 2014-04-07 | 2015-12-01 | Globalfoundries Inc. | Transistor contacts self-aligned in two dimensions |
US9269792B2 (en) * | 2014-06-09 | 2016-02-23 | International Business Machines Corporation | Method and structure for robust finFET replacement metal gate integration |
US9478660B2 (en) * | 2015-01-12 | 2016-10-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Protection layer on fin of fin field effect transistor (FinFET) device structure |
US9437694B1 (en) | 2015-04-01 | 2016-09-06 | Stmicroelectronics (Crolles 2) Sas | Transistor with a low-k sidewall spacer and method of making same |
KR102251061B1 (ko) * | 2015-05-04 | 2021-05-14 | 삼성전자주식회사 | 변형된 채널층을 갖는 반도체 소자 및 그 제조 방법 |
US9385318B1 (en) * | 2015-07-28 | 2016-07-05 | Lam Research Corporation | Method to integrate a halide-containing ALD film on sensitive materials |
US9711533B2 (en) * | 2015-10-16 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices having different source/drain proximities for input/output devices and non-input/output devices and the method of fabrication thereof |
US9786765B2 (en) * | 2016-02-16 | 2017-10-10 | Globalfoundries Inc. | FINFET having notched fins and method of forming same |
-
2016
- 2016-12-16 US US15/381,594 patent/US10224414B2/en active Active
-
2017
- 2017-12-05 WO PCT/US2017/064761 patent/WO2018111627A1/en active Application Filing
- 2017-12-05 KR KR1020197019250A patent/KR102450406B1/ko active IP Right Grant
- 2017-12-05 CN CN202310671148.7A patent/CN116884845A/zh active Pending
- 2017-12-05 CN CN201780077978.XA patent/CN110073467B/zh active Active
- 2017-12-05 KR KR1020227033843A patent/KR102610396B1/ko active IP Right Grant
- 2017-12-12 TW TW106143448A patent/TWI745505B/zh active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040222182A1 (en) * | 2003-05-09 | 2004-11-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for multiple spacer width control |
US20080090370A1 (en) * | 2006-10-12 | 2008-04-17 | Dyer Thomas W | Post-silicide spacer removal |
US20100267238A1 (en) * | 2009-04-20 | 2010-10-21 | Advanced Micro Devices, Inc. | Methods for fabricating finfet semiconductor devices using planarized spacers |
US20120171833A1 (en) * | 2010-12-31 | 2012-07-05 | Institute of Microelectronic Chinese Academy of Sc | Method for manufacturing semiconductor device |
US20130252430A1 (en) * | 2012-03-22 | 2013-09-26 | Tokyo Electron Limited | Method for reducing damage to low-k gate spacer during etching |
US20150145073A1 (en) * | 2013-11-26 | 2015-05-28 | Taiwan Semiconductor Manufacturing Company Limited | Low-k dielectric sidewall spacer treatment |
CN105895527A (zh) * | 2015-02-13 | 2016-08-24 | 台湾积体电路制造股份有限公司 | 具有数据存储结构的半导体结构及其制造方法 |
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KR102610396B1 (ko) | 2023-12-06 |
US10224414B2 (en) | 2019-03-05 |
KR102450406B9 (ko) | 2023-12-15 |
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US20180175161A1 (en) | 2018-06-21 |
WO2018111627A1 (en) | 2018-06-21 |
CN116884845A (zh) | 2023-10-13 |
KR20220137174A (ko) | 2022-10-11 |
KR20190088065A (ko) | 2019-07-25 |
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