CN109994436A - 具有集成电气功能的基于pcb的半导体封装 - Google Patents
具有集成电气功能的基于pcb的半导体封装 Download PDFInfo
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- CN109994436A CN109994436A CN201910122931.1A CN201910122931A CN109994436A CN 109994436 A CN109994436 A CN 109994436A CN 201910122931 A CN201910122931 A CN 201910122931A CN 109994436 A CN109994436 A CN 109994436A
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Abstract
本发明涉及具有集成的电气功能的基于PCB的半导体封装。半导体封装包括金属基板、具有附接到基板的参考端子和背向基板的RF端子的半导体管芯、以及具有附接到基板的第一侧和背向基板的第二侧的多层电路板。该多层电路板包括多个交错的信号层和接地层。各信号层中的一个在多层电路板的第二侧处并且被电气连接到半导体管芯的RF端子。各接地层中的一个在多层电路板的第一侧处并且被附接到金属基板。功率分配结构形成在多层电路板的第二侧处的信号层中。RF匹配结构形成在各信号层中的与功率分配结构不同的信号层中。
Description
本申请是申请日为2016年7月28日、申请号为201610602194.1以及发明名称为“具有集成电气功能的基于PCB的半导体封装”的发明专利申请的分案申请。
技术领域
本申请涉及RF功率封装,特别地基于PCB(印刷电路板)的封装RF功率应用。
背景技术
陶瓷气腔和塑料气腔/外模(overmold)封装被广泛地用于RF/微波分立功率晶体管。这两种类型的封装提供可靠且易于处理的处理机械设计。然而,陶瓷气腔和塑料气腔/外模封装由于它们的层叠和预先确定的物理尺寸而难以以电气意义来设计。
发明内容
根据半导体封装的一个实施例,该半导体封装包括:具有管芯附接区和外围区的金属基板;具有附接到管芯附接区的参考端子和背向基板的RF端子的晶体管管芯;以及多层电路板,其具有附接到外围区的第一侧和背向基板的第二侧,该多层电路板包括多个交错的信号层和接地层。各信号层中的第一信号层在多层电路板的第二侧处并且电气连接到晶体管管芯的RF端子。各接地层中的第一接地层在第一信号层下面。各信号层中的第二信号层在第一接地层下面并且通过延伸通过第一接地层的绝缘通孔电气连接到第一信号层。各接地层中的第二接地层在多层电路板的第一侧处并且被附接到金属基板。
根据半导体封装的另一实施例,该半导体封装包括:金属基板;具有附接到基板的参考端子和背向基板的RF端子的半导体管芯;以及具有附接到基板的第一侧和背向基板的第二侧的多层电路板。多层电路板包括多个交错的信号层和接地层。各信号层中的一个在多层电路板的第二侧处并且被电气连接到半导体管芯的RF端子。各接地层中的一个在多层电路的第一侧处并且被附接到金属基板。功率分配结构被形成在多层电路板的第二侧处的信号层中。RF匹配结构被形成在各信号层中的与功率分配结构不同的信号层中。
根据半导体组件的一个实施例,该半导体组件包括衬底和附接到该衬底的半导体封装。该半导体封装包括金属基板、具有附接到基板的参考端子和背向基板的RF端子的半导体管芯、以及具有附接到基板的第一侧和背向基板的第二侧的多层电路板。该多层电路板包括多个交错的信号层和接地层。各信号层中的一个在多层电路板的第二侧处并且被电气连接到半导体管芯的RF端子。各接地层中的一个在多层电路板的第一侧处并且被附接到金属基板。功率分配结构被形成在多层电路板的第二侧处的信号层中。RF匹配结构被形成在各信号层中的与功率分配结构不同的信号层中。
本领域技术人员在阅读下面的详细描述时且在查看附图时将认识到附加的特征和优点。
附图说明
图的元件没必要相对于彼此按照比例来绘制。相似的参考数字表示对应的类似部分。各个图示的实施例的特征可以被组合除非它们彼此排斥。在图中描绘实施例并且在下面的描述中详细描述该实施例。
图1图示具有多层电路板的半导体封装的局部截面图。
图2A和2B图示用于图1中示出的多层电路板的信号通孔结构的不同实施例。
图3A图示在半导体封装的多层电路板和子系统/系统电路板之间的接口的局部透视图。
图3B图示在具有多层电路板的半导体封装的附接之前图3A的子系统/系统电路板的局部透视图。
图4图示在具有多层电路板的半导体封装的输出侧处的不同电气功能的高级示意性表示。
图5图示利用半导体封装的输出侧的不同电气功能实施的多层电路板的混合视图。
图6示意性地图示在具有功率分配网络和平衡功率组合器的半导体封装的输出侧处实施的半导体封装的多层电路板的一个实施例。
图7图示利用功率分配网络和平衡功率组合器实施的图5中示出的多层电路板的最高信号层的自顶向下(top down)俯视图。
图8示意图性地图示利用谐波终端(harmonic termination)谐振器实施的图5中示出的多层电路板的中间信号层的一个实施例。
图9图示具有形成在半导体封装的多层电路板中的功率分配网络络、平衡功率组合器和谐波终端谐振器的半导体封装的局部透视图。
图10图示在具有多层电路板的半导体封装的输入侧处的不同电气功能的高级示意性表示。
图11图示具有形成在半导体封装的输入侧处的多层电路板中的RF匹配以及功率分配和组合结构的半导体封装的局部透视图。
具体实施方式
接下来描述的是基于PCB(印刷电路板)的功率半导体封装的实施例,在其中封装也被当作只代替机械部件的系统的电气设计的一部分。这样做对设计提供灵活性,改进集成并且在提供更紧凑物理大小的同时增强性能。通过将分立封装的概念与电气设计意义上的子系统模块组合,在还提升系统的电气性能并降低最终电路物理尺寸的同时仍实现设计灵活性。
这里描述的实施例为高设计集成提供基于多层有机PCB的封装。PCB最少有四层,其中的两层是接地层。信号层和接地层可以交错以降低干扰并改进性能。可以在PCB的一个或多个信号层中形成RF匹配以及功率分配和组合结构。例如,用于提供谐波终端的集成谐波谐振器可以被形成在PCB的各信号层中的一个或多个中以提供高效率的功率放大器等级功能。平衡功率组合器网络可以被形成在PCB的各信号层中的一个或多个中以提供跨越大管芯外围或大焊盘尺寸的均匀功率分配。此外或可替代地,基于PCB的封装可以具有交错的接地-信号-接地焊盘连接以用于提供基于PCB的封装和另一电路板之间的高频率和高可靠性电气接触。
图1图示根据一个实施例的半导体封装的局部截面图。功率半导体封装包括具有管芯附接区102和外围区104的金属基板100、附接到基板100的管芯附接区102的晶体管管芯106、用于向晶体管管芯106提供电气连接的多层电路板108(诸如PCB)、以及用于封闭晶体管管芯106的可选盖子110。基板100由导电且导热的材料(诸如Cu、CPC(铜、铜-钼、铜层压结构)、CuW等等)制成。在一些情况下,附接到基板100的晶体管管芯106是功率晶体管管芯,诸如RF放大器管芯。例如,晶体管管芯106可以是LDMOS(横向扩散金属氧化物半导体)、垂直功率MOSFET(金属氧化物半导体场效应晶体管)或GaN RF功率晶体管管芯。晶体管管芯106具有附接到管芯附接区102的参考端子112(诸如源极或发射极端子)和背向基板100的RF端子114(诸如漏极或集电极端子)。晶体管管芯的控制(栅极)端子在图1的视图之外。例如在多赫尔蒂(Doherty)放大器(在其中主放大器以及一个或多个峰值放大器可以被附接到基板100)的情况下,多于一个晶体管管芯可以被附接到基板100。
一般来说,多层电路板108具有附接到基板100的外围区104的第一侧116和背向基板100的第二侧118。多层电路板108延伸超过基板100的外部侧壁120以用于到另一电路板122的附接。另一电路板122属于并入半导体封装的子系统或系统。该电路板122可以具有用于接收半导体封装的基板100的凹进区。金属块124可以被设置在凹进中以用于增强与半导体封装的基板100的热和电气接口。包括例如铜的铝的散热器126可以被附接到附加电路板122的背面128。
多层电路板108的延伸超过基板100的外部侧壁120的部分被附接到另一电路板122的正面130。半导体封装的多层电路板108包括多个交错的信号层和接地层。图1中示出的示例具有四个层:两个接地层132、134和两个信号层136、138,它们彼此交错。一般来说,多层电路板108可以具有两个或更多个信号层以及两个或更多个接地层。最底层132是具有附接到半导体封装的基板100和其他电路板122二者的接地焊盘140的接地层。也就是说,多层电路板108的最底层132的接地焊盘140被附接到金属基板100并且还延伸超过基板100的外部侧壁120以用于到其他电路板122的附接。
多层电路板108的最高层138形成半导体封装的主RF信号层并且通过一个或多个电导体142(诸如一个或多个接合线、带状物、金属夹等等)电气连接到晶体管管芯106的RF端子114。主RF信号层138还可以通过绝缘信号通孔144电气连接到另一电路板122的正面130,该绝缘信号通孔144延伸通过多层电路板108到达形成在多层电路板108的最底接地层132中的信号焊盘146。在最底接地层132处的信号焊盘146被定位成超过基板100的外部侧壁120并且与最底层132处的接地焊盘140分开以确保适当的电气隔离。
中间接地层134被设置在主RF信号层138下面,并且中间信号层136被设置在该接地层134下面且在最底接地层132上面。中间信号层136通过绝缘信号通孔148电气连接到主RF信号层138,该绝缘信号通孔148延伸通过介于中间信号层136和主RF信号层138之间的接地层134。以类似的方式,接地层132、134通过绝缘接地通孔150电气连接。如果需要的话,多层电路板108可以具有附加的交错接地层和信号层。
图2A图示用于在多层电路板108的整个厚度上电气连接多层电路板108的最高信号层138的绝缘信号通孔144的一个实施例的截面图。根据该实施例,在铜通孔和顶部焊盘202邻近最高信号层138中的盖200的情况下,绝缘信号通孔144包括盖200,诸如铜盖。电镀穿通孔204垂直延伸通过多层电路板108,可选地经由对应的掩埋焊盘202来接触一个或多个中间信号层136。在铜通孔和底部焊盘208形成在最底接地层132的情况下,绝缘信号通孔144的底部包括盖206(诸如铜盖)。底盖206和焊盘208通过多层电路板108的介电材料210(诸如聚四氟乙烯、FR-1、FR-2、FR-3、FR-4、FR-5、FR-6、G-10、CEM-1、CEM-2、CEM-3、CEM-4、CEM-5等等)与最底接地层132的接地金属轨道/焊盘电气绝缘。非导电树脂212可以填充电镀穿通孔204。图1中示出的接地通孔150可以具有与图2A中示出的相同或相似的构造。
图2B图示根据一个实施例的用于将多层电路板108的最高信号层138电气连接到掩埋在多层电路板108中的中间信号层136的各绝缘信号通孔148中的一个的实施例的截面图。根据该实施例,在铜通孔和顶部焊盘222邻近最高信号层138中的盖220的情况下,绝缘信号通孔148包括盖220,诸如铜盖。电镀的盲孔224部分地通过多层电路板108垂直延伸到中间信号层136。绝缘信号通孔148的底部包括焊盘226,其接触中间信号层136的信号金属轨道。电镀的盲孔224通过介电材料228(诸如上文结合图2A描述的那种)与介于最高信号层138和中间信号层136之间的接地层134电绝缘。
通过利用这样的多层电路板构造,可以实现到包括在半导体封装中的每个晶体管管芯106的优化电气连接。例如,在晶体管管芯106是RF高功率放大器管芯的情况下,从半导体封装的多层电路板108到子系统/系统电路板122的电磁场传播对功率放大器的高频性能是关键的。电磁场传播可以被优化以实现高频下的高性能。例如,在存在接地通孔150的情况下,信号通孔144、148的电感被降低。接地通孔150为RF返回路径提供平滑的垂直过渡,从而降低信号通孔144、148的总环路电感,这进而降低回波损耗。在图1中,利用向右的箭头强调RF信号电流路径并且利用向左的箭头强调返回路径。
图3A图示在半导体封装的多层电路板108和子系统/系统电路板122之间的接口的一个实施例。图3中没有示出多层电路板108的介电材料,使得信号和接地金属轨道以及信号和接地通孔每一个都至少部分可见。根据该实施例,多层电路板108的最高信号层138包括多个信号金属轨道300(诸如微带线),它们通过延伸通过多层电路板108的绝缘信号通孔302电气连接到多层电路板108底侧处的相应信号焊盘146(图3A的视图之外)。在多层电路板108的底侧处的接地焊盘140(也在图3A的视图之外)与信号焊盘146分开并与其交错。接地焊盘140通过延伸通过多层电路板108的绝缘接地通孔304电气连接到多层电路板108的接地层132、134。如图3中所示,接地层132、134每一个可以包括单个金属薄片306,然而,其他配置是可能的,诸如多个接地金属轨道,诸如多个薄片或带状线。此外或可替代地,在一些实施例中接地金属轨道308可以部分在最高信号层138上延伸。在每种情况下,子系统/系统电路板122具有交错的接地和信号焊盘310、312,其与半导体封装的多层电路板108的交错的接地/信号焊盘配置相对应。电路板108、122可以在这些连接点处彼此焊接,例如通过如图1中示出的相应焊接接头152、154、156。
图3B示出在半导体封装的放置和附接之前的子系统/系统电路板122。子系统/系统电路板122可以具有用于接收半导体封装的基板100的凹进区314。图3A中示出多层电路板108的延伸超过基板100外部侧壁120的部分,并且通过交错的接地和信号焊盘310、312将其附接到子系统/系统电路板122的前侧。子系统/系统电路板122可以包括用于连接到子系统/系统电路板122的一个或多个其他接地层的绝缘接地通孔316。可以制成类似的通孔连接用于系统/系统电路板122的信号金属轨道,但是为了便于说明没有示出。图3A和3B中示出的交错的接地-信号-接地配置提供半导体封装的多层电路板108和子系统/系统电路板122之间电场的高效垂直传播。
除了上文解释的交错的接地-信号-接地配置之外或者对其进行替代,可以在半导体封装的多层电路板108的信号层136、138中形成RF匹配以及功率分配和组合结构。这样,多层电路板108可以将机械功能和电气功能二者合并到半导体封装的设计中。
图4图示可以被合并在多层电路板108中的半导体封装输出侧处的不同电气功能的高级示意性表示。示出具有源极端子(S)、漏极端子(D)和栅极端子(G)的单个晶体管部件,其可以表示一个或多个物理晶体管管芯。在该示例中,如本文先前描述的那样,功率晶体管的源极端子通过多层电路板108的最底层132电气连接到地,并且功率晶体管的漏极端子电气连接到多层电路板108的最高信号层138。多层电路板108具有介于最高信号层138和最底接地层132之间的一个或多个附加信号层136。还如本文先前描述的那样,附加的接地层134介于垂直邻近的信号层136、138之间。在多层电路板108的信号层136、138中形成RF匹配以及功率分配和组合结构。
例如,通过图4中的电感L1来表示多层电路板108的最高信号层138和功率晶体管的漏极端子之间的电气连接。多层电路板108的最高信号层138可以包括由传输线TL1表示的功率分配网络。功率分配网络可以被耦合到谐波终端谐振器,其被配置成捕获存在于晶体管的RF端子(例如漏极)处信号中的杂散谐波。谐波终端谐振器可以包括由传输线TL2表示的二次谐波终端谐振器,由传输线TL3表示的三次谐波终端谐振器,等等。可以在多层电路板108的与功率分配网络不同的信号层中形成谐波终端谐振器。除了功率分配网络之外,最高信号层138还可以包括由传输线TL4表示的用于组合谐波终端谐振器的输出的平衡功率组合器。由电感L2表示从半导体封装的多层电路板108到子系统/系统电路板122的电气连接。上文描述的RF匹配以及功率分配和组合结构可以被形成在多层电路板108的信号层136、138中。
图5图示半导体封装的多层电路板108的截面图,其中各种示意性覆盖图示出可以形成在多层电路板108的信号层136、138中的RF匹配以及功率分配和组合结构的示例性类型。例如,功率组合器网络(A)和集成无源部件(诸如输出电容器(B1、B2)和电感器(C1、C2、C3、C4))可以被形成在路由于多层电路板108的最高层138上的金属轨道中。集成无源部件形成准集总传输线器件。
集成谐波终端结构可以被形成在多层电路板108的最高信号层138下面的一个或多个信号层136中,以用于捕获存在于晶体管的RF端子处信号中的杂散谐波。例如,具有等于2fo(二次谐波终端)或3fo(三次谐波终端)处的四分之一波长的电气长度的断开短截线谐振器(D1)、准集总谐振器(D2)、辐射状短截线谐振器(D3)、方形开环谐振器(D4)、折叠臂方形开环谐振器(D5)、弯曲线方形开环谐振器(D6)、双模方形开环谐振器(D7)等等可以被形成在多层电路板108的一个或多个中间信号层136中。
在一个示例中,方形开环谐振器可以被用来设计在2fo具有高抑制的输出处的准椭圆低通滤波器,从而允许与标准断开短截线谐振器相比功率放大器的带宽的增加。还有其他谐波终端谐振器类型和配置可以被形成在多层电路板108的最高信号层138下面的(一个或多个)信号层136中。
阻抗变换网络可以被形成在与谐波终端谐振器相同或不同的中间信号层中。阻抗变换网络被配置成将晶体管的RF端子处的较低阻抗变换成较高阻抗。在一个实施例中,阻抗变换网络包括形成在信号层136、138中的一个中的辐射状短截线(D3)。如本文先前描述的那样,接地层134介于垂直邻近的信号层136、138之间。
为了实现高功率输出,宽的指长度外围通常被用于晶体管管芯106。这意味着大(宽)的晶体管管芯大小。例如,可以通过每个都具有针对同一晶体管管芯106而预先限定的外围长度的子单位单元的并行布置来实现宽的指长度外围。常规晶体管管芯的漏极接合焊盘通常被连接到宽引线,导致高电流密度仅在引线的边缘上,这暗示同一晶体管管芯的各单位单元之间的不平衡振幅和相移。
图6示意性地图示在半导体封装(其中功率分配网络400和平衡功率组合器402形成在多层电路板108的最高信号层138中)的输出侧实施的半导体封装的多层电路板108的一个实施例。在该示例中,晶体管管芯106被示出具有八个单位单元(1-8)。每个单位单元都贡献总体晶体管管芯信号容量的一部分。并行地布置单位单元的输出。多层电路板108的最高信号层138包括对于每个单位单元输出的分开的金属信号轨道(8*Zi)。单位单元输出可以被一个或多个电导体(诸如一个或多个接合线、带状物、金属夹等等)电气连接到相应的金属信号轨道。在每种情况下,功率分配网络400在不同层级处继续扇入(例如在该示例中从8个轨道、到4个轨道、到2个轨道),每个层级中的金属信号轨道(X*Zi)在宽度方面是前一层级的两倍。平衡功率组合器402在功率分配网络400的每个金属轨道(X*Zi)处在振幅和相位方面相等地分配电流。在图6中,Zi表示观察晶体管管芯106的每个单位单元的阻抗,并且Zo表示半导体封装的输出将与其匹配的阻抗(在该示例中为50Ω)。
图7图示利用图6中示意性示出的功率分配网络400和平衡功率组合器402实施的多层电路板108的最高信号层138的自顶向下俯视图。在一些实施例中,在最高信号层138中形成的用来实现功率分配网络400和平衡功率组合器402的金属信号轨道可以包括图案化的铜金属化404。
图8示意性地图示利用谐波终端谐振器结构500实施的多层电路板108的中间信号层136的一个实施例。中间信号层136被设置在多层电路板108的最高信号层138下面。在该示例中,金属信号轨道被布置成在中间信号层136中形成二次谐波终端结构502和三次谐波终端结构504。接地层134可以介于在具有谐波终端谐振器结构500的中间信号层136和最高信号层138之间。谐波终端谐振器结构500在一端处可以通过第一组绝缘信号通孔(图8中未示出)电气连接到形成在最高信号层138中的功率分配网络结构400,并且在另一端处可以通过第二组绝缘信号通孔(图8中未示出)电气连接到形成在最高信号层138中的平衡功率组合器402。
谐波终端谐振器结构500被形成多层电路板108的与功率分配网络400和平衡功率组合器402不同的信号层136,以便降低RF匹配部件和谐波终端谐振器结构500之间的不想要的寄生电感耦合或电气耦合,这进而降低归因于寄生耦合效应的损耗。谐波终端谐振器结构500可以具有如图8中示出的带状线配置以便具有良好受控的介电常数,意味着谐波终端谐振器502、504具有受控的电气长度和非常精确的谐振频率。此外,带状线被上覆的和下面的接地平面层良好地屏蔽。
图9图示具有形成在半导体封装的输出侧处的多层电路板108中的例如上述种类的功率分配网络600、平衡功率组合器602和谐波终端谐振器604的半导体封装的一个实施例。一些电导体606将半导体管芯608的RF输出端子连接到形成在多层电路板108的最高信号层138中的第一多个信号金属轨道610。这些信号金属轨道610形成功率分配网络600,其跨越晶体管管芯608的宽度(W)分配功率。设置在最高信号层138下面的中间信号层136包括形成谐波终端谐振器604的多个信号金属轨道612。
最高信号层138还包括与形成功率分配网络600的信号金属轨道610分开的第二多个信号金属轨道614。最高信号层138的这些附加信号金属轨道614形成平衡功率组合器602。形成谐波终端谐振器604的中间信号层136的信号金属轨道612通过第一组绝缘信号通孔616电气连接到形成功率分配网络600的第一信号金属轨道610的相应第一信号金属轨道,并且通过第二组绝缘信号通孔618连接到形成平衡功率组合器602的第二信号金属轨道614的相应第二信号金属轨道。图9中未示出介于最高信号层138和中间信号层136之间的中间接地层134和多层电路板108的介电材料,以使得信号金属轨道和对应的信号通孔至少部分可见。
最高信号层138还可以包括与分别形成功率分配网络600和平衡功率组合器602的第一和第二信号金属轨道610、614分开的多个接地金属轨道620。如图9中所示,形成最高信号层138的平衡功率组合器602和接地金属轨道620的信号金属轨道614可以在多层电路板108的顶侧交错。最高信号层138的接地金属轨道620通过延伸通过多层电路板108的绝缘接地通孔622电气连接到多层电路板108的底侧处的最底接地层132。形成平衡功率组合器602的信号金属轨道614可以通过延伸通过多层电路板108的绝缘信号通孔626电气连接到多层电路板108的底侧处的相应信号焊盘624。多层电路板108底侧处的信号焊盘626和接地焊盘628彼此分开和交错。照此,要被附接到子系统/系统电路板630的多层电路板108的输出部分可以具有交错的接地-信号-接地配置(GND/SIG/GND/SIG/GND),例如如本文先前结合图3A和3B描述的那样。子系统/系统电路板630具有与多层电路板108的输出侧相同的交错的接地-信号-接地配置(GND/SIG/GND/SIG/GND)。
图10图示可以被合并到多层电路板中的半导体封装的输入侧处的不同电气功能的高级表示。示出具有源极端子(S)、漏极端子(D)和栅极端子(G)的单个晶体管部件,其可以表示一个或多个物理晶体管管芯。在该示例中,功率晶体管的源极端子通过多层电路板108的最底层132电气连接到地,并且功率晶体管的栅极端子被电气连接到多层电路板108的最高信号层138。多层电路板108具有介于最高信号层138和最底接地层132之间的一个或多个附加信号层136。还如本文先前描述的那样,附加的接地层134介于每个信号层136、138之间。RF匹配以及功率分配和组合结构被形成在半导体封装的输入侧处的多层电路板的信号层136、138中。
例如,集成匹配部件(诸如辐射状短截线Stub1)可以被形成在多层电路板108的最高信号层138下面的中间信号层136中。集成匹配部件提供在晶体管的栅极和子系统/系统板之间的阻抗匹配。集成阻抗匹配部件通过由电感L3(其与两个板之间的物理连接的电感相对应)表示的过渡连接到子系统/系统板。多层电路板108的最高信号层138具有由传输线TL1示意性表示的平衡功率组合器和功率分配网络。功率组合器和功率分配网络可以被设置在与包括集成阻抗匹配部件的信号层136不同的同一信号层138中。
功率组合器在一端处被电气连接到集成匹配部件并且在另一端处被电气连接到功率分配网络。功率分配网络的相对端通过输入匹配网络电气连接到晶体管的栅极端子。输入匹配网络包括到由串联电感L1和L2、分流电容器SRC1和二次谐波终端结构SLC1表示的栅极端子的电气连接。输入匹配网络可以被集成到多层电路板108的一个或多个信号层1326、138中或者被提供为分立无源部件,例如诸如在电容器的情况下的集成无源器件。
图11图示具有形成在半导体封装的输入侧处的多层电路板108中的RF匹配以及功率分配和组合结构(例如上文先前结合图10描述的那种)的半导体封装的一个实施例。根据该实施例,输入匹配网络被实施为引线接合连接700和分立电容器702。输入匹配网络在一端处连接到晶体管管芯706的栅极端子704并且在另一端处连接到功率分配网络708。功率分配网络708包括形成在多层电路板108的最高信号层138中的第一多个金属信号轨道710。平衡功率组合器712由形成在最高信号层138中的第二多个金属信号轨道714形成。形成为辐射状短截线716的集成阻抗匹配部件被设置在多层电路板108的下面的中间信号层136中的一个中。辐射状短截线716通过一个或多个绝缘信号通孔718电气连接到形成平衡功率组合器712的第二信号金属轨道714的相应第二信号金属轨道。图11中未示出介于最高信号层138和具有多层电路板108的介电材料和辐射状短截线716的中间信号层136之间的中间接地层134,以使得信号金属轨道和对应信号通孔至少部分可见。
最高信号层138还可以包括与平衡功率组合器712的金属轨道714分开的多个接地金属轨道720。如图11中所示,形成在最高信号层138中的接地金属轨道720和平衡功率组合器712可以在多层电路板108的顶侧交错。最高信号层138的接地金属轨道720可以通过延伸通过多层电路板108的绝缘接地通孔722电气连接到多层电路板108底侧处的最底接地层132。平衡功率组合器712通过延伸通过多层电路板108的绝缘信号通孔724电气连接到多层电路板108的底侧处的信号焊盘。多层电路板108的底侧处的接地焊盘和信号焊盘(二者都在图11的视图之外)彼此分开和交错。照此,要被附接到子系统/系统电路板726的多层电路板108的输入部分可以具有交错的接地-信号-接地配置(GND/SIG/GND)。子系统/系统电路板726具有与多层电路板108的输入侧相同的交错的接地-信号-接地配置(GND/SIG/GND)。
诸如“在……下”、“在……下面”、“下部”、“在……上”、“在……上面”等等的空间相对术语被用来便于描述以解释一个元件相对于第二元件的定位。这些术语意图包括除了与图中描绘的那些不同的定向之外的设备的不同定向。此外,诸如“第一”、“第二”等等之类的术语也被用来描述各种元件、区域、部分等等,并且也不意图是限制性的。相似的术语指代遍及该描述的相似元件。
如本文所使用的,术语“具有”、“包含”、“包括”、“含有”等等是指示所述元件或特征的存在的开放端术语,但不排除附加的元件或特征。冠词“一”、“一个”、和“该”意图包括复数形式以及单数形式,除非上下文另外明确指出。
要理解,本文中描述的各种实施例的特征可以彼此组合,除非另外具体指出。
尽管本文已经图示和描述了具体实施例,但是本领域普通技术人员将会认识到在不偏离本发明范围的情况下多种替代和/或等同实施方式可以代替所示且描述的具体实施例。本申请意图覆盖本文讨论的具体实施例的任何改编或变化。因此,意图的是,本发明仅由权利要求及其等同物来限制。
Claims (17)
1.一种多赫尔蒂放大器,其包括:
具有管芯附接区和外围区的金属基板;
主放大器和一个或多个峰值放大器,其中每个放大器都包括晶体管管芯,所述晶体管管芯包含RF端子;
多层电路板,该多层电路板包括:与多个接地层交错的多个信号层,所述多个信号层包括至少第一和第二信号,所述多个接地层包含至少第一和第二接地层;附接到所述外围区的第一侧,其中所述第一接地层在所述第一侧处;背向所述基板的第二侧,其中所述第一信号层在所述第二侧处;
电路结构,所述电路结构被电气连接到放大器晶体管管芯中的至少一个放大器晶体管管芯的RF端子,并且所述电路结构包括第一部分和第二部分,其中:所述第一部分和所述第二部分中的一个形成在所述第一信号层上;并且所述第一部分和所述第二部分中的另一个形成在至少所述第二信号层上,而没有形成在所述第一信号层上。
2.根据权利要求1所述的多赫尔蒂放大器,其中,所述电路结构的所述第一部分包括RF功率分配网络和RF功率组合器网络中的至少一个。
3.根据权利要求1所述的多赫尔蒂放大器,其中,所述电路结构的所述第二部分包括阻抗变换网络和谐波终端谐振器中的至少一个。
4.根据权利要求3所述的多赫尔蒂放大器,其中:
所述电路结构的所述第一部分包括形成在所述第一信号层上的RF功率分配网络和RF功率组合器网络;以及
所述RF功率分配网络经由所述电路结构的所述第二部分连接到所述RF功率组合器网络,所述电路结构的所述第二部分没有形成在所述第一信号层上。
5.根据权利要求1所述的多赫尔蒂放大器,其中,所述电路结构的所述第一部分包括RF功率组合器网络,所述RF功率组合器网络连接到主放大器晶体管管芯和一个或多个峰值放大器晶体管管芯的所述RF端子。
6.根据权利要求5所述的多赫尔蒂放大器,其中,所述RF功率组合器网络经由阻抗变换网络连接到所述放大器晶体管管芯的至少一个RF端子,所述阻抗变换网络包括所述电路结构的所述第二部分。
7.根据权利要求1所述的多赫尔蒂放大器,其中:
所述第一接地层附接到所述金属基板;
所述第二接地层在所述第一信号层下面;以及
所述第二信号层在所述第一接地层下面,并且通过延伸通过所述第二接地层的绝缘通孔电气连接到所述第一信号层。
8.根据权利要求1所述的多赫尔蒂放大器,其中:
所述第一信号层包括电气连接到至少一个放大器晶体管管芯的所述RF端子的第一多个信号金属轨道;以及
所述第二信号层包括通过绝缘通孔电气连接到所述第一信号层的所述第一多个信号金属轨道的相应信号金属轨道的第一多个信号金属轨道。
9.根据权利要求8所述的多赫尔蒂放大器,其中:
所述第一信号层包括与所述第一信号层的所述第一多个信号金属轨道分开的第二多个信号金属轨道;以及
所述第二信号层的所述第一多个信号金属轨道通过第一组绝缘通孔电气连接到所述第一信号层的所述第一多个信号金属轨道的相应信号金属轨道,并且通过第二组绝缘通孔电气连接到所述第一信号层的所述第二多个信号金属轨道的相应信号金属轨道。
10.根据权利要求9所述的多赫尔蒂放大器,其中:
所述第一信号层包括与所述第一信号层的所述第一多个信号金属轨道和所述第二多个信号金属轨道分开的多个接地金属轨道;以及
所述第一信号层的所述第二多个信号金属轨道和所述多个接地金属轨道在所述多层电路板的所述第二侧处交错。
11.根据权利要求10所述的多赫尔蒂放大器,其中,所述第一信号层的所述多个接地金属轨道通过延伸通过所述多层电路板的绝缘通孔电气连接到所述多层电路板的所述第一侧处的所述第二接地层。
12.根据权利要求11所述的多赫尔蒂放大器,其中,所述第一信号层的所述第二多个信号金属轨道通过延伸通过所述多层电路板的绝缘通孔电气连接到所述多层电路板的所述第一侧处的相应信号焊盘。
13.根据权利要求1所述的多赫尔蒂放大器,其中,所述第一接地层包括介于在所述第一信号层和所述第二信号层之间的单个金属薄片。
14.根据权利要求1所述的多赫尔蒂放大器,其中:
所述第一接地层包括接地焊盘和信号焊盘;
所述第一接地层的所述接地焊盘附接到所述金属基板并且延伸超过所述基板的外部侧壁;以及
所述信号焊盘与所述接地焊盘间隔开,并且被定位成超过所述基板的所述外部侧壁。
15.一种半导体组件,其包括:
衬底;以及
附接到该衬底且包括根据权利要求1所述的多赫尔蒂放大器的半导体封装。
16.根据权利要求15所述的半导体组件,其中所述多赫尔蒂放大器的多层电路板的第一侧处的第一接地层包括:
附接到所述多赫尔蒂放大器的金属基板的第一组接地焊盘;
被定位成超过所述基板的外部侧壁且附接到所述衬底的接地焊盘的第二组接地焊盘;以及
被定位成超过所述基板的所述外部侧壁且附接到所述衬底的信号焊盘的一组信号焊盘。
17.根据权利要求15所述的半导体组件,还包括在所述多赫尔蒂放大器的多层电路板的第一侧处的接地焊盘,其中:
所述接地焊盘被电气连接到所述多层电路板的接地层并且与信号焊盘交错;以及
所述接地焊盘被附接到所述衬底的接地焊盘。
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Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102015212232B4 (de) * | 2015-06-30 | 2020-03-05 | TRUMPF Hüttinger GmbH + Co. KG | Leistungscombiner zur Kopplung von Hochfrequenzsignalen und Leistungscombineranordnung mit einem solchen Leistungscombiner |
US10225922B2 (en) * | 2016-02-18 | 2019-03-05 | Cree, Inc. | PCB based semiconductor package with impedance matching network elements integrated therein |
US10741476B2 (en) | 2017-04-19 | 2020-08-11 | Infineon Technologies Ag | Passive electrical component with thermal via |
US10332847B2 (en) * | 2017-06-01 | 2019-06-25 | Infineon Technologies Ag | Semiconductor package with integrated harmonic termination feature |
US10141303B1 (en) | 2017-09-20 | 2018-11-27 | Cree, Inc. | RF amplifier package with biasing strip |
US20190150296A1 (en) * | 2017-11-10 | 2019-05-16 | Raytheon Company | Additive manufacturing technology microwave vertical launch |
US10673387B2 (en) * | 2017-12-05 | 2020-06-02 | Nxp Usa, Inc. | Amplifiers with in-package radial stub harmonic traps |
US10685925B2 (en) | 2018-01-26 | 2020-06-16 | Nvidia Corporation | Resistance and capacitance balancing systems and methods |
CN110213880B (zh) * | 2018-02-28 | 2020-08-25 | 苏州旭创科技有限公司 | 柔性电路板、电路板组件、光收发组件及光模块 |
US10622736B2 (en) * | 2018-07-10 | 2020-04-14 | Futurewei Technologies, Inc. | Harmonic termination integrated passive device |
WO2021119898A1 (zh) * | 2019-12-16 | 2021-06-24 | 瑞声声学科技(深圳)有限公司 | 传输线 |
US11769768B2 (en) * | 2020-06-01 | 2023-09-26 | Wolfspeed, Inc. | Methods for pillar connection on frontside and passive device integration on backside of die |
US11342289B2 (en) * | 2020-09-01 | 2022-05-24 | Intel Corporation | Vertical power plane module for semiconductor packages |
JP7491188B2 (ja) | 2020-11-09 | 2024-05-28 | 株式会社デンソー | 電気機器 |
CN117202545B (zh) * | 2023-08-30 | 2024-05-10 | 山东航天电子技术研究所 | 一种宇航模块电源的高密度封装结构 |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3966196A (en) * | 1974-01-14 | 1976-06-29 | Roland Offsetmaschinenfabrik Faber & Schleicher Ag | Sheet delivery mechanism |
US5609889A (en) * | 1995-05-26 | 1997-03-11 | Hestia Technologies, Inc. | Apparatus for encapsulating electronic packages |
US6329713B1 (en) * | 1998-10-21 | 2001-12-11 | International Business Machines Corporation | Integrated circuit chip carrier assembly comprising a stiffener attached to a dielectric substrate |
US20030150641A1 (en) * | 2002-02-14 | 2003-08-14 | Noyan Kinayman | Multilayer package for a semiconductor device |
US20050146390A1 (en) * | 2004-01-07 | 2005-07-07 | Jae-Myung Baek | Multi-layer substrate having impedance-matching hole |
CN101202256A (zh) * | 2006-07-19 | 2008-06-18 | 英飞凌科技股份公司 | 功率放大器 |
CN101308727A (zh) * | 2007-04-13 | 2008-11-19 | 阿维科斯公司 | 焊盘格栅穿心低等效串联电感技术 |
CN101625730A (zh) * | 2008-07-07 | 2010-01-13 | 国际商业机器公司 | 射频集成电路芯片封装及其制造方法 |
CN103367268A (zh) * | 2012-03-28 | 2013-10-23 | 英飞凌科技股份有限公司 | 基于pcb的射频功率封装窗口框架 |
US20130294041A1 (en) * | 2012-05-04 | 2013-11-07 | Sierra Wireless, Inc. | Uicc encapsulated in printed circuit board of wireless terminal |
CN103887264A (zh) * | 2012-12-21 | 2014-06-25 | 三星电机株式会社 | 预空间变换器、空间变换器、以及半导体装置检查设备 |
CN204332946U (zh) * | 2014-01-27 | 2015-05-13 | 半导体元件工业有限责任公司 | 半导体封装结构和电子封装结构 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3986196A (en) * | 1975-06-30 | 1976-10-12 | Varian Associates | Through-substrate source contact for microwave FET |
JPH06295962A (ja) | 1992-10-20 | 1994-10-21 | Ibiden Co Ltd | 電子部品搭載用基板およびその製造方法並びに電子部品搭載装置 |
US5622588A (en) | 1995-02-02 | 1997-04-22 | Hestia Technologies, Inc. | Methods of making multi-tier laminate substrates for electronic device packaging |
US5597643A (en) | 1995-03-13 | 1997-01-28 | Hestia Technologies, Inc. | Multi-tier laminate substrate with internal heat spreader |
US5843808A (en) | 1996-01-11 | 1998-12-01 | Asat, Limited | Structure and method for automated assembly of a tab grid array package |
JPH10242377A (ja) | 1997-02-25 | 1998-09-11 | Hitachi Ltd | 高周波電力増幅器モジュール |
US5973389A (en) | 1997-04-22 | 1999-10-26 | International Business Machines Corporation | Semiconductor chip carrier assembly |
US6261868B1 (en) | 1999-04-02 | 2001-07-17 | Motorola, Inc. | Semiconductor component and method for manufacturing the semiconductor component |
US6511866B1 (en) | 2001-07-12 | 2003-01-28 | Rjr Polymers, Inc. | Use of diverse materials in air-cavity packaging of electronic devices |
JP2003179181A (ja) | 2001-12-11 | 2003-06-27 | Ngk Spark Plug Co Ltd | 樹脂製配線基板 |
JP3813098B2 (ja) | 2002-02-14 | 2006-08-23 | 三菱電機株式会社 | 電力用半導体モジュール |
DE10223035A1 (de) | 2002-05-22 | 2003-12-04 | Infineon Technologies Ag | Elektronisches Bauteil mit Hohlraumgehäuse, insbesondere Hochfrequenz-Leistungsmodul |
JP2004158605A (ja) | 2002-11-06 | 2004-06-03 | Konica Minolta Holdings Inc | プリント配線基板、及びプリント配線基板の導電性筐体への取付方法 |
US7298046B2 (en) | 2003-01-10 | 2007-11-20 | Kyocera America, Inc. | Semiconductor package having non-ceramic based window frame |
US7446411B2 (en) | 2005-10-24 | 2008-11-04 | Freescale Semiconductor, Inc. | Semiconductor structure and method of assembly |
US8013429B2 (en) | 2009-07-14 | 2011-09-06 | Infineon Technologies Ag | Air cavity package with copper heat sink and ceramic window frame |
US8110915B2 (en) | 2009-10-16 | 2012-02-07 | Infineon Technologies Ag | Open cavity leadless surface mountable package for high power RF applications |
JP5765174B2 (ja) | 2011-09-30 | 2015-08-19 | 富士通株式会社 | 電子装置 |
-
2015
- 2015-07-28 US US14/811,325 patent/US9629246B2/en active Active
-
2016
- 2016-07-28 CN CN201910122931.1A patent/CN109994436B/zh active Active
- 2016-07-28 DE DE102016113946.7A patent/DE102016113946B4/de active Active
- 2016-07-28 CN CN201610602194.1A patent/CN106409783B/zh active Active
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3966196A (en) * | 1974-01-14 | 1976-06-29 | Roland Offsetmaschinenfabrik Faber & Schleicher Ag | Sheet delivery mechanism |
US5609889A (en) * | 1995-05-26 | 1997-03-11 | Hestia Technologies, Inc. | Apparatus for encapsulating electronic packages |
US5776512A (en) * | 1995-05-26 | 1998-07-07 | Hestia Technologies, Inc. | Apparatus for encapsulating electronic packages |
US6329713B1 (en) * | 1998-10-21 | 2001-12-11 | International Business Machines Corporation | Integrated circuit chip carrier assembly comprising a stiffener attached to a dielectric substrate |
US20020038913A1 (en) * | 1998-10-21 | 2002-04-04 | Farquhar Donald S. | Integrated circuit chip carrier assembly |
US6503821B2 (en) * | 1998-10-21 | 2003-01-07 | International Business Machines Corporation | Integrated circuit chip carrier assembly |
US20030150641A1 (en) * | 2002-02-14 | 2003-08-14 | Noyan Kinayman | Multilayer package for a semiconductor device |
US20050146390A1 (en) * | 2004-01-07 | 2005-07-07 | Jae-Myung Baek | Multi-layer substrate having impedance-matching hole |
CN101202256A (zh) * | 2006-07-19 | 2008-06-18 | 英飞凌科技股份公司 | 功率放大器 |
CN101308727A (zh) * | 2007-04-13 | 2008-11-19 | 阿维科斯公司 | 焊盘格栅穿心低等效串联电感技术 |
CN101625730A (zh) * | 2008-07-07 | 2010-01-13 | 国际商业机器公司 | 射频集成电路芯片封装及其制造方法 |
CN103367268A (zh) * | 2012-03-28 | 2013-10-23 | 英飞凌科技股份有限公司 | 基于pcb的射频功率封装窗口框架 |
US20130294041A1 (en) * | 2012-05-04 | 2013-11-07 | Sierra Wireless, Inc. | Uicc encapsulated in printed circuit board of wireless terminal |
CN103887264A (zh) * | 2012-12-21 | 2014-06-25 | 三星电机株式会社 | 预空间变换器、空间变换器、以及半导体装置检查设备 |
CN204332946U (zh) * | 2014-01-27 | 2015-05-13 | 半导体元件工业有限责任公司 | 半导体封装结构和电子封装结构 |
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