CN109952654A - 在纳米线和纳米板处理中防止块体硅电荷转移的方法 - Google Patents

在纳米线和纳米板处理中防止块体硅电荷转移的方法 Download PDF

Info

Publication number
CN109952654A
CN109952654A CN201780069522.9A CN201780069522A CN109952654A CN 109952654 A CN109952654 A CN 109952654A CN 201780069522 A CN201780069522 A CN 201780069522A CN 109952654 A CN109952654 A CN 109952654A
Authority
CN
China
Prior art keywords
fin
substrate
fin structure
layered
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201780069522.9A
Other languages
English (en)
Other versions
CN109952654B (zh
Inventor
杰弗里·史密斯
安东·德维利耶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of CN109952654A publication Critical patent/CN109952654A/zh
Application granted granted Critical
Publication of CN109952654B publication Critical patent/CN109952654B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种制造半导体装置的方法，包括提供在其上具有层状鳍结构的衬底。所述层状鳍结构包括基底鳍部分、设置在所述基底鳍部分上的牺牲部分和设置在所述牺牲部分上的沟道部分。在所述衬底上在所述层状鳍结构上方提供掺杂源膜，并且使掺杂材料从所述掺杂源膜扩散到所述层状鳍结构的除所述沟道部分之外的一部分中，以在所述层状鳍结构中形成扩散掺杂区。在所述衬底上在所述层状鳍结构的至少所述扩散掺杂区上方提供隔离材料。

Description

在纳米线和纳米板处理中防止块体硅电荷转移的方法
发明背景
相关申请的交叉引用
本申请是基于2016年11月14日提交的美国临时申请号62/421,522并且要求所述美国临时申请的优先权权益，所述申请的全部内容以引用的方式并入本文中。
技术领域
本公开涉及一种制造诸如集成电路的半导体装置以及用于集成电路的晶体管和晶体管部件的方法。
背景技术
半导体装置的制造(特别是在微观尺度上)涉及各种制造工艺，诸如成膜沉积、蚀刻掩模形成、图案化、材料蚀刻和移除，以及掺杂处理，所述工艺被重复地执行以在衬底上形成期望的半导体装置元件。历史上，通过微制造，已经在一个平面中形成晶体管，其中布线/金属化形成在这种平面上方，并且因此已经被表征为二维(2D)电路或2D制造。缩放工作大大增加了2D电路中每单位面积的晶体管的数量，但随着缩放进入单个数字纳米半导体装置制造节点，缩放工作正面临更大的挑战。半导体装置制造商已经表达了对三维(3D)半导体装置的需要，在三维半导体装置中晶体管堆叠在彼此之上。
仍然需要提供改进的和高性能的半导体装置的缩放，并且需要对应的制造工艺。
发明内容
本公开的一个目标是提供改进电性能和可靠性的3D半导体装置和方法。这些和其他目标由本文中公开的实施方案提供，所述实施方案包括本发明的以下编号的示例方面。
(1)一种制造半导体装置的方法包括提供在其上具有层状鳍结构的衬底，所述层状鳍结构包括基底鳍部分、设置在所述基底鳍部分上的牺牲部分和设置在所述牺牲部分上的沟道部分。在所述衬底上在所述层状鳍结构上方提供掺杂源膜，并且使掺杂材料从所述掺杂源膜扩散到所述层状鳍结构的除所述沟道部分之外的一部分中，以在所述层状鳍结构中形成扩散掺杂区。在所述衬底上在所述层状鳍结构的至少所述扩散掺杂区上方提供隔离材料。
(2)如方面(1)所述的方法，其中所述提供衬底包括将所述基底鳍提供为由经掺杂Si的块体形成的块体鳍。在所述块体鳍上提供多层鳍结构，其中所述多层鳍结构包括将所述牺牲部分提供为与形成所述沟道部分的多个Si层交替的多个SiGe层
(3)如方面(2)所述的方法，其中所述多个Si层中的每一者形成纳米线或纳米板。
(4)如方面(2)所述的方法，其中所述提供掺杂源膜包括仅在所述层状鳍结构的一部分上方提供所述掺杂源膜，所述掺杂源膜的位置被选择以防止所述掺杂材料扩散到所述沟道部分中。
(5)如方面4所述的方法，其中选择所述掺杂源膜的所述位置以至少覆盖所述层状鳍结构的所述基底鳍部分的一部分。
(6)如方面5所述的方法，其中选择所述掺杂源膜的所述位置以覆盖所述层状鳍结构的所述基底鳍部分。
(7)如方面6所述的方法，其中选择所述掺杂源膜的所述位置以覆盖所述层状鳍结构的所述牺牲部分的一部分。
(8)如方面1所述的方法，其中所述扩散包括执行驱动退火加热以使所述掺杂材料扩散到所述层状鳍结构中。
(9)如方面8所述的方法，其中所述扩散还包括执行源极/漏极尖峰退火加热以使所述掺杂材料扩散到所述层状鳍结构中。
(10).如方面8所述的方法，其中所述扩散还包括调节所述驱动退火的时间和温度中的至少一者，以防止所述掺杂材料扩散到所述层状鳍结构的所述沟道部分中。
(11).如方面1所述的方法，其中所述提供隔离材料包括在所述衬底上形成浅沟槽隔离层以至少覆盖所述层状鳍结构的所述扩散掺杂区。
(12)如方面1所述的方法，所述方法还包括在所述层状鳍结构上方提供屏蔽层，掺杂源层设置在所述屏蔽层上。
(13)如方面1所述的方法，所述方法还包括在所述扩散之前在所述掺杂源层上方提供衬垫。
(14)另一方面包括一种半导体装置，所述半导体装置包括衬底和设置在所述衬底上的鳍结构。所述鳍结构包括：半导体材料的基底鳍部分，所述基底鳍部分包括扩散掺杂区；以及半导体材料的沟道部分，所述沟道部分设置在所述基底鳍部分上并与所述基底鳍部分竖直地间隔开。栅极结构布置在所述基底鳍部分与所述沟道部分之间并且包括导电材料，其中扩散掺杂区被配置为将所述基底鳍部分与所述栅极结构电隔离。隔离结构形成在所述衬底上并且至少覆盖所述扩散掺杂区。
(15)如方面14所述的半导体装置，其中所述鳍结构包括：块体鳍，所述块体鳍提供为所述基底鳍部分并由经掺杂半导体材料块体形成；以及多个竖直堆叠的半导体层，所述半导体层提供为所述沟道部分。所述多个竖直堆叠的半导体层彼此间隔开并掺杂为与所述掺杂半导体材料相同的极性类型。所述扩散掺杂区具有与所述掺杂半导体材料相反的极性类型以提供所述块体鳍的反向掺杂。
(16).如方面15所述的半导体装置，其中所述多个Si层中的每一者形成纳米线或纳米板。
(17)如方面15所述的半导体装置，其中所述经掺杂半导体材料块体包括p型掺杂材料。
(18)如方面16所述的半导体装置，其中所述多个竖直堆叠的半导体层各自包括p型掺杂材料。
(19)如方面15所述的半导体装置，其中所述扩散掺杂区包括n型掺杂材料。
(20)如方面19所述的半导体装置，其中所述n型掺杂材料包括磷或砷。
附图说明
并入本说明书中并构成本说明书的一部分的附图示出了一个或多个实施方案，并与描述一起用来解释这些实施方案。附图不一定按比例绘制。附图中示出的任何值尺寸仅用于说明目的，并且可能代表或可能不代表实际或优选的值或尺寸。在适用的情况下，可能未示出一些或所有特征以帮助描述基础特征。在附图中：
图1是根据本公开的某些方面的用于形成具有块体鳍隔离的半导体装置的制造过程的流程图。
图2是根据本公开的某些方面的具有块体鳍隔离的半导体装置的透视截面图；
图3A是根据本公开的某些方面的用于制造图2的装置的示例起始结构的透视截面图；
图3B是根据本公开的某些方面的在制造图2的装置的过程中的示例中间结构的透视截面图；
图3C是根据本公开的某些方面的在制造图2的装置的过程中的示例中间结构的透视截面图；
图3D是根据本公开的某些方面的在制造图2的装置的过程中的示例中间结构的透视截面图；
图3E是根据本公开的某些方面的在制造图2的装置的过程中的示例中间结构的透视截面图；
图3F是根据本公开的某些方面的在制造图2的装置的过程中的示例中间结构的透视截面图；
图3G是根据本公开的某些方面的在制造图2的装置的过程中的示例中间结构的透视截面图；
图3H是根据本公开的某些方面的在制造图2的装置的过程中的示例中间结构的透视截面图；
图3I是根据本公开的某些方面的在制造图2的装置的过程中的示例中间结构的透视截面图；
图3J是根据本公开的某些方面的在制造图2的装置的过程中的示例中间结构的透视截面图；
图3K是根据本公开的某些方面的在制造图2的装置的过程中的示例中间结构的透视截面图；
图3L是根据本公开的某些方面的在制造图2的装置的过程中的示例中间结构的透视截面图；
图3M是根据本公开的某些方面的在制造图2的装置的过程中的示例中间结构的透视截面图；并且
图4是其中栅极电荷可以转移到相邻的栅极结构的半导体装置的透视截面图。
具体实施方式
本文中的技术涉及使用环绕栅极处理的装置制造，环绕栅极处理在纳米线FET(场效应晶体管)中或通过堆叠的互补FET装置并入了纳米线(或纳米板或纳米片)。环绕栅极(GAA)识别FET装置，其中金属栅极物理地环绕硅或硅/锗线，并且是三栅极工艺的进一步延伸，在三栅极工艺中栅极环绕硅或硅/锗鳍。对于鳍式FET，栅极在四条边中的三条边上环绕，而对于GAA FET装置，栅极环绕所有给定沟道(无论给定沟道是具有矩形还是圆形横截面)。一种GAA FET装置是纳米线FET。
图4示出了从沿着纳米线本身的取向看的GAA纳米线结构的透视图。如所见，所述装置包括衬底401，衬底401具有设置在其上的堆叠纳米线结构403的阵列。每个堆叠结构403包括块体鳍部分405，块体鳍部分405具有设置在其上的纳米线装置410和栅极结构420。块体鳍405是中间鳍结构的一部分，中间鳍结构被处理以形成纳米线装置410和栅极结构420。每个纳米线装置410包括纳米线沟道区411，纳米线沟道区411在其相对侧上具有源极/漏极区413。每个栅极结构420是围绕纳米线沟道区411的多层结构，其包括高k层421、功函数金属层423和栅极金属填充物425。盖407设置在每个鳍403上方，并且栅极间隔物427将栅极结构420与设置在相邻的堆叠的纳米线结构403之间的源极/漏极金属429电绝缘。浅沟槽隔离结构431设置在鳍结构403之间。
在GAA装置中，栅极金属425通过栅极触点(未示出)充电，并且电荷在经过纳米线、纳米片或纳米板411之前通过功函数金属423运载。期望通过并入介电栅极间隔物427而将到个别栅极的电荷包含在所选栅极内而不包含在相邻的源极/漏极条429内。然而，对于纳米线或纳米板设计，在线是通过中间过程从由硅和硅锗(例如)组成的多层鳍形成的情况下，在金属栅极结构的底部或基底处将存在残余的鳍。来自该鳍405的硅将类似地沉积高k膜421(诸如HfO)和沉积在其之上的功函数金属423(诸如TiN)。其结果可能是埋藏的鳍在特定栅极的充电期间变为带电的并且使该电荷由残余鳍结构运载到相邻栅极结构，从而导致电性能问题和/或装置故障。从图4中可以看出，到特定栅极的任何电荷可以通过功函数金属423转移到块体硅鳍，并且接着运载到相邻栅极。
根据本文中的发现，放置在金属栅极下方的块体硅鳍与金属栅极结构隔离。一种实现此情况的技术包括对块体硅进行反向掺杂以中和鳍并防止其在特定金属栅极的充电期间带电。反向掺杂不会影响将直接放置在块体硅鳍上方的实际纳米线或纳米片，因此与常规注入工艺相反，掺杂工艺受益于固体源掺杂方法。另一技术包括一种方法，其中块体硅鳍在金属栅极下方进一步充分凹陷，并且额外电介质层沉积在块体硅鳍上方。从工艺集成方法来看，凹陷技术可能更加困难，因为一旦完成硅线释放过程，就需要将电介质材料直接沉积到开口的替换栅极中。此外，材料将需要各向同性地凹陷在开口的替换栅极内以填充栅极底部，同时确保线没有残余的电介质沉积，并且栅极底部沉积的厚度足以防止电荷转移到块体硅鳍。本文中描述的技术将集中于通过固体源掺杂工艺来中和块体硅鳍的实施方案。本文中的这种工艺可以用来将磷或砷掺杂到预先掺杂了硼的硅鳍中。可以控制处理，使得不通过工艺集成流程直接对硅或硅锗纳米线或纳米片进行掺杂。
本文中的技术包括将块体鳍部分405与3D半导体装置的栅极部分隔离的集成和硬件方法。图1是根据本文中的实施方案的用于形成具有隔离的块体鳍部分的半导体装置的示例制造过程的流程图。该过程开始于提供具有包括沟道部分的层状鳍结构的衬底，如步骤101中所见。在步骤103中，在层状鳍结构上提供掺杂膜。在步骤105中，使掺杂材料从掺杂膜扩散，以形成层状鳍结构的除沟道部分之外的扩散掺杂部分。在步骤107中，在层状鳍结构的至少扩散掺杂部分上方提供隔离材料。
图2是根据本公开的实施方案的具有隔离的块体鳍部分的多沟道FET装置的透视截面图。图2示出了从沿着纳米线本身的取向看的GAA纳米线结构。类似于图4，所述装置包括衬底201，衬底201具有设置在其上的堆叠纳米线结构203的阵列。每个堆叠结构203包括块体鳍部分205，块体鳍部分205具有设置在其上的纳米线装置210和栅极结构220。鳍203包括扩散掺杂鳍区209以将块体鳍205与栅极金属隔离。每个纳米线装置210包括在其相对侧上具有源极/漏极区213的纳米线沟道区211，并且每个栅极结构220包括高k层221、功函数金属层223和栅极金属填充物225。盖207设置在每个鳍203上方，并且栅极间隔物227将栅极结构220与设置在相邻的堆叠的纳米线结构203之间的源极/漏极金属229电绝缘。浅沟槽隔离结构231设置在鳍结构203之间。
图3A至图3M示出了用于制造具有图2的结构的特定装置的示例过程中的各个阶段的结构。将参考图3A至图3M更详细地描述图1。如本领域中已知的，纳米线或纳米片可以由含交替的半导体材料(诸如Si和SiGe)的“鳍”结构形成。硅纳米线的形成可以通过鳍中的SiGe的各向同性蚀刻以及栅极间隔物材料的形成来实现，该栅极间隔物材料终止于栅极结构的任一端上的硅线的末端。类似地，可以通过相对于SiGe选择性地蚀刻鳍中的Si来形成SiGe纳米线。本文中的技术可适用于Si和SiGe纳米线或纳米片或纳米板，以及其他类似的半导体结构。为了便于解释本文中的实施方案，图1和图3A至图3M中的描述涉及生产硅纳米线的过程。因此，图1和图3A至图3M公开了一种将块体鳍与半导体装置的栅极结构隔离的集成和硬件方法。
回到图1，方法100可以以诸如图3A中所示的示例结构的半导体结构开始。所述结构示出了在装置处理的中间阶段的多层鳍阵列。所述结构包括衬底301，衬底301在其上具有鳍303的阵列。每个鳍303包括块体鳍305、用作牺牲部分的SiGe层307，以及用作沟道部分的Si纳米线309。将移除SiGe 307以在该过程中稍后释放纳米线309。在结构300A中，包括纳米线309的鳍结构由盖层311保护。
任选地，可以通过原子层沉积来沉积诸如SiO的屏蔽层313以在鳍303上方形成间隔物。该膜的并入是任选的，并且用于在下文讨论的驱动退火步骤期间控制磷或砷到鳍中的扩散。图3B中示出了示例屏蔽层313。
在图1的步骤103中，在层状鳍结构上提供掺杂膜。掺杂源膜用于使掺杂材料扩散到层状鳍结构的部分中。在一些实施方案中，在层状鳍结构的一部分上方提供掺杂源膜，以使掺杂剂扩散到层状鳍结构的对应部分中。然而，阻挡衬垫也可用于控制从掺杂源层到鳍的所选部分中的扩散。在图3的实施方案中，掺杂源膜315最初跨越整个鳍结构303设置在屏蔽层313上方，如图3C中所见。掺杂源膜315可以通过CVD或ALD沉积到鳍结构上。出于实际目的，如果所使用的块体硅是p型，其中硅已经是硼掺杂的，则掺杂源材料可以由n型材料，诸如磷或砷，诸如PSG或AsSG组成。
移除掺杂源层315的一部分开始于在衬底(多层鳍阵列)上沉积填充物材料，诸如可流动的SiO膜或旋涂的有机膜。这种填充物材料沉积可能导致材料过载。图3D是示出使用可流动的SiO填充材料317进入鳍阵列中的结果的示例图。然后在氮化物盖311上利用止挡件抛光过载的填充物材料317，氮化物盖311作为顶表面材料设置在鳍303的顶部，如图3E中所见。
填充物材料317相对于鳍阵列的顶部平面化后，填充物材料的任何后续凹陷更可控。例如，SiO填充物317可以与固体源掺杂膜315和屏蔽层313一起凹陷到下部纳米线309(或纳米板)与剩余块体硅鳍305之间的水平，如图3F中所见。这种凹陷端点可以用于包括形成装置的制造流程，其中硅线307将跨越NMOS和PMOS栅极两者使用，或者用于3D逻辑应用的公共栅极。对于并入了SiGe线的应用可以切换凹陷的定位。
可以以各种方式执行掺杂膜315和填充物317的凹陷。优选地，SiO填充物以对掺杂膜317的1:1的选择性各向同性地凹陷，使得在单个过程步骤中移除这些层。或者，SiO填充物317各向同性地凹陷，从而留下掺杂膜315跨越整个鳍303，并且接着可以使用随后的各向同性蚀刻或甚至原子层蚀刻(ALE)工艺来将暴露的掺杂源膜315从SiO填充物材料317已经凹陷的鳍中清除。可以执行随后的清洁步骤以确保所有掺杂材料从鳍中的硅线清除。
可以设置凹陷的SiO填充物317和掺杂膜315的位置以确保掺杂材料不会通过SiGe层307扩散到Si纳米线309中。使掺杂膜充分凹陷是有益的，因为通过SiGe的任何掺杂扩散必须在远处以避免对最底部的硅线或板掺杂。在图3F中，凹陷仅示出为向下到块体硅鳍305与最下部硅线309之间的水平，但是在其他实施方案中，该凹陷量可以任选地向下延伸到块体硅鳍307的最顶部表面下方。给定凹陷深度可以取决于所使用的掺杂物质和掺杂物质分别在硅和硅锗内的扩散。
在一个实施方案中，可以在扩散之前通过原子层沉积来沉积诸如SiN或BN的任选衬垫材料，如图3G中所见。该衬垫膜319可用于在驱动退火过程期间防止磷或砷掺杂物质的任何向外扩散。
回到图1，在步骤105中，使掺杂材料从掺杂膜扩散以在沟道部分外部形成层状鳍结构的扩散掺杂部分。也就是说，在图3A至图3M的堆叠的纳米线结构中，掺杂剂扩散到鳍303中，至少包括纳米线309。
掺杂材料的扩散可以通过专用的驱动退火过程提供，或者利用由随后的s/d尖峰退火提供的进一步扩散来提供。在图3A至图3M的示例中，执行驱动退火步骤以使掺杂物质(诸如磷或砷)扩散到块体硅鳍305中但不扩散到硅纳米线或纳米片309中。在某些情况下，扩散到在最下部硅纳米线309与块体硅鳍305的顶部之间的SiGe 307中可以是可接受的。例如，进一步扩散在源极/漏极尖峰退火期间可以是最小的，并且因此不足以扩散到硅纳米线309中。SiGe 307中的任何掺杂材料将在硅纳米线释放步骤期间出来。而且，可以调节驱动退火过程(时间和/或温度)，使得磷或砷掺杂剂的总扩散长度由驱动退火和尖峰退火的组合设置。
对于在驱动退火过程期间使用诸如SiN或BN的临时衬垫材料的实施方案，随后移除衬垫。当使用BN时，膜性质使得材料在驱动退火步骤期间可以闪蒸出，使得临时衬垫移除是扩散过程中固有的。驱动退火和移除临时衬垫319的示例结果在图3H中示出，其中块体鳍被指定为305'并且SiGe层被指定为307'以指示鳍303的这些区域中的扩散掺杂部分。
在一个实施方案中，在扩散之后，从鳍阵列移除SiO填充物材料317和固体源掺杂膜315。到此为止，掺杂剂已经被驱入块体硅鳍305'中。除非在掺杂剂膜315之上沉积另一衬垫，否则在任何后续热处理期间，块体鳍305硅表面上的任何残留掺杂膜在晶片上提供额外的掺杂剂源。因此，掺杂膜315可以留在鳍上的适当位置，以例如在源极/漏极尖峰退火期间提供另外的掺杂剂源。在图3的实施方案中，移除掺杂剂膜，并且接着随后将它从鳍表面清洁掉。对于仅需要驱动退火来将掺杂剂驱入块体硅鳍305'中的情况，可以移除掺杂剂源膜315。对于通过驱动退火和源极/漏极尖峰退火过程来设置到块体鳍305'中的扩散的情况，掺杂膜可以保留在块体硅鳍305'之上。如果在移除掺杂源时正在执行任何凹陷，则所述过程也可以在需要时移除屏蔽氧化物313。示例结果在图3I中示出。
在使掺杂材料扩散到鳍中之后，提供隔离材料以至少覆盖层状鳍结构的扩散掺杂部分，如图1中的步骤107所见。在该步骤中，衬垫可以沉积在块体硅鳍305'之上，以便在STI氧化物沉积到鳍阵列中之后防止磷或砷在源极/漏极尖峰退火期间从块体鳍305'到STI氧化物中的任何扩散，如图3J中所见。SiN衬垫321可以通过原子层沉积或CVD沉积以覆盖鳍303，但随后将在STI凹陷蚀刻过程期间凹陷在硅线309的高度之下。
在形成STI隔离时，STI氧化物323沉积在膜321和鳍阵列(在衬底上)内的扩散掺杂部分上方。然后将STI氧化物323向下抛光(移除)到鳍303之上的SiN盖311，如图3K中所示。在抛光之后，然后使STI氧化物323向下凹陷到所需高度。优选地，STI氧化物323将至少覆盖由扩散步骤105引起的鳍303的扩散掺杂部分。在一些实施方案中，STI氧化物323的底部仍将具有SiN扩散衬垫321，SiN扩散衬垫321将掺杂的块体硅301和掺杂的残余鳍305中的每一者与STI氧化物323分隔开。此外，在一些实施方案中，仅从将用于实际纳米线的SiGe和Si的部分中移除SiN衬垫321。因此，SiN衬垫321也从Si/SiGe鳍303的在STI氧化物323的高度上方的表面移除。这可以在STI凹陷期间通过各向同性蚀刻来完成，在STI凹陷中可以将选择性调节为1:1的选择性，使得在单个过程步骤中移除所述层。或者，可以使用两步蚀刻过程，其中STI氧化物323向下凹陷到期望高度，并且接着通过气相蚀刻(化学氧化物移除)或者通过原子层蚀刻来蚀刻Si/SiGe鳍303上暴露的SiN衬垫321，以显露STI氧化物323上方的Si/SiGe鳍。SiN衬垫321保留在块体硅鳍305'上，并且可以在某种程度上保留在块体硅鳍305'上方，如图3L中所见。衬垫321的存在用于防止磷或硼掺杂剂在后续热处理(诸如源极/漏极尖峰退火)期间从硅到STI氧化物321中的任何扩散。
在STI氧化物凹陷之后，鳍303由另一衬垫材料保护，所述衬垫材料在替换栅极(多晶硅)清除过程期间提供对硅和硅锗鳍的某一选择性。如图3M中所见，衬垫325设置在STI氧化物323和鳍303的上部上。衬垫325有助于确保鳍303以及随后的纳米线307在替换栅极开口蚀刻过程期间不被损坏。图3M中的结构的处理继续释放纳米线，从而形成源极/漏极区和栅极结构，如图2所示。
因此，所公开发明的实施方案提供固体源掺杂工艺，以将块体鳍与GAA纳米线装置中的栅极结构电隔离。已经对鳍式FET结构实施了这种固体源扩散/掺杂工艺，其中包含在STI氧化物内的鳍被掺杂并且使将与栅极接触的鳍区域与起始硅(通常用硼进行p掺杂)保持一致。鉴于鳍工艺的小间距(当考虑鳍间距向下延伸到22nm的总间距-或-在8nm鳍之间的约14nm的间隔时具有不足的空间的膜沉积太多)，这种用于鳍式FET应用的工艺已经转变为植入型应用。
利用本文中的技术，纳米线鳍结构的基底被掺杂以有效地防止电荷从一个带电栅极到相邻栅极的任何转移，这是由于功函数金属在块体鳍之上而将鳍留在不可易于移除或者由电介质埋藏的金属栅极下方。因此，本文中的技术扩展了固体源掺杂以对包含在STI氧化物内的硅鳍结构，而不一定是硅纳米线本身掺杂。因此，本文中的技术在中和块体硅时维持常规p掺杂水平。在前面的描述中，已经阐述了具体细节，诸如处理系统的特定几何形状以及其中使用的各种部件和过程的描述。然而，应理解，本文中的技术可以在脱离这些具体细节的其他实施方案中实践，并且这些细节是出于解释而非限制的目的。已经参考附图描述了本文中公开的实施方案。类似地，出于解释的目的，已经阐述了具体数量、材料和配置以便提供透彻理解。然而，可以在没有这些具体细节的情况下实践实施方案。具有基本相同的功能构造的部件由相同的附图标记表示，并且因此可以省略任何冗余的描述。
已经将各种技术描述为多个离散操作以帮助理解各种实施方案。描述的顺序不应被解释为暗示这些操作必须依赖于顺序。实际上，这些操作无需以呈现的顺序执行。所描述的操作可以以与所描述的实施方案不同的顺序执行。在额外实施方案中，可以执行各种额外操作和/或可以省略所描述的操作。
如本文中所使用的“衬底”或“目标衬底”通常是指根据本发明处理的物体。衬底可以包括装置，具体地说是半导体或其他电子装置的任何材料部分或结构，并且可以是例如基础衬底结构，诸如半导体晶片、光罩或在基础衬底结构上或覆盖基础衬底结构的层，诸如薄膜。因此，衬底不限于任何特定的基础结构、下层或覆盖层、图案化或未图案化的，而是预期包括任何这样的层或基础结构，以及层和/或基础结构的任何组合。所述描述可以参考特定类型的衬底，但是这仅用于说明性目的。
本领域技术人员还将理解，可以对上文解释的技术的操作进行许多变化，同时仍然实现本发明的相同目标。这些变化旨在由本公开的范围所涵盖。因此，本发明的实施方案的前述描述不旨在是限制性的。而是，在所附权利要求书中呈现对本发明的实施方案的任何限制。

Claims (20)

1.一种制造半导体装置的方法，所述方法包括：
提供在其上具有层状鳍结构的衬底，所述层状鳍结构包括基底鳍部分、设置在所述基底鳍部分上的牺牲部分和设置在所述牺牲部分上的沟道部分；
在所述衬底上在所述层状鳍结构上方提供掺杂源膜；
使掺杂材料从所述掺杂源膜扩散到所述层状鳍结构的除所述沟道部分之外的一部分中，以在所述层状鳍结构中形成扩散掺杂区；以及
在所述衬底上在所述层状鳍结构的至少所述扩散掺杂区上方提供隔离材料。
2.如权利要求1所述的方法，其中所述提供衬底包括：
将所述基底鳍提供为由经掺杂Si的块体形成的块体鳍；以及
在所述块体鳍上提供多层鳍结构，其中所述多层鳍结构包括将所述牺牲部分提供为与形成所述沟道部分的多个Si层交替的多个SiGe层。
3.如权利要求2所述的方法，其中所述多个Si层中的每一者形成纳米线或纳米板。
4.如权利要求2所述的方法，其中所述提供掺杂源膜包括仅在所述层状鳍结构的一部分上方提供所述掺杂源膜，所述掺杂源膜的位置被选择以防止所述掺杂材料扩散到所述沟道部分中。
5.如权利要求4所述的方法，其中选择所述掺杂源膜的所述位置以至少覆盖所述层状鳍结构的所述基底鳍部分的一部分。
6.如权利要求5所述的方法，其中选择所述掺杂源膜的所述位置以覆盖所述层状鳍结构的所述基底鳍部分。
7.如权利要求6所述的方法，其中选择所述掺杂源膜的所述位置以覆盖所述层状鳍结构的所述牺牲部分的一部分。
8.如权利要求1所述的方法，其中所述扩散包括执行驱动退火加热以使所述掺杂材料扩散到所述层状鳍结构中。
9.如权利要求8所述的方法，其中所述扩散还包括执行源极/漏极尖峰退火加热以使所述掺杂材料扩散到所述层状鳍结构中。
10.如权利要求8所述的方法，其中所述扩散还包括调节所述驱动退火的时间和温度中的至少一者，以防止所述掺杂材料扩散到所述层状鳍结构的所述沟道部分中。
11.如权利要求1所述的方法，其中所述提供隔离材料包括在所述衬底上形成浅沟槽隔离层以至少覆盖所述层状鳍结构的所述扩散掺杂区。
12.如权利要求1所述的方法，所述方法还包括在所述层状鳍结构上方提供屏蔽层，所述掺杂源层设置在所述屏蔽层上。
13.如权利要求1所述的方法，所述方法还包括在所述扩散之前在所述掺杂源层上方提供衬垫。
14.一种半导体装置，所述半导体装置包括：
衬底；
鳍结构，所述鳍结构设置在所述衬底上，所述鳍结构包括：
半导体材料的基底鳍部分，所述基底鳍部分包括扩散掺杂区，以及
半导体材料的沟道部分，所述沟道部分设置在所述基底鳍部分上并与所述基底鳍部分竖直地间隔开；
栅极结构，所述栅极结构布置在所述基底鳍部分与所述沟道部分之间并且包括导电材料，其中扩散掺杂区被配置为将所述基底鳍部分与所述栅极结构电隔离；以及
隔离结构，所述隔离结构形成在所述衬底上并且至少覆盖所述扩散掺杂区。
15.如权利要求14所述的半导体装置，其中所述鳍结构包括：
块体鳍，所述块体鳍提供为所述基底鳍部分并由经掺杂半导体材料块体形成；以及
多个竖直堆叠的半导体层，所述半导体层提供为所述沟道部分，其中所述多个竖直堆叠的半导体层彼此间隔开并掺杂为与所述掺杂半导体材料相同的极性类型，其中所述扩散掺杂区具有与所述掺杂半导体材料相反的极性类型以提供所述块体鳍的反向掺杂。
16.如权利要求15所述的半导体装置，其中所述多个Si层中的每一者形成纳米线或纳米板。
17.如权利要求15所述的半导体装置，其中所述经掺杂半导体材料块体包括p型掺杂材料。
18.如权利要求16所述的半导体装置，其中所述多个竖直堆叠的半导体层各自包括p型掺杂材料。
19.如权利要求15所述的半导体装置，其中所述扩散掺杂区包括n型掺杂材料。
20.如权利要求19所述的半导体装置，其中所述n型掺杂材料包括磷或砷。
CN201780069522.9A 2016-11-14 2017-11-14 在纳米线和纳米板处理中防止块体硅电荷转移的方法 Active CN109952654B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662421522P 2016-11-14 2016-11-14
US62/421,522 2016-11-14
PCT/US2017/061550 WO2018090007A1 (en) 2016-11-14 2017-11-14 Method of preventing bulk silicon charge transfer for nanowire and nanoslab processing

Publications (2)

Publication Number Publication Date
CN109952654A true CN109952654A (zh) 2019-06-28
CN109952654B CN109952654B (zh) 2023-05-05

Family

ID=62108252

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201780069522.9A Active CN109952654B (zh) 2016-11-14 2017-11-14 在纳米线和纳米板处理中防止块体硅电荷转移的方法

Country Status (5)

Country Link
US (2) US10490630B2 (zh)
KR (1) KR102326463B1 (zh)
CN (1) CN109952654B (zh)
TW (1) TWI746696B (zh)
WO (1) WO2018090007A1 (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI746696B (zh) * 2016-11-14 2021-11-21 日商東京威力科創股份有限公司 奈米線及奈米平板處理用之本體矽電荷轉移之預防方法
KR102574454B1 (ko) 2016-12-16 2023-09-04 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US10269983B2 (en) * 2017-05-09 2019-04-23 Globalfoundries Inc. Stacked nanosheet field-effect transistor with air gap spacers
US10868127B2 (en) 2017-10-30 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Gate-all-around structure and manufacturing method for the same
US10643906B2 (en) * 2017-12-15 2020-05-05 Micron Technology, Inc. Methods of forming a transistor and methods of forming an array of memory cells
US10971630B2 (en) * 2019-04-24 2021-04-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure having both gate-all-around devices and planar devices
CN110189997B (zh) * 2019-04-28 2022-07-12 中国科学院微电子研究所 堆叠纳米片环栅晶体管及其制备方法
US11075266B2 (en) 2019-04-29 2021-07-27 International Business Machines Corporation Vertically stacked fin semiconductor devices
US11417781B2 (en) * 2020-03-25 2022-08-16 Intel Corporation Gate-all-around integrated circuit structures including varactors
WO2022094041A1 (en) * 2020-10-30 2022-05-05 Tokyo Electron Limited High precision 3d metal stacking for a plurality of 3d devices
US11315938B1 (en) 2020-12-18 2022-04-26 International Business Machines Corporation Stacked nanosheet rom
US20230088753A1 (en) * 2021-09-23 2023-03-23 Intel Corporation Gate-all-around integrated circuit structures having doped subfin

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080203491A1 (en) * 2007-02-28 2008-08-28 Anderson Brent A Radiation hardened finfet
CN102301480A (zh) * 2009-02-17 2011-12-28 国际商业机器公司 纳米线网格器件及其制备方法
US20130040447A1 (en) * 2010-04-15 2013-02-14 Shankar Swaminathan Conformal doping via plasma activated atomic layer deposition and conformal film deposition
US20150303284A1 (en) * 2014-04-16 2015-10-22 International Business Machines Corporation Punch through stopper in bulk finfet device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8753942B2 (en) 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
US9224810B2 (en) 2011-12-23 2015-12-29 Intel Corporation CMOS nanowire structure
US9012284B2 (en) 2011-12-23 2015-04-21 Intel Corporation Nanowire transistor devices and forming techniques
US8956942B2 (en) 2012-12-21 2015-02-17 Stmicroelectronics, Inc. Method of forming a fully substrate-isolated FinFET transistor
US9793403B2 (en) 2015-04-14 2017-10-17 Samsung Electronics Co., Ltd. Multi-layer fin field effect transistor devices and methods of forming the same
US10903210B2 (en) * 2015-05-05 2021-01-26 International Business Machines Corporation Sub-fin doped bulk fin field effect transistor (FinFET), Integrated Circuit (IC) and method of manufacture
US9953874B2 (en) * 2016-04-28 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods of forming FinFETs
US9728621B1 (en) * 2016-09-28 2017-08-08 International Business Machines Corporation iFinFET
TWI746696B (zh) * 2016-11-14 2021-11-21 日商東京威力科創股份有限公司 奈米線及奈米平板處理用之本體矽電荷轉移之預防方法
US10347742B2 (en) * 2016-11-14 2019-07-09 Tokyo Electron Limited Method of forming gate spacer for nanowire FET device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080203491A1 (en) * 2007-02-28 2008-08-28 Anderson Brent A Radiation hardened finfet
CN102301480A (zh) * 2009-02-17 2011-12-28 国际商业机器公司 纳米线网格器件及其制备方法
US20130040447A1 (en) * 2010-04-15 2013-02-14 Shankar Swaminathan Conformal doping via plasma activated atomic layer deposition and conformal film deposition
US20150303284A1 (en) * 2014-04-16 2015-10-22 International Business Machines Corporation Punch through stopper in bulk finfet device

Also Published As

Publication number Publication date
KR20190072622A (ko) 2019-06-25
CN109952654B (zh) 2023-05-05
US10665672B2 (en) 2020-05-26
TWI746696B (zh) 2021-11-21
US20180138268A1 (en) 2018-05-17
WO2018090007A1 (en) 2018-05-17
US20190140050A1 (en) 2019-05-09
TW201830693A (zh) 2018-08-16
KR102326463B1 (ko) 2021-11-12
US10490630B2 (en) 2019-11-26

Similar Documents

Publication Publication Date Title
CN109952654A (zh) 在纳米线和纳米板处理中防止块体硅电荷转移的方法
TWI788335B (zh) 全包覆式閘極結構及其製造方法
US10868179B2 (en) Fin-type field effect transistor structure and manufacturing method thereof
KR101833107B1 (ko) 스플릿 게이트 플래시 기술에서의 인터디지테이티드 커패시터
CN114068533A (zh) 半导体器件及其制造方法及包括该器件的电子设备
TW201719895A (zh) 製造堆疊奈米線電晶體之方法
CN108122845A (zh) 接触结构制造方法
US8927432B2 (en) Continuously scalable width and height semiconductor fins
TWI721468B (zh) 積體電路與用於形成積體電路的方法
TW201724218A (zh) 積體電路
US10164037B2 (en) Semiconductor device structure and method for forming the same
CN103456782B (zh) 半导体器件及其制造方法
US20190172949A1 (en) Fabricating method of fin structure with tensile stress and complementary finfet structure
US9263402B2 (en) Self-protected metal-oxide-semiconductor field-effect transistor
TW202228211A (zh) 具有介電芯的高效能浮體垂直場效電晶體
TW202226346A (zh) 具有先進cmos裝置佈局之複數高密度邏輯元件的製作方法
US9117926B2 (en) Semiconductor devices and methods for manufacturing the same
TW200414450A (en) Method for fabricating NROM memory cell field
KR102237433B1 (ko) 반도체 소자의 제조 방법
TW201539663A (zh) 半導體裝置及其形成方法
CN104681535B (zh) 半导体器件的接触件结构
CN109148607A (zh) 半导体装置、mos电容器及其制造方法
TWI578497B (zh) 具有改善字元線電阻與減少矽化物橋接之形成的製造方法
JP2011243727A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant