TW201830693A - 奈米線及奈米平板處理用之本體矽電荷轉移之預防方法 - Google Patents

奈米線及奈米平板處理用之本體矽電荷轉移之預防方法 Download PDF

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TW201830693A
TW201830693A TW106139283A TW106139283A TW201830693A TW 201830693 A TW201830693 A TW 201830693A TW 106139283 A TW106139283 A TW 106139283A TW 106139283 A TW106139283 A TW 106139283A TW 201830693 A TW201830693 A TW 201830693A
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doped
fin
semiconductor device
fin structure
layered
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TW106139283A
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TWI746696B (zh
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傑佛瑞 史密斯
安東 Ｊ 德維利耶
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日商東京威力科創股份有限公司
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Abstract

一種半導體裝置的製造方法，其步驟包含提供其上具有一分層鰭狀物結構的基板。該分層鰭狀物結構包含基底鰭狀物部分、設置於該基底鰭狀物部分上之犧牲部分、以及設置於該犧牲部分上之通道部分。於該基板之該分層鰭狀物結構上方設置一摻雜源膜，並將摻雜源材料從摻雜源膜擴散到分層鰭狀物結構中除了通道部分以外的一部分中，以在分層鰭狀物結構中形成擴散摻雜區域。於該基板上之該分層鰭狀物結構的至少該擴散摻雜區域上方提供一隔離材料。

Description

奈米線及奈米平板處理用之本體矽電荷轉移之預防方法
[相關申請案的交互參照] 本申請案係基於2016年11月14日所提申之美國臨時專利申請案第62/421,522號，並主張其優先權，其所有內容乃併入以供參照。
本發明揭露係關於一種例如積體電路、電晶體以及用於積體電路之電晶體元件之半導體裝置的製造方法。
在半導體裝置（尤其是微觀尺寸時）的製造過程中，會執行各種不同的製程，例如成膜沉積、蝕刻光罩的產生、圖案化、材料蝕刻及移除、以及摻雜處理。這些製程處理乃重複地執行，直到在基板上形成所需的半導體裝置元件。在歷史上來說，使用微製程，電晶體一直是在平面上產生，且在使用中的裝置平面上方形成配線/金屬化，因此其特徵在於二維（2D）電路或2D製造。尺寸的不斷縮放乃大幅增加了2D電路中每單位面積的電晶體數量，然而隨著尺寸進入到單一位元奈米半導體裝置製造節點，縮放尺寸便面臨越來越大的挑戰。半導體裝置製造者也表達了對在三維（3D）半導體電路中將電晶體堆疊於彼此上方的興趣。
對於提供改良之高性能半導體裝置的縮放比例以及對相應之製造處理製程的需要仍持續有其需求。
本揭露內容的一個目的是提供改善電性能和可靠度的3D半導體裝置和方法。這些和其他目的由本揭露之實施例所提供，包含以下編號之本發明的例示性態樣。
(1)一種半導體裝置的製造方法，其步驟包含提供其上具有一分層鰭狀物結構的一基板，該分層鰭狀物結構包含一基底鰭狀物部分、設置於該基底鰭狀物部分上的一犧牲部分以及設置於該犧牲部分上的一通道部分。於該基板之該分層鰭狀物結構上方設置一摻雜源膜，並自該摻雜源膜將摻雜材料擴散至該分層鰭狀物結構上之該通道部分以外的一部份，以在該分層鰭狀物結構中形成一擴散摻雜區域。於該基板上設置一隔離材料而位於該分層鰭狀物結構之至少該擴散摻雜區域上方。
(2)根據態樣(1)之方法，其中提供該基板之步驟包含提供作為一鰭本體的該基底鰭狀物，該鰭本體係形成自一摻雜矽塊。於該鰭本體上設置一多層鰭狀物結構，其中該多層鰭狀物結構包含提供以複數SiGe層形成之該犧牲部分，其與形成該通道部分之複數Si層交替形成。
(3)根據態樣(2)之方法，其中該複數Si層中的每一個均形成一奈米線或奈米平板。
(4)根據態樣(2)之方法，其中設置該摻雜源膜之步驟包含將該摻雜源膜僅設置在該分層鰭狀物結構的一部份上方，該摻雜源膜的位置係經選擇以預防摻雜材料擴散至通道部分。
(5)根據態樣4之方法，其中該摻雜源膜的位置係經選擇以至少覆蓋該分層鰭狀物結構之部分的基底鰭狀物部分。
(6)根據態樣5之方法，其中該摻雜源膜的位置係經選擇以覆蓋該分層鰭狀物結構之該基底鰭狀物部分。
(7)根據態樣6之方法，其中該摻雜源膜的位置係經選擇以覆蓋該分層鰭狀物結構之該犧牲部分的一部份。
(8)根據態樣1之方法，其中該擴散步驟包含執行一驅動退火加熱，以將該摻雜材料擴散至該分層鰭狀物結構中。
(9)根據態樣8之方法，其中該擴散步驟更包含執行源極/汲極尖峰式退火加熱，以將該摻雜材料擴散至該分層鰭狀物結構中。
(10)根據態樣8之方法，其中該擴散步驟更包含調節該驅動退火的時間及溫度至少其中之一，以防止該摻雜材料擴散至該分層鰭狀物結構之該通道部分中。
(11)根據態樣1之方法，其中設置該隔離材料的步驟更包含於該基板上形成一淺溝槽隔離層，以覆蓋該分層鰭狀物結構之該擴散摻雜區域。
(12)根據態樣1之方法，其步驟更包含在該分層鰭狀物結構上方設置一屏蔽層，該摻雜源膜係設置於該屏蔽層上。
(13)根據態樣1之方法，其步驟更包含在該擴散步驟之前於該摻雜源膜上方設置一襯墊。
(14)本發明之另一態樣包含一種半導體裝置，其包含一基板以及位於該基板上之一鰭狀物結構。該鰭狀物結構包含一半導體材料之基底鰭狀物部分，該基底鰭狀物部分包含一擴散摻雜區域；以及一半導體材料之通道部分，其設置於該基底鰭狀物部分上並與該基底鰭狀物部分垂直分開。一閘極結構，設置於該基底鰭狀物部分與該通道部分之間，其包含一導電材料，其中該擴散摻雜區域係用以將該基底鰭狀物部分與該閘極結構電性隔離。一隔離結構形成於該基板上，且覆蓋至少該擴散摻雜區域。
(15)根據態樣14之該半導體裝置，其中該鰭狀物結構包含設置作為該基底鰭狀物部分的一鰭本體，其由摻雜半導體材料塊形成；設置作為該通道部分之複數個垂直堆疊之半導體層。該複數個垂直堆疊之半導體層彼此隔開，且係摻雜成與該摻雜半導體材料相同之極性類型。該擴散摻雜區域具有與該摻雜半導體材料相反的極性類型，以提供該鰭本體之逆摻雜。
(16)根據態樣15之該半導體裝置，其中該複數個垂直堆疊之半導體層中的每一個均形成一奈米線或奈米平板。
(17)根據態樣15之該半導體裝置，其中該摻雜半導體材料塊包含p-型摻雜材料。
(18)根據態樣16之該半導體裝置，其中該複數個垂直堆疊之半導體層包含p-型摻雜材料。
(19)根據態樣15之該半導體裝置，其中該擴散摻雜區域包含n-型摻雜材料。
(20)根據態樣19之該半導體裝置，其中該n-型摻雜材料包含磷或砷。
本文技術涉及使用在奈米線FET（場效電晶體）中納入奈米線（或奈米平板或奈米片）或通過堆疊的互補式FET裝置的全閘極處理的裝置製造。 GAA（Gate-all-around）技術標識出一種FET裝置，其中金屬閘極乃實體包覆在矽或矽/鍺線周圍，是三閘極製程的進一步延伸，三閘極製程中其閘極係包覆在矽或矽/鍺鰭周圍。對於鰭式場效電晶體，閘極乃環繞四面中的三面，而對於GAA FET裝置，閘極係環繞於給定通道的所有部分（無論給定通道具有矩形截面或是圓形截面）。GAA FET裝置的其中一種類型是奈米線FET。
圖4顯示出沿著奈米線本身方向之GAA奈米線結構的透視圖。如所見，該裝置包含基板401，於其上具有一堆疊奈米線結構403陣列。每一堆疊結構403均包含一鰭本體部分405，其具有奈米線裝置410以及設置在奈米線裝置410上的閘極結構420。鰭本體部分405為中間鰭狀物結構的一部分，該中間鰭狀物結構係經處理以形成奈米線裝置410和閘極結構420。每一奈米線裝置410均包含一奈米線通道區域411，並在奈米線通道區域411之兩相對側上具有源極/汲極區413。每一閘極結構420均為圍繞奈米線通道區域411的多層結構，其包含高k層421、功函數金屬層423以及閘極金屬填充物425。在每一鰭狀物403上提供一蓋407，而閘極間隔件427將閘極結構420與設置在相鄰之堆疊奈米線結構403之間的源極/汲極金屬429電絕緣。於鰭狀物結構403之間設置淺溝槽隔離結構431。
在GAA裝置中，閘極金屬425透過閘極接點（未顯示）充電，且該電荷在穿過奈米線、奈米片或奈米平板411之前係先被攜帶通過功函數金屬423。透過結合介電閘極間隔件427，吾人係期望至個別閘極的電荷係包含在該選定的閘極內而不在相鄰的源極/汲極條狀區429內。然而，對於奈米線或奈米平板的設計而言，只要該等線路係由矽及矽鍺組成（例如）的多層鰭狀物之中間製程所形成，在金屬閘極結構的底部或基底便會存在鰭狀物的殘留物。來自該鰭狀物405的矽將類似地沉積例如HfO的高k薄膜421以及沉積在其上方之例如TiN的功函數金屬423。在使特定閘極充電期間，此結果可能潛在地使埋入的鰭狀物也被充電，而由殘留之鰭狀物結構所攜帶的電荷便帶至相鄰的閘極結構，從而導致電性能問題及/或裝置故障。從圖4可以看出，對特定閘極的任何電荷都可以通過功函數金屬423轉移到矽鰭本體，然後轉移到相鄰的閘極。
根據本文的發現，放置在金屬閘極下方的矽鰭本體係與金屬閘極結構隔離。實現此一目標的一種技術包含逆摻雜矽塊以中和鰭狀物並防止其在特定金屬閘極充電期間被充電。逆摻雜並不會影響放置在矽鰭本體正上方的實際奈米線或奈米片，因此與習知之注入製程相反，此摻雜製程係受益於固態源摻雜法。另一種技術包含一種方法，其中使該矽鰭本體進一步充分地凹陷至金屬閘極之下，並在該矽鰭本體上沉積額外的介電層。該凹陷技術從製程整合方法實施可能更困難，因為一旦矽線釋放處理完成之後，介電材料便需直接沉積到開啟的替換閘極中。且，材料需要在開啟的替代閘極內各向同性地凹入以填充閘極的底部，同時確保該等線路沒有殘留介電沉積，且該閘極底部所沉積的厚度足以防止電荷轉移到矽鰭本體。本文描述的技術將集中於透過固態源摻雜製程來中和矽鰭本體的實施例。此處之此種製程可用於將磷或砷摻入已用硼預先摻雜的矽鰭中。透過製程整合流程可以控制處理，而不直接在矽或矽鍺奈米線或奈米片上進行摻雜。
此處之技術包含整合和硬體方法以將鰭本體部分405與3D半導體裝置之閘極部分隔離。圖1為一例示性製程的流程圖，說明根據本文實施例之形成一具有隔離鰭本體部分之半導體裝置。該製程始於提供一具有包含通道部分之分層鰭狀物結構的基板，如步驟101所示。在步驟103中，於該分層鰭狀物結構上提供一摻雜膜。在步驟105中，摻雜材料係從該摻雜膜擴散，以在分層鰭狀物結構之除了通道部分以外形成一擴散摻雜部分。在步驟107中，於該分層鰭狀物結構之至少擴散摻雜部分上方提供隔離材料。
圖2顯示一橫剖面透視圖，說明根據本揭露內容之實施例中具有一隔離鰭本體部分的多通道FET裝置。圖2顯示出沿著奈米線本身方向的GAA奈米線結構。類似於圖4，該裝置包含基板201，其上具有一堆疊奈米線結構203陣列。每一堆疊結構203包含一鰭本體部分205，其具有奈米線裝置210以及設置於其上的閘極結構220。鰭本體205包含擴散摻雜鰭狀物區域209，而將鰭本體205與閘極金屬隔離。每一奈米線裝置210均包含一奈米線通道區域211，並在奈米線通道區域211之兩相對側上具有源極/汲極區213，且每一閘極結構220均包含高k層221、功函數金屬層223以及閘極金屬填充物225。每一鰭狀物203上方均提供一蓋207，而閘極間隔件227將閘極結構220與設置在相鄰之堆疊奈米線結構203之間的源極/汲極金屬229電隔離。於鰭狀物結構203之間設置淺溝槽隔離結構231。
圖3A-3M顯示用於製造具有圖2所示結構之特定裝置的製程範例中各個階段的結構。將參考圖3A-3M更詳細地說明圖1。如熟悉本技藝者所知，奈米線或奈米片可以由例如Si和SiGe的交替半導體材料的「鰭狀」結構所形成。矽奈米線的形成可以先透過對鰭狀物中的SiGe進行各向同性蝕刻以及完成於在閘極結構任一端上的矽線末端處形成閘極間隔件材料來實現。類似地，可以透過相對於SiGe而選擇性蝕刻鰭狀物中的Si來形成SiGe奈米線。本文的技術適用於Si和SiGe兩者之奈米線或奈米片或奈米平板，以及其他類似的半導體結構。為了便於解釋本文的實施例， 圖1和3A-3M說明製造矽奈米線的製程。因此，圖1和3A-3M揭露了將鰭本體隔絕於半導體裝置之閘極結構的整合和硬體方法。
回到圖1，方法100可以從例如圖3A所示之結構範例的半導體結構開始。該結構在裝置處理的中間階段顯示一多層鰭狀物陣列。該結構包含其上具有鰭狀物303陣列的基板301。每一鰭狀物303包含鰭本體305、作為犧牲部分的SiGe層307以及作為通道部分的Si奈米線309。SiGe 307稍後將在製程中移除以釋放奈米線309。在結構300A中，該包含奈米線309的鰭結構係由一蓋層311所保護。
選擇性地，吾人可透過原子層沉積來沉積例如SiO的屏蔽層313以在鰭狀物303上方形成一間隔件。該膜的結合為選擇性地，且其係用以在下面討論的驅動退火步驟期間控制磷或砷擴散到鰭狀物中。圖3B顯示一屏蔽層313範例。
在圖1的步驟103中，於該分層鰭狀物結構上設置一摻雜膜。該摻雜源膜係用以將摻雜材料擴散到分層鰭狀物結構的部分中。在一些實施例中，摻雜源膜係設置在分層鰭狀物結構的一部分上方，以將摻雜劑擴散到分層鰭狀物結構的對應部分中。然而，也可使用一阻障襯墊來控制從摻雜源層擴散到鰭狀物之選定部分。在圖3的實施例中，如圖3C所示，摻雜源膜315最初係設置在屏蔽層313上方而遍佈整個鰭狀物結構303。摻雜源膜315可以透過CVD或ALD而沉積到該鰭狀物結構上。出於實用的目的，如果所使用的矽塊為p-型，其中矽已經是硼摻雜的，則摻雜源材料可以由例如磷或砷（例如PSG或AsSG）的n-型材料所組成。
移除部分摻雜源層315的步驟開始於在基板（多層鰭狀物陣列）上沉積一填充材料，例如可流動SiO膜或旋塗有機膜。此種填充材料的沉積會導致材料的過載。圖 3D為一例示圖，描繪使用可流動的SiO填充材料317進入鰭狀物陣列的結果。接著，如圖3E所示，將過載的填充材料317進行拋光，直到作為頂部表面材料之氮化物蓋311（設置在鰭狀物303頂部）露出為止。
一旦填充材料317係相對於鰭狀物陣列的頂部而被平面化，該填充材料的任何後續凹陷更加可控。例如，SiO填充物317可以與固態源摻雜膜315及屏蔽層313一起凹入到下部奈米線309（或奈米平板）和剩餘矽鰭本體305之間的水平，如圖3F所示。這種凹陷端點可以用於包括形成裝置的製造流程，其中矽線307將用於整個NMOS和PMOS兩閘極或用於3D邏輯應用的共用閘極。在併入SiGe線的應用中，凹陷的位置可以斷開。
可以以各種方式執行摻雜膜315和填充物317的凹陷。較佳地，SiO填充物以1：1的選擇性對摻雜膜315各向同性地凹陷，俾使這些層在單一處理步驟中被移除。或者，使SiO填充物317各向同性地凹陷，而讓摻雜膜315遍及整個鰭狀物303，接著可以使用後續的各向同性蝕刻或甚至原子層蝕刻（ALE）製程來將暴露的摻雜源膜315從SiO填充材料317已經凹陷的鰭狀物中清除。隨後可以執行後續的清潔步驟，以確保所有摻雜材料從鰭狀物中的矽線清除。
凹入的SiO填充物317及摻雜膜315的位置可經設定，以確保摻雜材料不會擴散穿過SiGe層307而進入Si奈米線309。充分地使摻雜膜凹陷是有利的，因為必須遠離通過SiGe的任何摻雜擴散，以避免摻雜了最底層的矽線或平板。在圖3F中，該凹陷乃顯示出僅向下至矽鰭本體305與最下方的矽線309之間的水平，但是在其他實施例中，該凹陷的量可以選擇性地向下延伸至矽鰭本體305之最頂部表面下方。給定的凹陷深度可分別取決於所使用的摻雜物種以及該摻雜物種在矽和矽鍺內的擴散而定。
在一實施例中，一例如SiN或BN的選擇性襯墊材料可在擴散步驟之前透過原子層沉積來沉積，如圖3G 所示。此襯墊膜319可用於防止驅動退火過程中磷或砷摻雜物質的任何向外擴散。
回到圖1，在步驟105中，摻雜材料係自該摻雜膜擴散，以在分層鰭狀物結構之通道部分以外形成一擴散摻雜部分。也就是說，在圖3A-3M之堆疊奈米線結構中，摻雜劑乃擴散到鰭狀物303，包括至少奈米線309。
摻雜材料的擴散可以透過專用的驅動退火處理來提供，或是透過隨後的s / d尖峰退火來提供進一步的擴散。在圖3A-3M 的例子中，執行驅動退火步驟以將摻雜物種（例如磷或砷）擴散到矽鰭本體305但不擴散至矽奈米線或奈米片309。在某些情況下，擴散到最下方矽奈米線309以及矽鰭本體305頂部之間的SiGe 307是可接受的。例如，在源極/汲極尖峰退火期間進一步的擴散可能是最小的，並且因此不足以擴散到矽奈米線309中。在矽奈米線釋放步驟期間，SiGe 307中的任何摻雜材料都會出來。而且，可以調整驅動退火處理（時間及/或溫度），使得磷或砷摻雜劑的總擴散長度可透過驅動及尖峰退火的組合來設定。
對於在驅動退火製程期間使用例如SiN或BN的臨時襯墊材料的實施例，該襯墊乃接著被移除。當使用BN時，薄膜性質使得材料在驅動退火步驟期間可以脫落，故而在擴散處理中該臨時襯墊的移除是固有的。在圖3H中顯示出驅動退火以及移除臨時襯墊319的例示性結果，其中該鰭本體被指定為305'而SiGe層被指定為307'，以指出鰭狀物303的這些區域中的擴散摻雜部分。
在一實施例中，SiO填充材料317和固態源摻雜膜315在擴散步驟之後自該鰭狀物陣列移除。到此一時點，摻雜劑已經被驅動到矽鰭本體305'中。除非在摻雜劑膜315上方沉積另一襯墊，否則在任何後續熱處理期間，鰭本體305矽表面上的任何殘留摻雜膜會提供晶圓上的額外摻雜劑源。因此，摻雜膜315便可留在鰭狀物上以例如在源極/汲極尖峰退火期間提供另外的摻雜劑源。在圖3的實施例中，該摻雜劑膜被移除並接著自該鰭狀物表面清除。對於僅需要驅動退火來將摻雜劑驅入矽鰭本體305'的情況，可移除摻雜劑源膜315。對於透過驅動退火和源極/汲極尖峰退火製程來設定擴散到鰭本體305'中的情況，該摻雜膜可以維持在矽鰭本體305'的上方。如果在移除摻雜源時正在執行任何凹陷，則需要的話該處理也可以移除屏蔽層313。圖3I顯示了一個例示結果。
在摻雜材料擴散到鰭狀物中之後，便提供一隔離材料以覆蓋至少該分層鰭狀物結構之擴散摻雜部分，如圖1中的步驟107所示。在該步驟中，在STI氧化物沉積至該鰭狀物陣列之後的源極/汲極尖峰退火期間，為了防止磷或砷從鰭本體305'擴散到STI氧化物中，可以沉積一襯墊在矽鰭本體305'的上方，如圖3J所示。可以利用原子層沉積或CVD來沉積SiN襯墊321，以覆蓋鰭狀物303，但該襯墊隨後將在STI凹陷蝕刻處理期間被凹下至低於矽線309的高度。
在形成STI隔離時，STI氧化物323係沉積在薄膜321和鰭狀物陣列內（基板上）的擴散摻雜部分上方。接著將STI氧化物323向下拋光（移除）到鰭狀物303頂部的SiN蓋311，如圖3K所示。在拋光處理之後，STI氧化物323接著向下凹陷到期望的高度。較佳地，STI氧化物323將覆蓋至少由擴散步驟105引起的鰭狀物303的擴散摻雜部分。在某些實施例中，STI氧化物323的底部仍具有SiN擴散襯墊321，其將每個摻雜的、矽塊301以及摻雜殘留物鰭狀物305與STI氧化物323隔開。此外，在某實施例中，僅移除會用於實際奈米線中的SiGe和Si部分的SiN襯墊321。因此，SiN襯墊321也從高於STI氧化物323高度的Si / SiGe鰭狀物303的表面移除。此處理可以透過在STI凹陷期間的各向同性蝕刻來完成，其中選擇性可以調節為1:1選擇性，使得在單一處理步驟中便可移除層。或者，可以使用兩步驟之蝕刻處理，其中將STI氧化物323向下凹陷到所需高度，然後透過氣相蝕刻（化學氧化物去除）或原子層蝕刻，蝕刻暴露在Si / SiGe鰭狀物303上的SiN襯墊321，以顯現出STI氧化物323上方的Si / SiGe鰭狀物。SiN襯墊321係保留在矽鰭本體305'上，並且可以在某種程度上保留在矽鰭本體305'上方，如圖3L所見。襯墊321的存在用於在隨後的熱處理（例如源極/汲極尖峰退火）期間防止磷或硼摻雜劑從矽到STI氧化物323中的任何擴散。
在STI氧化物凹陷之後，鰭狀物303便被另一襯墊材料所保護，該襯墊材料在替代閘極（多晶矽）清除處理期間提供對矽和矽鍺鰭狀物的一些選擇性。如圖3M所示，襯墊325係設置在STI氧化物323以及鰭狀物303的上部份上。襯墊325有助於確保鰭狀物303以及後續的奈米線309於替代閘極開口蝕刻製程期間不被損壞。圖3M中之結構的處理繼續釋放奈米線、形成如圖2所示的源極/汲極區域以及閘極結構。
因此，本揭露發明之實施例提供一固態源摻雜製程，以在GAA奈米線裝置中將鰭本體與閘極結構電隔離。這種固態源擴散/摻雜製程已用於FINFET結構，其中包含在STI氧化物內的鰭狀物被摻雜，而閘極要接觸的鰭狀物區域則維持與起始的矽（典型上以硼做p-摻雜）一致 。考慮到鰭狀物製程的間距小（考慮到鰭狀物間距已延伸下至總間距22nm或在8nm鰭狀物之間約14nm的間距時，太多的薄膜需沉積而空間卻不足），用於FINFET應用的這些製程已轉變為植入類型的應用。
利用本文之技術，奈米線鰭狀物結構的基底被加以摻雜，以有效地防止由於鰭本體上方之功函數金屬以及金屬閘極下方之的殘餘鰭狀物而導致電荷從一個帶電閘極到相鄰閘極的任何轉移，此並不容易被移除或者被介電質掩埋。因此，本文的技術延伸至固態源摻雜，以摻雜包含在STI氧化物內的矽鰭狀物結構，而不一定是矽奈米線本身。 因此，本文的技術不僅維持習知之p型-摻雜水平，同時中和矽塊。在前面的描述中，已設定了具體細節，例如處理系統的特定幾何形狀以及其中使用的各種元件及處理的描述。然而，吾人應理解，本文中的技術可以偏離這些具體細節而在其他實施例中實施，且這些細節是為了解釋而非限制的目的。此處所揭露之實施例係參考附圖而說明。類似地，為了解釋的目的，此處設定了具體的數字、材料以及和配置以便提供透徹的理解。儘管如此，吾人仍可在沒有這些具體細節的情況下實踐實施例。具有基本相同的功能結構的元件係由相似的附圖標記表示，並因此可以省略任何冗餘的描述。
本文係將各種技術以多個個別操作來加以描述，以幫助理解各種實施例。描述的順序不應被解釋為暗示這些操作必須取決於順序。事實上，這些操作不需要按照說明的順序進行。所描述的操作可以與該實施例不同的順序來執行。在額外的實施例中可以執行各種額外的操作以及/或可以省略所描述的操作。
本文中所使用之「基板」或「目標基板」一般是指依據本發明而受處理的物體。基板可包含裝置(特別是半導體或其他電子裝置)的任何材料部分或結構，且可例如是基礎基板結構，如半導體晶圓、倍縮遮罩、或基礎基板結構上或覆蓋該基礎基板結構的覆層(如薄膜)。因此，基板不受限於任何特定的基礎結構、下方層或上方層、圖案化或非圖案化，反而基板被認為包含任何的如此之覆層或基礎結構、以及覆層及/或基礎結構的任何組合。本描述內容可能參照特定類型的基板，但其僅為說明性的目的。
熟習該領域技術者亦將理解，針對以上所解釋之技術的操作可作出諸多不同變化，而仍達成本發明之同樣的目標。如此之變化意在涵蓋於本揭露內容的範疇中。因此，本發明之實施例的前述內容並不意圖為限制性。反而，對於本發明之實施例的任何限制係呈現於以下申請專利範圍中。
100‧‧‧方法
101、103、105、107‧‧‧步驟
201、301、401‧‧‧基板
203‧‧‧堆疊奈米線結構
205、405‧‧‧鰭本體部分
207、407‧‧‧蓋
209‧‧‧擴散摻雜鰭狀物區域
210、410‧‧‧奈米線裝置
211、411‧‧‧奈米線通道區域
213、413‧‧‧源極/汲極區
220、420‧‧‧閘極結構
221、421‧‧‧高k層
223、423‧‧‧功函數金屬層
225、425‧‧‧閘極金屬填充物
227、427‧‧‧閘極間隔件
229、429‧‧‧源極/汲極金屬
231、431‧‧‧淺溝槽隔離結構
303‧‧‧鰭狀物
305、305’‧‧‧矽鰭本體、鰭本體
307、307’‧‧‧SiGe層
309‧‧‧奈米線
311‧‧‧蓋層
313‧‧‧屏蔽層
315‧‧‧摻雜源膜、摻雜劑膜、摻雜劑源膜
317‧‧‧填充材料、填充物
319‧‧‧襯墊
321‧‧‧襯墊、薄膜
323‧‧‧STI氧化物
325‧‧‧襯墊
403‧‧‧堆疊奈米線結構
結合在說明書中並構成說明書的一部分的附圖說明了一或多個實施例，並且與說明書一起解釋了這些實施例。所附圖示不一定按比例繪製。附圖中所示的任何數值尺寸僅用於說明之目的，並且可能或可能不代表實際或較佳值或尺寸。在適用的情況下，可能沒有說明某些或所有功能，以幫助描述下述特徵。在所附圖示中：
圖1為一流程圖，說明根據本揭露內容之某些態樣中，形成具有鰭本體隔離部之半導體裝置的製造過程；
圖2是一橫剖面透視圖，說明根據本揭露內容之某些態樣中之具有鰭本體隔離部之半導體裝置；
圖3A為一橫剖面透視圖，說明根據本揭露內容的某些態樣中用以製造圖2之裝置的起始結構範例；
圖3B為一橫剖面透視圖，說明根據本揭露內容的某些態樣中在製造圖2裝置過程中之中間結構範例；
圖3C為一橫剖面透視圖，說明根據本揭露內容的某些態樣中在製造圖2裝置過程中之中間結構範例；
圖3D為一橫剖面透視圖，說明根據本揭露內容的某些態樣中在製造圖2裝置過程中之中間結構範例；
圖3E為一橫剖面透視圖，說明根據本揭露內容的某些態樣中在製造圖2裝置過程中之中間結構範例；
圖3F為一橫剖面透視圖，說明根據本揭露內容的某些態樣中在製造圖2裝置過程中之中間結構範例；
圖3G為一橫剖面透視圖，說明根據本揭露內容的某些態樣中在製造圖2裝置過程中之中間結構範例；
圖3H為一橫剖面透視圖，說明根據本揭露內容的某些態樣中在製造圖2裝置過程中之中間結構範例；
圖3I為一橫剖面透視圖，說明根據本揭露內容的某些態樣中在製造圖2裝置過程中之中間結構範例；
圖3J一橫剖面透視圖，說明根據本揭露內容的某些態樣中在製造圖2裝置過程中之中間結構範例；
圖3K為一橫剖面透視圖，說明根據本揭露內容的某些態樣中在製造圖2裝置過程中之中間結構範例；
圖3L為一橫剖面透視圖，說明根據本揭露內容的某些態樣中在製造圖2裝置過程中之中間結構範例；
圖3M為一橫剖面透視圖，說明根據本揭露內容的某些態樣中在製造圖2裝置過程中之中間結構範例；以及
圖4是一半導體裝置之橫剖面透視圖，其中閘極電荷可能被轉移至相鄰的閘極結構。

Claims (20)

  1. 一種半導體裝置的製造方法，其步驟包含： 提供其上具有一分層鰭狀物結構的一基板，該分層鰭狀物結構包含一基底鰭狀物部分、設置於該基底鰭狀物部分上的一犧牲部分以及設置於該犧牲部分上的一通道部分； 於該基板上之該分層鰭狀物結構上方設置一摻雜源膜； 自該摻雜源膜將摻雜材料擴散至該分層鰭狀物結構上之該通道部分以外的一部份，以在該分層鰭狀物結構中形成一擴散摻雜區域；以及 於該基板之該分層鰭狀物結構之至少該擴散摻雜區域上方設置一隔離材料。
  2. 如申請專利範圍第1項之半導體裝置的製造方法，其中提供該基板之該步驟包含： 提供作為一鰭本體的該基底鰭狀物，該鰭本體係形成自一摻雜矽塊；以及 於該鰭本體上設置一多層鰭狀物結構，其中該多層鰭狀物結構包含提供以複數SiGe層形成之該犧牲部分，其與形成該通道部分之複數Si層交替形成。
  3. 如申請專利範圍第2項之半導體裝置的製造方法，其中該複數Si層中的每一個均形成一奈米線或奈米平板。
  4. 如申請專利範圍第1項之半導體裝置的製造方法，其中設置該摻雜源膜之該步驟包含將該摻雜源膜僅設置在該分層鰭狀物結構的一部份上方，該摻雜源膜的位置係經選擇以預防該摻雜材料擴散至該通道部分。
  5. 如申請專利範圍第4項之半導體裝置的製造方法，其中該摻雜源膜的該位置係經選擇以覆蓋該分層鰭狀物結構之至少部分的該基底鰭狀物部分。
  6. 如申請專利範圍第5項之半導體裝置的製造方法，其中該摻雜源膜的該位置係經選擇以覆蓋該分層鰭狀物結構之該基底鰭狀物部分。
  7. 如申請專利範圍第6項之半導體裝置的製造方法，其中該摻雜源膜的該位置係經選擇以覆蓋該分層鰭狀物結構之該犧牲部分的一部份。
  8. 如申請專利範圍第1項之半導體裝置的製造方法，其中該擴散步驟包含執行驅動退火加熱，以將該摻雜材料擴散至該分層鰭狀物結構中。
  9. 如申請專利範圍第8項之半導體裝置的製造方法，其中該擴散步驟更包含執行源極/汲極尖峰式退火加熱，以將該摻雜材料擴散至該分層鰭狀物結構中。
  10. 如申請專利範圍第8項之半導體裝置的製造方法，其中該擴散步驟更包含調節該驅動退火的時間及溫度至少其中之一，以防止該摻雜材料擴散至該分層鰭狀物結構之該通道部分中。
  11. 如申請專利範圍第1項之半導體裝置的製造方法，其中設置該隔離材料的該步驟更包含於該基板上形成一淺溝槽隔離層，以覆蓋該分層鰭狀物結構之該擴散摻雜區域。
  12. 如申請專利範圍第1項之半導體裝置的製造方法，其步驟更包含在該分層鰭狀物結構上方設置一屏蔽層，該摻雜源膜係設置於該屏蔽層上。
  13. 如申請專利範圍第1項之半導體裝置的製造方法，其步驟更包含在該擴散步驟之前於該摻雜源膜上方設置一襯墊。
  14. 一種半導體裝置，包含： 一基板； 一鰭狀物結構，位於該基板上，其包含： 一半導體材料之基底鰭狀物部分，該基底鰭狀物部分包含一擴散摻雜區域，以及 一半導體材料之通道部分，其設置於該基底鰭狀物部分上並與該基底鰭狀物部分垂直分開； 一閘極結構，設置於該基底鰭狀物部分與該通道部分之間，其包含一導電材料，其中該擴散摻雜區域係用以將該基底鰭狀物部分與該閘極結構電性隔離；以及 一隔離結構，形成於該基板上，且覆蓋至少該擴散摻雜區域。
  15. 如申請專利範圍第14項之半導體裝置，其中該鰭狀物結構包含： 設置作為該基底鰭狀物部分的一鰭本體，其由摻雜半導體材料塊形成； 設置作為該通道部分之複數個垂直堆疊之半導體層，其中該複數個垂直堆疊之半導體層彼此隔開，且係摻雜成與該摻雜半導體材料相同之極性類型，其中該擴散摻雜區域具有與該摻雜半導體材料相反的極性類型，以提供該鰭本體之逆摻雜。
  16. 如申請專利範圍第15項之半導體裝置，其中該複數個垂直堆疊之半導體層中的每一個均形成一奈米線或奈米平板。
  17. 如申請專利範圍第15項之半導體裝置，其中該摻雜半導體材料塊包含p-型摻雜材料。
  18. 如申請專利範圍第16項之半導體裝置，其中該複數個垂直堆疊之半導體層包含p-型摻雜材料。
  19. 如申請專利範圍第15項之半導體裝置，其中該擴散摻雜區域包含n-型摻雜材料。
  20. 如申請專利範圍第19項之半導體裝置，其中該n-型摻雜材料包含磷或砷。
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