US20190172949A1 - Fabricating method of fin structure with tensile stress and complementary finfet structure - Google Patents

Fabricating method of fin structure with tensile stress and complementary finfet structure Download PDF

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US20190172949A1
US20190172949A1 US16/252,521 US201916252521A US2019172949A1 US 20190172949 A1 US20190172949 A1 US 20190172949A1 US 201916252521 A US201916252521 A US 201916252521A US 2019172949 A1 US2019172949 A1 US 2019172949A1
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fin structure
trenches
silicon oxide
top surface
oxide layer
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US10629734B2 (en
Inventor
Kai-Lin Lee
Zhi-Cheng Lee
Wei-Jen Chen
Ting-Hsuan Kang
Ren-Yu He
Hung-Wen Huang
Chi-Hsiao Chen
Hao-Hsiang Yang
An-Shih Shih
Chuang-Han Hsieh
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Marlin Semiconductor Ltd
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United Microelectronics Corp
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    • H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
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Definitions

  • the present invention relates to a method of fabricating a fin structure with tensile stress, and more particularly to a method of providing tensile stress by two single diffusion breaks.
  • the FinFET Fin Field Effect Transistor
  • the channel is formed by a semiconductor fin with a gate electrode located on at least two sides of the fin. Due to the advantageous feature of full depletion in a FinFET, there are an increased number of sides on which the gate electrode can control the channel of the FinFET, which enhances the controllability of the FinFET channel as compared to a planar MOSFET.
  • One way to influence charge carrier mobility in a channel is to create tensile or compressive stress in the channel region to produce a corresponding strain in the channel region which, in turn, results in a modified mobility for electrons and holes.
  • Creating tensile strain in the channel region can enhance the performance of an N-type FinFET, while creating compressive strain in the channel region may enhance the performance of a P-type FinFET. Therefore, it would be desirable to provide a method which can form tensile or compressive stress individually in both N-type FinFET and P-type FinFET devices.
  • a method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer which fills the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
  • a complementary FinFET structure includes an N-type FinFET and a P-type FinFET.
  • the N-type FinFET includes a first fin structure, two shallow trench isolations respectively disposed at two sides of the first fin structure, two first single diffusion breaks respectively disposed at two ends of the first fin structure, wherein a top surface of each of the first single diffusion breaks is not lower than a top surface of the first fin structure, a first gate structure crossing the first fin structure, and two first source/drain doped regions respectively disposed in the first fin structure at two sides of the first gate structure.
  • the P-type FinFET includes a second fin structure, the shallow trench isolations respectively disposed at two sides of the second fin structure, two second single diffusion breaks respectively disposed at two ends of the second fin structure, wherein a top surface of each of the second single diffusion breaks is lower than a top surface of the second fin structure, a second gate structure crossing the second fin structure, and two second source/drain doped regions respectively disposed in the second fin structure at two sides of the second gate structure.
  • FIG. 1 to FIG. 8 depict a fabricating method of a fin structure with tensile stress according to a first preferred embodiment of the present invention, wherein:
  • FIG. 1 shows a top view of a substrate, first trenches and second trenches
  • FIG. 2 depicts a sectional view of FIG. 1 taken along line A-A′, and line B-B′;
  • FIG. 3 is a fabricating stage following FIG. 2 ;
  • FIG. 4 is a fabricating stage following FIG. 3 ;
  • FIG. 5 is a fabricating stage following FIG. 4 ;
  • FIG. 6 is a fabricating stage following FIG. 5 ;
  • FIG. 7 is a fabricating stage following FIG. 6 ;
  • FIG. 8 is a fabricating stage following FIG. 7 .
  • FIG. 9 to FIG. 10 depict a fabricating method of a fin structure with tensile stress according to a second preferred embodiment of the present invention, wherein:
  • FIG. 9 shows a top surface of a SDB aligned with a top surface of a first fin structure
  • FIG. 10 is a fabricating stage following FIG. 9 .
  • FIG. 1 to FIG. 8 depict a fabricating method of a fin structure with tensile stress according to a first preferred embodiment of the present invention, wherein FIG. 1 shows a top view of a substrate, first trenches and second trenches.
  • Example (a) in FIG. 2 depicts a sectional view of FIG. 1 taken along line A-A′.
  • Example (b) in FIG. 2 depicts a sectional view of FIG. 1 taken along line B-B′.
  • FIG. 3 continues from FIG. 2 , wherein Example (a) and Example (b) illustrated in FIG. 3 to FIG. 8 are continuations of Example (a) and Example (b) in the previous figure.
  • a substrate 10 such as a silicon substrate is provided.
  • the substrate 10 is divided into an N-type transistor region 100 and a P-type transistor region 200 .
  • numerous first trenches 12 and numerous second trenches 14 are formed within the substrate 10 .
  • the second trenches 14 segment the first trenches 12 .
  • each of the second trenches 14 crosses all of the first trenches 12 .
  • Two adjacent first trenches 12 define a long fin structure.
  • Numerous second trenches 14 segment the long fin structure into numerous short fin structures.
  • Each of the short fin structures within the N-type transistor region 100 is named as a first fin structure 16 .
  • Each of the short fin structures within the P-type transistor region 200 is named as a second fin structure 18 .
  • a top surface of the first fin structure 16 is aligned with a top surface of the second fin structure 18 .
  • a flowable chemical vapor deposition (FCVD) process is performed to form a silicon oxide layer 20 which covers the entire substrate 10 and fills each of the first trenches 12 , and each of the second trenches 14 .
  • the FCVD process is performed by coating the silicon oxide layer 20 on the substrate 10 via spinning the wafer. After the FCVD, the silicon oxide layer 20 is densified by a thermal process. Later, as shown in FIG. 4 , a planarization process is performed to planarize the silicon oxide layer 20 , while maintaining the height of the top surface of the silicon oxide layer 20 as not lower than the top surface of the first fin structure 16 and the top surface of the second fin structure 18 .
  • FIG. 4 takes the top surface of the silicon oxide layer 20 being higher than the top surface of the first fin structure 16 and the top surface of the second fin structure 18 as an example.
  • a mask layer (not shown) is formed to entirely cover the substrate 10 .
  • the mask layer can be a photoresist.
  • the mask layer is patterned to become a patterned mask layer 22 .
  • the patterned mask layer 22 is only disposed within the N-type transistor region 100 , and only overlaps the silicon oxide layer 20 within the second trenches 14 .
  • part of the silicon oxide layer 22 is removed by taking the patterned mask layer 22 as a mask to make both the top surface of the silicon oxide layer 20 in the first trenches 12 within the N-type transistor region 100 and the top surface of the silicon oxide layer 20 within the P-type transistor region 200 lower than the top surface of the first fin structure 16 and the top surface of the second fin structure 18 .
  • the horizontal surface of the substrate 10 is exposed.
  • the patterned mask layer 22 is removed.
  • the silicon oxide layer 20 remaining in the first trenches 12 serves as a shallow trench isolation (STI) 24 .
  • Numerous STIs 24 are shown in this embodiment.
  • the silicon oxide layer 20 remaining in the second trenches 14 serves as a single diffusion break (SDB) 26 .
  • SDB single diffusion break
  • the SDB within the N-type transistor region 100 is designated as numeral 26 a
  • the SDB within the P-type transistor region 200 is designated as numeral 26 b.
  • the positions of the SDBs 26 b within the P-type doped region 200 and the STIs 24 on the substrate 10 are not covered by the patterned mask layer 22 ; therefore, the SDBs 26 b and the STIs 24 are formed simultaneously so the top surfaces of the SDBs 26 b and the top surfaces of the STIs 24 are all lower than the top surface of the first fin structure 16 and second fin structure 18 . Moreover, the top surfaces of the SDB 26 b are aligned with the top surfaces of the STIs 24 .
  • the silicon oxide layer 20 formed by the FCVD process contains tensile stress.
  • the top surfaces of the SDB 26 a are not lower than the top surface of the first fin structure 16 , and the SDBs 26 a sandwich the first fin structure 16 within the N-type doped region 100 . Therefore, the silicon oxide layer 20 can provide tensile stress to the first fin structure 16 .
  • the top surfaces of the SDBs 26 b at two ends of the second fin structure 18 are lower than the top surface of the second fin structure 18 , meaning the SDBs 26 b do not provide tensile stress to the second fin structure 18 .
  • a compressive material such as silicon nitride can be formed within each of the second trenches 14 , wherein the top surface of the compressive material is higher than the top surface of the second fin structure 16 .
  • a gate structure process is performed to form a first gate structure 28 and the second gate structure 30 on, respectively, the first fin structure 16 and the second fin structure 18 .
  • a passing gate structure 32 is formed on each of the SDBs 26 a/ 26 b. There are four passing gate structures 32 shown in this embodiment.
  • a spacer 34 is formed on the first gate structure 28 , the second gate structure 30 , and the passing gate structures 32 .
  • the sidewalls of the passing gate structures may not cross the sidewalls of the SDBs 26 a/ 26 b. In another embodiment, the sidewalls of the passing gate structures may cross the sidewalls of the SDBs 26 a/ 26 b and directly contact the first fin structure 16 or the second fin structure 18 .
  • the first gate structure 28 , the second gate structure 30 and the passing gate structure 32 respectively include a polysilicon gate 36 and a dielectric layer 38 .
  • recesses (not shown) are formed in the first fin structure 16 and the second fin structure 18 at two sides of the first gate structure 28 , the second gate structure 30 and the passing gate structure 32 .
  • an epitaxial layer 40 fills in the recesses.
  • N-type dopants are implanted into the epitaxial layer 40 in the first fin structure 16 , and the epitaxial layer 40 in the first fin structure 16 serves as a source/drain doped regions 42 .
  • the source/drain doped regions 42 and the source/drain doped regions 44 can be formed by implanting dopants into the substrate 10 without forming the epitaxial layer 40 .
  • an interlayer dielectric 46 is formed.
  • contact plugs can be formed in the interlayer dielectric 46 to connect the source/drain doped regions 42 / 44 .
  • a replacement metal gate process can be performed after the contact plugs are formed.
  • the replacement metal gate process can be performed by the steps of removing the first gate structure 28 , the second gate structure 30 and the passing gate structures 32 to form numerous recesses (not shown). Then, a gate dielectric layer 48 and a work function layer (not shown) fill into the recesses.
  • the gate dielectric layer 48 is generally made of high-k dielectric materials. In addition, the gate dielectric layer 48 and the work function layer can be altered based on different requirements.
  • the metal gate 50 is formed on the work function layer.
  • the metal gate 50 , the gate dielectric layer 48 and the work function layer within the N-type transistor region 100 serve as a first metal gate structure 52 .
  • the metal gate 50 , the gate dielectric layer 48 and the work function layer within the P-type transistor region 200 serve as a second metal gate structure 54 . Because the replacement metal gate process is a conventional process, the details of this process are omitted. At this point, a complementary FinFET structure 300 is completed.
  • the top surface silicon oxide layer 20 can become aligned with the top surface of the first fin structure 16 .
  • the following process is the same as that in the FIG. 5 to FIG. 8 , and another complementary FinFET structure 300 can be formed as shown in FIG. 10 .
  • the feature of the complementary FinFET structure 300 in FIG. 10 is that the top surface of the SDBs 26 a is aligned with the first fin structure 16 .
  • a complementary FinFET structure 300 includes a substrate 10 .
  • the substrate 10 is divided into an N-type transistor region 100 and a P-type transistor region 200 .
  • An N-type FinFET 400 and a P-type FinFET 500 are respectively disposed within the N-type transistor region 100 and the P-type transistor region 200 .
  • the N-type FinFET 400 includes a first fin structure 16 , and two STIs 24 respectively disposed at two sides of the first fin structure 16 .
  • Two SDBs 26 a are respectively disposed at two ends of the first fin structure 16 .
  • a top surface of each of the SDBs 26 a is not lower than a top surface of the first fin structure 16 .
  • the P-type FinFET 500 includes a second fin structure 18 and two STIs 24 respectively disposed at two sides of the second fin structure 18 .
  • the relative position of the STIs 24 disposed at two sides of the second fin structure 18 is the same as the relative position of the STIs 24 disposed at two sides of the first fin structure 16 , please refer to the position of the STIs 24 and the first fin structure 16 .
  • Two SDBs 26 b are respectively disposed at two ends of the second fin structure 18 .
  • a top surface of each of the SDBs 26 b is lower than a top surface of the second fin structure 18 .
  • a second gate structure such as a second metal gate structure 54 crosses the second fin structure 18 .
  • Two second source/drain doped regions 44 are respectively disposed in the second fin structure 18 at two sides of the second metal gate structure 54 .
  • the SDBs 26 a are made of the silicon oxide layer 20 formed by the FCVD process. Therefore, the SDBs 26 a provide tensile stress to the first fin structure 16 . As a result, the channel region of the N-type FinFET 400 contains tensile stress, and the electron mobility is increased. As tensile stress is not needed in the P-type FinFET 500 , the top surface of the SDBs 26 b at two ends of the second fin structure 18 is lower than the top surface of the second fin structure 18 .
  • a top surface of the SDBs 26 a can be aligned with the top surface of the first fin structure 16 as shown in FIG. 10 .
  • the top surface of the SDBs 26 a at two ends of the first fin structure 16 are aligned with the top surface of the first fin structure 16 to provide the tensile stress for the N-type FinFET 400 .
  • Other elements are the same as those in FIG. 8 , and therefore omitted here.

Abstract

A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This patent application is a divisional application of and claims priority to U.S. patent application Ser. No. 15/668,719, filed on Aug. 4, 2017, and entitled “FABRICATING METHOD OF FIN STRUCTURE WITH TENSILE STRESS AND COMPLEMENTARY FINFET STRUCTURE” the entire contents of which are incorporated herein by reference.
    • BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The present invention relates to a method of fabricating a fin structure with tensile stress, and more particularly to a method of providing tensile stress by two single diffusion breaks.
    • 2. Description of the Prior Art
  • As integrated circuits continue to be scaled downwards in size, the FinFET (Fin Field Effect Transistor) is becoming an attractive device. In a FinFET, the channel is formed by a semiconductor fin with a gate electrode located on at least two sides of the fin. Due to the advantageous feature of full depletion in a FinFET, there are an increased number of sides on which the gate electrode can control the channel of the FinFET, which enhances the controllability of the FinFET channel as compared to a planar MOSFET.
  • One way to influence charge carrier mobility in a channel is to create tensile or compressive stress in the channel region to produce a corresponding strain in the channel region which, in turn, results in a modified mobility for electrons and holes. Creating tensile strain in the channel region can enhance the performance of an N-type FinFET, while creating compressive strain in the channel region may enhance the performance of a P-type FinFET. Therefore, it would be desirable to provide a method which can form tensile or compressive stress individually in both N-type FinFET and P-type FinFET devices.
    • SUMMARY OF THE INVENTION
  • According to a first preferred embodiment of the present invention, a method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer which fills the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
  • According to a second preferred embodiment of the present invention, a complementary FinFET structure includes an N-type FinFET and a P-type FinFET. The N-type FinFET includes a first fin structure, two shallow trench isolations respectively disposed at two sides of the first fin structure, two first single diffusion breaks respectively disposed at two ends of the first fin structure, wherein a top surface of each of the first single diffusion breaks is not lower than a top surface of the first fin structure, a first gate structure crossing the first fin structure, and two first source/drain doped regions respectively disposed in the first fin structure at two sides of the first gate structure. The P-type FinFET includes a second fin structure, the shallow trench isolations respectively disposed at two sides of the second fin structure, two second single diffusion breaks respectively disposed at two ends of the second fin structure, wherein a top surface of each of the second single diffusion breaks is lower than a top surface of the second fin structure, a second gate structure crossing the second fin structure, and two second source/drain doped regions respectively disposed in the second fin structure at two sides of the second gate structure.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 to FIG. 8 depict a fabricating method of a fin structure with tensile stress according to a first preferred embodiment of the present invention, wherein:
  • FIG. 1 shows a top view of a substrate, first trenches and second trenches;
  • FIG. 2 depicts a sectional view of FIG. 1 taken along line A-A′, and line B-B′;
  • FIG. 3 is a fabricating stage following FIG. 2;
  • FIG. 4 is a fabricating stage following FIG. 3;
  • FIG. 5 is a fabricating stage following FIG. 4;
  • FIG. 6 is a fabricating stage following FIG. 5;
  • FIG. 7 is a fabricating stage following FIG. 6; and
  • FIG. 8 is a fabricating stage following FIG. 7.
  • FIG. 9 to FIG. 10 depict a fabricating method of a fin structure with tensile stress according to a second preferred embodiment of the present invention, wherein:
  • FIG. 9 shows a top surface of a SDB aligned with a top surface of a first fin structure; and
  • FIG. 10 is a fabricating stage following FIG. 9.
    •  DETAILED DESCRIPTION
  • FIG. 1 to FIG. 8 depict a fabricating method of a fin structure with tensile stress according to a first preferred embodiment of the present invention, wherein FIG. 1 shows a top view of a substrate, first trenches and second trenches. Example (a) in FIG. 2 depicts a sectional view of FIG. 1 taken along line A-A′. Example (b) in FIG. 2 depicts a sectional view of FIG. 1 taken along line B-B′. FIG. 3 continues from FIG. 2, wherein Example (a) and Example (b) illustrated in FIG. 3 to FIG. 8 are continuations of Example (a) and Example (b) in the previous figure.
  • Please refer to FIG. 1 and FIG. 2. A substrate 10 such as a silicon substrate is provided. The substrate 10 is divided into an N-type transistor region 100 and a P-type transistor region 200. Next, numerous first trenches 12 and numerous second trenches 14 are formed within the substrate 10. The second trenches 14 segment the first trenches 12. In detail, each of the second trenches 14 crosses all of the first trenches 12. Two adjacent first trenches 12 define a long fin structure. Numerous second trenches 14 segment the long fin structure into numerous short fin structures. Each of the short fin structures within the N-type transistor region 100 is named as a first fin structure 16. Each of the short fin structures within the P-type transistor region 200 is named as a second fin structure 18. A top surface of the first fin structure 16 is aligned with a top surface of the second fin structure 18.
  • As shown in FIG. 3, a flowable chemical vapor deposition (FCVD) process is performed to form a silicon oxide layer 20 which covers the entire substrate 10 and fills each of the first trenches 12, and each of the second trenches 14. The FCVD process is performed by coating the silicon oxide layer 20 on the substrate 10 via spinning the wafer. After the FCVD, the silicon oxide layer 20 is densified by a thermal process. Later, as shown in FIG. 4, a planarization process is performed to planarize the silicon oxide layer 20, while maintaining the height of the top surface of the silicon oxide layer 20 as not lower than the top surface of the first fin structure 16 and the top surface of the second fin structure 18. FIG. 4 takes the top surface of the silicon oxide layer 20 being higher than the top surface of the first fin structure 16 and the top surface of the second fin structure 18 as an example.
  • Refer to FIG. 5. A mask layer (not shown) is formed to entirely cover the substrate 10. The mask layer can be a photoresist. Then, the mask layer is patterned to become a patterned mask layer 22. The patterned mask layer 22 is only disposed within the N-type transistor region 100, and only overlaps the silicon oxide layer 20 within the second trenches 14. As shown in FIG. 6, part of the silicon oxide layer 22 is removed by taking the patterned mask layer 22 as a mask to make both the top surface of the silicon oxide layer 20 in the first trenches 12 within the N-type transistor region 100 and the top surface of the silicon oxide layer 20 within the P-type transistor region 200 lower than the top surface of the first fin structure 16 and the top surface of the second fin structure 18. At the same time, the horizontal surface of the substrate 10 is exposed. Then, the patterned mask layer 22 is removed. At this point, the silicon oxide layer 20 remaining in the first trenches 12 serves as a shallow trench isolation (STI) 24. Numerous STIs 24 are shown in this embodiment. The silicon oxide layer 20 remaining in the second trenches 14 serves as a single diffusion break (SDB) 26. In order to clearly describe the present invention, the SDB within the N-type transistor region 100 is designated as numeral 26 a, and the SDB within the P-type transistor region 200 is designated as numeral 26 b. There are two SDBs 26 a respectively disposed at two ends of the first fins structure 16, and two SDBs 26 b respectively disposed at two ends of the second fins structure 18. It is noteworthy that the positions of the SDBs 26 a are protected by the patterned mask layer 22 while the silicon oxide layer 20 in other places is removed. Therefore, the top surfaces of the SDBs 26 a within the N-type doped region 100 are not lower than the top surface of the first fin structure 16. The positions of the SDBs 26 b within the P-type doped region 200 and the STIs 24 on the substrate 10 are not covered by the patterned mask layer 22; therefore, the SDBs 26 b and the STIs 24 are formed simultaneously so the top surfaces of the SDBs 26 b and the top surfaces of the STIs 24 are all lower than the top surface of the first fin structure 16 and second fin structure 18. Moreover, the top surfaces of the SDB 26 b are aligned with the top surfaces of the STIs 24.
  • The silicon oxide layer 20 formed by the FCVD process contains tensile stress. The top surfaces of the SDB 26 a are not lower than the top surface of the first fin structure 16, and the SDBs 26 a sandwich the first fin structure 16 within the N-type doped region 100. Therefore, the silicon oxide layer 20 can provide tensile stress to the first fin structure 16. The top surfaces of the SDBs 26 b at two ends of the second fin structure 18, however, are lower than the top surface of the second fin structure 18, meaning the SDBs 26 b do not provide tensile stress to the second fin structure 18. If compressive stress needs to be added to the second fin structure 18, a compressive material (not shown) such as silicon nitride can be formed within each of the second trenches 14, wherein the top surface of the compressive material is higher than the top surface of the second fin structure 16.
  • Next, as shown in FIG. 7, a gate structure process is performed to form a first gate structure 28 and the second gate structure 30 on, respectively, the first fin structure 16 and the second fin structure 18. A passing gate structure 32 is formed on each of the SDBs 26 a/ 26 b. There are four passing gate structures 32 shown in this embodiment. A spacer 34 is formed on the first gate structure 28, the second gate structure 30, and the passing gate structures 32. The sidewalls of the passing gate structures may not cross the sidewalls of the SDBs 26 a/ 26 b. In another embodiment, the sidewalls of the passing gate structures may cross the sidewalls of the SDBs 26 a/ 26 b and directly contact the first fin structure 16 or the second fin structure 18. The first gate structure 28, the second gate structure 30 and the passing gate structure 32 respectively include a polysilicon gate 36 and a dielectric layer 38. Later, recesses (not shown) are formed in the first fin structure 16 and the second fin structure 18 at two sides of the first gate structure 28, the second gate structure 30 and the passing gate structure 32. Then, an epitaxial layer 40 fills in the recesses. N-type dopants are implanted into the epitaxial layer 40 in the first fin structure 16, and the epitaxial layer 40 in the first fin structure 16 serves as a source/drain doped regions 42. P-type dopants are implanted into the epitaxial layer 40 in the second fin structure 18, and the epitaxial layer 40 in the second fin structure 18 serves as a source/drain doped regions 44. According to another preferred embodiment of the present invention, the source/drain doped regions 42 and the source/drain doped regions 44 can be formed by implanting dopants into the substrate 10 without forming the epitaxial layer 40. Subsequently, an interlayer dielectric 46 is formed. Next, contact plugs can be formed in the interlayer dielectric 46 to connect the source/drain doped regions 42/44.
  • As shown in FIG. 8, if a metal gate is needed in the transistor formed afterwards, a replacement metal gate process can be performed after the contact plugs are formed. The replacement metal gate process can be performed by the steps of removing the first gate structure 28, the second gate structure 30 and the passing gate structures 32 to form numerous recesses (not shown). Then, a gate dielectric layer 48 and a work function layer (not shown) fill into the recesses. The gate dielectric layer 48 is generally made of high-k dielectric materials. In addition, the gate dielectric layer 48 and the work function layer can be altered based on different requirements. Next, the metal gate 50 is formed on the work function layer. The metal gate 50, the gate dielectric layer 48 and the work function layer within the N-type transistor region 100 serve as a first metal gate structure 52. The metal gate 50, the gate dielectric layer 48 and the work function layer within the P-type transistor region 200 serve as a second metal gate structure 54. Because the replacement metal gate process is a conventional process, the details of this process are omitted. At this point, a complementary FinFET structure 300 is completed.
  • As shown in FIG. 9, according to another preferred embodiment of the present invention, during the planarization process, the top surface silicon oxide layer 20 can become aligned with the top surface of the first fin structure 16. The following process is the same as that in the FIG. 5 to FIG. 8, and another complementary FinFET structure 300 can be formed as shown in FIG. 10. The feature of the complementary FinFET structure 300 in FIG. 10 is that the top surface of the SDBs 26 a is aligned with the first fin structure 16.
  • As shown in FIG. 8, a complementary FinFET structure 300 includes a substrate 10. The substrate 10 is divided into an N-type transistor region 100 and a P-type transistor region 200. An N-type FinFET 400 and a P-type FinFET 500 are respectively disposed within the N-type transistor region 100 and the P-type transistor region 200. The N-type FinFET 400 includes a first fin structure 16, and two STIs 24 respectively disposed at two sides of the first fin structure 16. Two SDBs 26 a are respectively disposed at two ends of the first fin structure 16. A top surface of each of the SDBs 26 a is not lower than a top surface of the first fin structure 16. FIG. 8 takes the top surface of the SDBs 26 a being higher than the top surface of the first fin structure 16 as an example. A first gate structure such as a first metal gate structure 52 crosses the first fin structure 16. Two first source/drain doped regions 42 are respectively disposed in the first fin structure 16 at two sides of the first metal gate structure 52. The P-type FinFET 500 includes a second fin structure 18 and two STIs 24 respectively disposed at two sides of the second fin structure 18. The relative position of the STIs 24 disposed at two sides of the second fin structure 18 is the same as the relative position of the STIs 24 disposed at two sides of the first fin structure 16, please refer to the position of the STIs 24 and the first fin structure 16. Two SDBs 26 b are respectively disposed at two ends of the second fin structure 18. A top surface of each of the SDBs 26 b is lower than a top surface of the second fin structure 18. A second gate structure such as a second metal gate structure 54 crosses the second fin structure 18. Two second source/drain doped regions 44 are respectively disposed in the second fin structure 18 at two sides of the second metal gate structure 54.
  • It is noteworthy that there are two SDBs 26 a at two ends of the first fin structure 16 of the N-type FinFET 400. The SDBs 26 a are made of the silicon oxide layer 20 formed by the FCVD process. Therefore, the SDBs 26 a provide tensile stress to the first fin structure 16. As a result, the channel region of the N-type FinFET 400 contains tensile stress, and the electron mobility is increased. As tensile stress is not needed in the P-type FinFET 500, the top surface of the SDBs 26 b at two ends of the second fin structure 18 is lower than the top surface of the second fin structure 18.
  • According to another preferred embodiment of the present invention, a top surface of the SDBs 26 a can be aligned with the top surface of the first fin structure 16 as shown in FIG. 10. The top surface of the SDBs 26 a at two ends of the first fin structure 16 are aligned with the top surface of the first fin structure 16 to provide the tensile stress for the N-type FinFET 400. Other elements are the same as those in FIG. 8, and therefore omitted here.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (5)

What is claimed is:
1. A fabricating method of a fin structure with tensile stress, comprising:
providing a substrate comprising an N-type transistor region and a P-type transistor region;
forming two first trenches and two second trenches within the substrate, wherein the first trenches define a fin structure, and the second trenches segment the first trenches;
performing a flowable chemical vapor deposition process to form a silicon oxide layer in the first trenches and the second trenches;
planarizing the silicon oxide layer, wherein after planarizing the silicon oxide layer, a top surface of the silicon oxide layer is not lower than a top surface of the fin structure;
forming a patterned mask layer only within the N-type transistor region, wherein the patterned mask layer only overlaps the silicon oxide layer within the second trenches;
removing part of the silicon oxide layer by taking the patterned mask layer as a mask to make both the top surface of the silicon oxide layer in the first trenches within the N-type transistor region and the top surface of the silicon oxide layer within the P-type transistor region lower than the top surface of the fin structure; and
removing the patterned mask layer.
2. The fabricating method of a fin structure with tensile stress of claim 1, wherein:
after planarizing the silicon oxide layer and before forming the patterned mask layer, the top surface of the silicon oxide layer is higher than the top surface of the fin structure; and
after removing the patterned mask layer, the top surface of the silicon oxide layer within the second trenches within the N-type transistor region is higher than the top surface of the fin structure.
3. The fabricating method of a fin structure with tensile stress of claim 1, wherein:
after planarizing the silicon oxide layer and before forming the patterned mask layer, the top surface the silicon oxide layer is aligned with the top surface of the fin structure; and
after removing the patterned mask layer, the top surface of the silicon oxide layer within the second trenches within the N-type transistor region is aligned with the top surface of the fin structure.
4. The fabricating method of a fin structure with tensile stress of claim 1, wherein the patterned mask layer is not formed within the P-type transistor region.
5. The fabricating method of a fin structure with tensile stress of claim 4, wherein the top surface of the silicon oxide layer in the second trenches within the P-type transistor region is aligned with the silicon oxide layer in the first trenches within the P-type transistor region.
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10700204B2 (en) * 2018-08-17 2020-06-30 Qualcomm Incorporated Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods
CN112864016B (en) * 2019-11-26 2023-11-21 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN113314467A (en) * 2020-02-26 2021-08-27 联华电子股份有限公司 Semiconductor element and manufacturing method thereof

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7211864B2 (en) * 2003-09-15 2007-05-01 Seliskar John J Fully-depleted castellated gate MOSFET device and method of manufacture thereof
US7314836B2 (en) * 2004-06-30 2008-01-01 Intel Corporation Enhanced nitride layers for metal oxide semiconductors
US7271442B2 (en) * 2005-01-12 2007-09-18 International Business Machines Corporation Transistor structure having stressed regions of opposite types underlying channel and source/drain regions
US7719058B2 (en) * 2005-10-12 2010-05-18 Seliskar John J Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof
CN101711300B (en) * 2007-05-01 2013-08-14 史丹利安全科技有限公司 Key and core with side pin
US7906381B2 (en) * 2007-07-05 2011-03-15 Stmicroelectronics S.A. Method for integrating silicon-on-nothing devices with standard CMOS devices
US8941153B2 (en) * 2009-11-20 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with different fin heights
US8937353B2 (en) * 2010-03-01 2015-01-20 Taiwan Semiconductor Manufacturing Co., Ltd. Dual epitaxial process for a finFET device
US7947551B1 (en) 2010-09-28 2011-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a shallow trench isolation structure
US8735252B2 (en) 2012-06-07 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor integrated circuit fabrication
US8927388B2 (en) 2012-11-15 2015-01-06 United Microelectronics Corp. Method of fabricating dielectric layer and shallow trench isolation
US9087869B2 (en) * 2013-05-23 2015-07-21 International Business Machines Corporation Bulk semiconductor fins with self-aligned shallow trench isolation structures
KR102066848B1 (en) * 2013-06-24 2020-01-16 삼성전자 주식회사 Semiconductor device and method for fabricating the same
WO2014209396A1 (en) * 2013-06-28 2014-12-31 Intel Corporation Integrating vlsi-compatible fin structures with selective epitaxial growth and fabricating devices thereon
KR102138506B1 (en) * 2013-07-15 2020-07-28 엘지전자 주식회사 Mobile terminal
US8981487B2 (en) * 2013-07-31 2015-03-17 United Microelectronics Corp. Fin-shaped field-effect transistor (FinFET)
CN104733390B (en) * 2013-12-20 2018-06-26 台湾积体电路制造股份有限公司 For the mechanism of FinFET traps doping
US9419134B2 (en) * 2014-01-13 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Strain enhancement for FinFETs
TWI600159B (en) * 2014-10-01 2017-09-21 聯華電子股份有限公司 Semiconductor device and method for fabricating the same
TWI610435B (en) * 2014-11-17 2018-01-01 聯華電子股份有限公司 High-voltage finfet device having ldmos structure and method for manufacturing the same
US9281379B1 (en) * 2014-11-19 2016-03-08 International Business Machines Corporation Gate-all-around fin device
US9887165B2 (en) * 2014-12-10 2018-02-06 Stmicroelectronics S.R.L. IC with insulating trench and related methods
KR102446858B1 (en) * 2015-08-07 2022-09-23 삼성디스플레이 주식회사 Method for manufacturing quantum dots
TWI675406B (en) * 2015-10-07 2019-10-21 聯華電子股份有限公司 Semiconductor device and method for fabricating the same
KR102323943B1 (en) * 2015-10-21 2021-11-08 삼성전자주식회사 Method of manufacturing semiconductor device
CN106803484B (en) * 2015-11-26 2021-08-10 联华电子股份有限公司 Semiconductor element and manufacturing method thereof
US9659943B1 (en) * 2016-03-08 2017-05-23 Globalfoundries Singapore Pte. Ltd. Programmable integrated circuits and methods of forming the same
US20170373144A1 (en) * 2016-06-28 2017-12-28 GlobalFoundries, Inc. Novel sti process for sdb devices
US9589970B1 (en) * 2016-08-02 2017-03-07 United Microelectronics Corp. Antifuse one-time programmable memory
US9917103B1 (en) * 2017-01-04 2018-03-13 Globalfoundries Inc. Diffusion break forming after source/drain forming and related IC structure
CN109216191B (en) * 2017-06-29 2022-08-16 蓝枪半导体有限责任公司 Semiconductor element and manufacturing method thereof

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