CN109801905A - 与传热板有关的半导体封装体及其制造方法 - Google Patents
与传热板有关的半导体封装体及其制造方法 Download PDFInfo
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- CN109801905A CN109801905A CN201811139296.XA CN201811139296A CN109801905A CN 109801905 A CN109801905 A CN 109801905A CN 201811139296 A CN201811139296 A CN 201811139296A CN 109801905 A CN109801905 A CN 109801905A
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Abstract
本申请可以提供一种半导体封装体和制造该半导体封装体的方法。半导体封装体可以包括设置在互连层的第一表面上的第一半导体芯片、设置在互连层的第二表面上的第二半导体芯片和第三半导体芯片。半导体封装体可以包括传热板,该传热板设置在第二半导体芯片与第三半导体芯片之间、与互连层的第二表面接触并且与第一半导体芯片重叠。传热板可以被配置为提供热散发路径。
Description
相关申请的交叉引用
本申请要求于2017年11月16日提交的申请号为10-2017-0153368的韩国专利申请的优先权,该申请通过引用整体并入本文。
技术领域
本公开总体而言涉及一种半导体封装体技术,并且更具体地,涉及一种与传热板有关的半导体封装体及其制造方法。
背景技术
半导体封装体已经用于诸如移动电话或计算机的电子系统中。已经集中大量精力将多个半导体芯片集成到单个封装体中,使得单个封装体执行多功能操作,同时还能够以高速处理大量数据。例如,已经提出2.5维(2.5D)系统级封装(SIP)技术来将处理器芯片和存储芯片并排设置在插入器上。由于各种类型的半导体芯片嵌入在单个封装体中,因此可能需要用于散发由单个封装体中的特定半导体芯片产生的热量的冷却结构,以防止单个封装体的性能劣化。
发明内容
根据一个实施例,一种半导体封装体可以包括设置在互连层的第一表面上的第一半导体芯片。所述半导体封装体可以包括彼此间隔开并且设置在所述互连层的第二表面上的第二半导体芯片和第三半导体芯片。所述半导体封装体可以包括传热板,所述传热板设置在所述第二半导体芯片与所述第三半导体芯片之间、与所述互连层的第二表面接触并且与所述第一半导体芯片重叠。所述传热板可以提供热散发路径。
根据一个实施例,一种半导体封装体可以包括设置在互连层的第一表面上的第一半导体芯片。所述半导体封装体可以包括设置在所述互连层的第二表面上的第二半导体芯片,使得所述第一半导体芯片的四个角区域(corner region)分别与所述第二半导体芯片的边缘区域重叠。所述半导体封装体可以包括传热板,所述传热板设置在所述第二半导体芯片之间以与所述互连层的第二表面接触并且与所述第一半导体芯片重叠。所述传热板可以提供热散发路径。
根据一个实施例,提供了一种制造半导体封装体的方法。所述方法可以包括将传热板设置在第二半导体芯片与第三半导体芯片之间。所述方法可以包括形成用于固定所述第二半导体芯片和所述第三半导体芯片以及所述传热板的模塑层。所述方法可以包括在所述第二半导体芯片和所述传热板上形成互连层,使得所述互连层的第二表面与所述第二半导体芯片和所述传热板接触。所述方法可以包括将第一半导体芯片设置在所述互连层的第一表面上以与热所述转移板重叠。
附图说明
图1是示出根据一个实施例的半导体封装体的平面图。
图2是沿图1的线A-A'截取的截面图。
图3是示出图2中所示的半导体封装体的热传导路径的截面图。
图4是示出根据一个实施例的半导体封装体的截面图。
图5至图7是示出在根据一个实施例的半导体封装体中包括的互连层的配置的截面图。
图8是示出在根据一个实施例的半导体封装体中包括的半导体芯片的截面图。
图9至图14是示出根据一个实施例的制造半导体封装体的方法的截面图。
图15是示出采用包括根据一个实施例的半导体封装体的存储卡的电子系统的框图。
图16是示出包括根据一个实施例的半导体封装体的电子系统的框图。
具体实施方式
本文中使用的术语可以对应于考虑到它们在实施例中的功能而选择的词语,并且这些术语的含义可以被解释为根据实施例所属领域的普通技术而不同。如果被详细定义,则这些术语可以根据其定义解释。除非另外定义,否则本文中使用的术语(包括技术术语和科学术语)具有与实施例所属领域的普通技术人员通常理解的含义相同的含义。
应当理解,尽管本文中可以使用术语“第一”、“第二”、“第三”等来描述各种元件,但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一个元件区分开,但不用于仅定义元件本身或用于表示特定次序。
还应理解,当一个元件或层被称为在另一元件或层“上”、“之上”、“下”、“之下”或“外部”时,该元件或层可以与该另一元件或层直接接触,或者可以存在中间元件或层。用于描述元件或层之间的关系的其他词语应以类似的方式来解释(例如,“在...之间”对“直接在...之间”或“相邻”对“直接相邻”)。
例如,如附图中所示,空间相对术语,诸如“之下”、“下方”、“下面”、“之上”、“上方”、“顶”、“底”等可以用于描述一个元件和/或特征与另一个元件和/或特征的关系。应当理解,除了附图中所示的取向之外,空间相对术语旨在包括使用和/或操作中的设备的不同取向。例如,当附图中的设备翻转时,描述为在其他元件或特征下面和/或下方的元件将被定向为在其他元件或特征之上。该设备可以以其他方式定向(旋转90度或在其他取向处),并且相应地解释本文中使用的空间相对描述符。
半导体封装体可以包括诸如半导体芯片或半导体裸片的电子设备。半导体芯片或半导体裸片可以通过使用裸片切割工艺来将诸如晶片的半导体衬底分离成多个片来获得。半导体芯片可以对应于存储芯片、逻辑芯片(包括专用集成电路(ASIC)芯片)或片上系统(SoC)。存储芯片可以包括集成在半导体衬底上的动态随机存取存储器(DRAM)电路、静态随机存取存储器(SRAM)电路、NAND型快闪存储器电路、NOR型快闪存储器电路、磁性随机存取存储器(MRAM)电路、电阻式随机存取存储器(ReRAM)电路、铁电随机存取存储器(FeRAM)电路或相变随机存取存储器(PcRAM)电路。逻辑芯片可以包括集成在半导体衬底上的逻辑电路。半导体封装体可以用于诸如移动电话的通信系统、与生物技术或医疗保健相关的电子系统或可穿戴电子系统中。
在整个说明书中,相同的附图标记表示相同的元件。尽管一个附图标记没有参考附图而被提及或描述,但是该附图标记可以参考另一个附图而被提及或描述。另外,即使附图标记未在附图中示出,但是其也可以参考另一个附图而被提及或描述。
本公开可以提供半导体封装体,每个半导体封装体可以被配置为包括多个半导体芯片和传热板,所述多个半导体芯片在互连层上面和下面三维地层叠,并且所述传热板可以被设置为与多个半导体芯片中的任意一个垂直地重叠并与互连层接触。
图1是示出根据一个实施例的半导体封装体100的平面图。图2是沿图1的线A-A'截取的截面图。
参考图1和图2,半导体封装体100可以包括第一半导体芯片120、第二半导体芯片130以及设置在第一半导体芯片120与第二半导体芯片130之间的互连层110。互连层110可以具有彼此相对的第一表面111和第二表面112。第一半导体芯片120可以设置在互连层110的第一表面111(对应于图2中的底表面)上。第一半导体芯片120可以通过内部连接器121而连接到互连层110的第一表面111。内部连接器121可以是具有相对小尺寸的微凸块。第二半导体芯片130可以设置在互连层110的第二表面112(对应于图2中的顶表面)上。
第三半导体芯片130A可以另外设置在互连层110的第二表面112上,以与第二半导体芯片130横向间隔开。第四半导体芯片130B和第五半导体芯片130C也可以设置在互连层110的第二表面112上,以与第二半导体芯片130横向间隔开。传热板140可以设置在互连层110的与第一半导体芯片120相对的第二表面112上,以与第一半导体芯片120垂直重叠。第二半导体芯片至第五半导体芯片130、130A、130B和130C以及传热板140的全部可以被设置为与互连层110的第二表面112接触。传热板140可以具有与互连层110的第二表面112接触的底表面142。
传热板140可以设置在第二半导体芯片130与第三半导体芯片130A之间。当从图1的平面图观察时,在X轴方向上第二半导体芯片130与第三半导体芯片130A之间的第一距离D1可以被设置为比在与X轴方向垂直的Y轴方向上第二半导体芯片130与第四半导体芯片130B之间的第二距离D2大。传热板140可以设置在彼此间隔开第一距离D1的第二半导体芯片130与第三半导体芯片130A之间,并且可以延伸到彼此间隔开第一距离D1的第四半导体芯片130B与第五半导体芯片130C之间的间隔中。因此,传热板140可以实质上定位成与第一半导体芯片120的大部分垂直重叠。结果,第二半导体芯片至第五半导体芯片130、130A、130B和130C中的每一个可以具有与第一半导体芯片120的四个角区域120C中的任意一个重叠的边缘区域130E或者与第一半导体芯片120的四个角区域120C中的任意一个相邻的部分。
再次参考图2,半导体封装体100还可以包括覆盖互连层110的第二表面112的模塑层150。模塑层150可以不设置在互连层110的第一表面111上。外部连接器160代替模塑层150可以设置在互连层110的第一表面111上,以将半导体封装体100连接到外部设备。外部连接器160可以包括尺寸大于内部连接器121的焊球。模塑层150可以包括诸如环氧树脂模塑料(EMC)材料的包封剂。
第二半导体芯片至第五半导体芯片130、130A、130B和130C以及传热板140可以设置在模塑层150中。在这种情况下,模塑层150可以被形成为具有与第二半导体芯片130的顶表面131设置在相同水平面处的顶表面151。即,第二半导体芯片130的顶表面131可以被暴露在与模塑层150的顶表面151相同的水平面处。另外,传热板140的顶表面141也可以被暴露在与模塑层150的顶表面151相同的水平面处。模塑层150可以被形成为覆盖并保护第二半导体芯片130和第三半导体芯片130A的侧表面,并填充第二半导体芯片130与传热板140之间的间隙以及第三半导体芯片130A与传热板140之间的间隙。因此,传热板140可以被设置为实质上穿透模塑层150在第二半导体芯片130与第三半导体芯片130A之间的一部分。即,传热板140可以提供从互连层110的第二表面112延伸以到达模塑层150的顶表面151的水平面的热散发路径(即,热传导路径)。
图3是示出图2中所示的半导体封装体100的热传导路径的截面图。
参考图3,半导体封装体100可以安装在电路衬底170上。电路衬底170可以是印刷电路板(PCB)或包括电路图案的主板。例如,半导体封装体100可以通过外部连接器160连接到电路衬底170。第一半导体芯片120可以设置在位于第一半导体芯片120之下的电路衬底170与位于第一半导体芯片120之上的互连层110之间。另外,在平面图中,第一半导体芯片120可以由外部连接器160包围。即,第一半导体芯片120可以设置在由互连层110、电路衬底170和外部连接器160包围的内部间隔171中。
热量可以由位于内部间隔171中的第一半导体芯片120的运行来产生,并且由第一半导体芯片120的运行产生的热量可以被保持在内部间隔171中。然而,根据一个实施例,由第一半导体芯片120的运行产生的热量可以通过传热板140传输到半导体封装体100的外部区域中。传热板140可以包括导热材料,该导热材料的导热率比模塑层150的导热率高。因此,由第一半导体芯片120的运行产生的热量可以被快速地传输到半导体封装体100的外部区域中。因此,由于传热板140防止了由第一半导体芯片120的运行产生的热量累积在内部间隔171中,因此第一半导体芯片120的温度可能不会过度升高。即,传热板140可以用作将第一半导体芯片120产生的热量快速地传输到半导体封装体100的外部区域中的热传导路径。传热板140可以被形成为包括导热材料(诸如铜材料或铝材料),该导热材料的导热率比用于形成模塑层150的EMC材料的导热率高。
由于第一半导体芯片120设置在内部间隔171中,因此从互连层110的第一表面111到第一半导体芯片120的与互连层110相对的表面的第一高度H1可以比与互连层110和电路衬底170之间的距离相对应的第二高度H2小。为了使第一高度H1小于第二高度H2,第一半导体芯片120可以具有比与每个外部连接器160的高度相对应的第二高度H2小的厚度T。
图4是示出根据一个实施例的半导体封装体100S的截面图。
参考图4,半导体封装体100S可以提供如下结构:散热器180另外附接到在图3的半导体封装体100中包括的模塑层150的顶表面151。散热器180还可以附接到传热板140的顶表面141。散热器180可以散发从传热板140传输的热量。因此,由第一半导体芯片120产生的热量可以通过散热器180而更有效地散发。在这种情况下,热界面材料层181可以位于散热器180与传热板140之间的界面处。热界面材料层181可以改善传热板140与散热器180之间的热交换。
散热器180可以延伸以附接到第二半导体芯片130的顶表面131和模塑层150的顶表面151。由于第二半导体芯片130的顶表面131被模塑层150暴露,因此第二半导体芯片130与散热器180之间的热交换可以通过热界面材料层181而更容易地发生。散热器180和热界面材料层181可以延伸到第二半导体芯片130和第三半导体芯片130A上。因此,由第二半导体芯片130和第三半导体芯片130A产生的热量也可以通过散热器180来散发。
传热板140可以被设置成使得传热板140的侧表面143面对第二半导体芯片130的侧表面133。传热板140的与第二半导体芯片130相对的侧表面143A可以面对第三半导体芯片130A的侧表面133A。传热板140可以被设置成使得传热板140的侧表面143与第二半导体芯片130的侧表面133相邻。因此,由第二半导体芯片130的运行产生的热量可以通过第二半导体芯片130的侧表面133传输到传热板140,而传输到传热板140的热量可以被传导到散热器180并且可以散发到半导体封装体100的外部区域中。因此,由第三半导体芯片130A的运行产生的热量可以通过第三半导体芯片130A的侧表面133A传输到传热板140,而传输到传热板140的热量可以被传导到散热器180并且可以散发到半导体封装体100的外部区域中。这样,散热器180可以更有效地改善半导体封装体100S的冷却效率。
再次参考图2,由于半导体封装体100的第一半导体芯片120可以通过传热板140来冷却下来,因此第一半导体芯片120可以被设置在互连层110的第一表面111上。此外,由于第二半导体芯片130设置在互连层110的与第一半导体芯片120相对的第二表面112上,因此在平面图中第二半导体芯片130的至少一部分可以与第一半导体芯片120的至少一部分重叠。即,由于第二半导体芯片130的至少一部分可以层叠在第一半导体芯片120的至少一部分之上,因此当从平面图观察时,与第一半导体芯片120和第二半导体芯片130并排设置的情况相比,可以减小半导体封装体100的总宽度。
由于在平面图中第二半导体芯片130层叠在第一半导体芯片120之上,使得第二半导体芯片130的至少一部分与第一半导体芯片120的至少一部分重叠,因此可以减小设置在第一半导体芯片120与第二半导体芯片130之间的信号路由路径的长度。互连层110可以包括再分配图案114以及覆盖再分配图案114以使再分配图案114彼此绝缘的电介质层115。在这种情况下,在平面图中,第二半导体芯片130的至少一部分可以与第一半导体芯片120的至少一部分重叠。因此,可以减小用于将第一半导体芯片120和第二半导体芯片130彼此连接的再分配图案114的长度。
图5至图7是示出在图1至图4中所示的半导体封装体100和100S中的任意一个中包括的互连层110的示例的截面图。图5至图7是分别示出图2中示出的半导体封装体100的一些部分的放大视图。
图5是示出图2的部分“E1”的放大截面图。互连层110可以包括使再分配图案114与传热板140电绝缘的第一电介质层115A。互连层110还可以包括使再分配图案114彼此电绝缘的第二电介质层115B。第一电介质层115A和第二电介质层115B可以被层压以彼此接触并提供电介质层(图2中的115)。由于互连层110被配置为包括电介质层(图2的115)和再分配图案114,因此互连层110可以具有比普通PCB的厚度小的厚度。因此,可以减小半导体封装体(图2中的100)的总厚度。
第一半导体芯片120的边缘区域(实质上,角区域120C中的一个)可以与第二半导体芯片130的边缘区域130E垂直地重叠。具有用于在第一半导体芯片120与第二半导体芯片130之间的信号传输的接口结构的物理层PHY可以设置在第一半导体芯片120的角区域120C中,而具有用于在第一半导体芯片120与第二半导体芯片130之间的信号传输的接口结构的另一物理层PHY也可以设置在第二半导体芯片130的边缘区域130E中。
在一个实施例中,第一芯片焊盘135A可以设置在第二半导体芯片130的边缘区域130E上,以将第二半导体芯片130电连接到第一半导体芯片120。另外,第一内部连接器121A可以设置在第一半导体芯片120的角区域120C上,以将第一半导体芯片120电连接到第二半导体芯片130。第一内部连接器121A可以对应于内部连接器121中的一些。
第一再分配图案114A可以设置在互连层110中,使得第一再分配图案114A的第一端部电连接到第二半导体芯片130的第一芯片焊盘135A,而第一再分配图案114A的第二端部电连接到第一内部连接器121A。第一再分配图案114A可以对应于再分配图案114中的一些,并且可以设置在第二半导体芯片130的边缘区域130E与第一半导体芯片120的角区域120C之间。
第一再分配图案114A可以用作垂直信号路径,所述垂直信号路径将第二半导体芯片130的边缘区域130E实质上垂直连接到第一半导体芯片120的角区域120C。在平面图中,第一再分配图案114A可以被设置为与第二半导体芯片130的边缘区域130E和第一半导体芯片120的角区域120C重叠。因此,根据一个实施例,可以减小第一再分配图案114A的长度,并且还可以减小第一半导体芯片120与第二半导体芯片130之间的信号路径的路由长度。
第一电介质层115A可以被形成为具有用于使第一芯片焊盘135A暴露的第一开口116A,以便将第一再分配图案114A的第一端部连接到第一芯片焊盘135A。第一再分配图案114A的第一端部可以填充第一开口116A以连接到第一芯片焊盘135A。第二电介质层115B可以被形成为具有用于使第一再分配图案114A的第二端部暴露的第二开口116B,以便将第一再分配图案114A的第二端部连接到第一内部连接器121A。第一内部连接器121A可以延伸为填充第二开口116B以连接到第一再分配图案114A。
图6是示出图2的部分“E2”的放大截面图。在平面图中,与再分配图案114中的一个相对应的第二再分配图案114B可以从与第二半导体芯片130重叠的区域延伸到第二半导体芯片130的外部区域中。在平面图中,第二再分配图案114B可以延伸到与模塑层150重叠的区域中。因此,在平面图中,与外部连接器160中的一个相对应的第一外部连接器160A可以连接到第二再分配图案114B,并且可以设置为与模塑层150的位于第二半导体芯片130的外部区域处的一部分重叠。结果,第一外部连接器160A可以是将第二半导体芯片130电连接到外部设备的连接器。
第二再分配图案114B可以延伸到第二半导体芯片130的外部区域中,以将第一外部连接器160A连接到与第二半导体芯片130的芯片焊盘中的一个相对应的第二芯片焊盘135B。因为第二再分配图案114B延伸到第二半导体芯片130的外部区域中,所以第一电介质层115A也可以延伸以与模塑层150的底表面152接触。
第二再分配图案114B可以被设置在互连层110中,使得第二再分配图案114B的第一端部电连接到第二半导体芯片130的第二芯片焊盘135B,而第二再分配图案114B的第二端部电连接到第一外部连接器160A。第一电介质层115A可以被形成为具有用于使第二芯片焊盘135B暴露的第三开口116C,以将第二再分配图案114B的第一端部连接到第二芯片焊盘135B。第二再分配图案114B的第一端部可以填充第三开口116C以连接到第二芯片焊盘135B。第二电介质层115B可以被形成为具有用于使第二再分配图案114B的第二端部暴露的第四开口116D,以便将第二再分配图案114B的第二端部连接到第一外部连接器160A。第一外部连接器160A可以延伸为填充第四开口116D以连接到第二再分配图案114B。
图7是示出图2的部分“E3”的放大截面图。在平面图中,与再分配图案114中的一个相对应的第三再分配图案114C可以从与第三半导体芯片130A重叠的区域延伸到第三半导体芯片130A的外部区域中。因此,与外部连接器160中的一个相对应的第二外部连接器160B可以连接到第三再分配图案114C,并且可以被设置为与第三半导体芯片130A重叠。在一个实施例中,如图2中所示,连接到第三再分配图案114C的另一个外部连接器160可以被设置为与模塑层150重叠。第二外部连接器160B可以是将第一半导体芯片120电连接到外部设备的连接器。
第三再分配图案114C可以延伸到第一半导体芯片120的外部区域中,以将第二外部连接器160B连接到第二内部连接器121B,该第二内部连接器121B与连接到第一半导体芯片120的内部连接器121中的一个相对应。由于第三再分配图案114C延伸到第一半导体芯片120的外部区域中,因此第一电介质层115A也可以延伸以与第三半导体芯片130A重叠。
第三再分配图案114C可以被设置在互连层110中,使得第三再分配图案114C的第一端部电连接到第二内部连接器121B,而第三再分配图案114C的第二端部电连接到第二外部连接器160B。第二电介质层115B可以被形成为具有用于使第三再分配图案114C的第一端部暴露的第五开口116E,以便将第三再分配图案114C的第一端部连接到第二内部连接器121B。第二内部连接器121B可以延伸为填充第五开口116E以连接到第三再分配图案114C的第一端部。第二电介质层115B可以被形成为具有用于使第三再分配图案114C的第二端部暴露的第六开口116F,以便将第三再分配图案114C的第二端部连接到第二外部连接器160B。第二外部连接器160B可以延伸为填充第六开口116F以连接到第三再分配图案114C的第二端部。
这样,再分配图案114可以包括具有不同形状的第一再分配图案至第三再分配图案114A、114B和114C。
图8是示出图2中的第二半导体芯片130的截面图。
参考图2和图8,第二半导体芯片130可以包括垂直层叠的多个半导体裸片。例如,第二半导体芯片130可以包括基底逻辑半导体裸片136以及顺序层叠在基底逻辑半导体裸片136上的第一核心半导体裸片至第四核心半导体裸片137A、137B、137C和137D。包括基底逻辑半导体裸片136以及第一核心半导体裸片至第四核心半导体裸片137A、137B、137C和137D的第二半导体芯片130可以用作诸如高带宽存储(HBM)器件的高性能存储器件。第三半导体芯片至第五半导体芯片(图1中的130A、130B和130C)中的每一个半导体芯片可以被设置为具有与第二半导体芯片130实质上相同的配置和功能。
基底逻辑半导体裸片136以及第一核心半导体裸片至第四核心半导体裸片137A、137B、137C和137D可以通过裸片间(inter-die)连接器138B而彼此电连接。裸片间连接器138B可以包括微凸块。第一核心半导体裸片至第三核心半导体裸片137A、137B和137C中的每一个可以包括穿透其主体的第一穿通硅通孔(TSV)138A,并且第一核心半导体裸片至第三核心半导体裸片137A、137B和137C的第一穿通硅通孔(TSV)138A可以通过裸片间连接器138B垂直地连接以构成输入/输出(I/O)路径。在第一核心半导体裸片至第四核心半导体裸片137A、137B、137C和137D之中的与最顶部的半导体裸片相对应的第四核心半导体裸片137D中可以不包括穿通硅通孔(TSV)。然而,在一些其他实施例中,第四核心半导体裸片137D也可以包括穿通硅通孔(TSV)。
第一核心半导体裸片至第四核心半导体裸片137A、137B、137C和137D可以包括实质上相同的集成电路以执行相同的操作。第一核心半导体裸片至第四核心半导体裸片137A、137B、137C和137D可以包括DRAM单元以提供数据存储体(data bank)。基底逻辑半导体裸片136可以控制第一核心半导体裸片至第四核心半导体裸片137A、137B、137C和137D的运行。
基底逻辑半导体裸片136可以包括第二穿通硅通孔(TSV)136A,第二TSV 136A通过裸片间连接器138B而耦接到第一核心半导体裸片137A的第一TSV 138A。基底逻辑半导体裸片136可以包括将第二半导体芯片130电连接到互连层(图2的110)的芯片焊盘135。芯片焊盘135可以包括图5中所示的第一芯片焊盘135A和图6中所示的第二芯片焊盘135B。基底逻辑半导体裸片136还可以包括将第二TSV 136A连接到芯片焊盘135的内部互连线136B。
第二半导体芯片130以及第三半导体芯片至第五半导体芯片(图1的130A、130B和130C)可以提供存储器件,并且第一半导体芯片(图2的120)可以是诸如中央处理单元(CPU)或图形处理单元(GPU)的处理器。在这种情况下,图1的半导体封装体100或图4的半导体封装体100S可以对应于片上系统(SoC)。因此,第一半导体芯片120和第二半导体芯片130可以以高速与宽带宽来彼此传输数据。
第二半导体芯片130还可以包括内部保护层139,该内部保护层139覆盖并保护基底逻辑半导体裸片136以及第一核心半导体裸片至第四核心半导体裸片137A、137B、137C和137D。内部保护层139可以被形成为包括诸如EMC材料或底部填充材料的包封剂。内部保护层139可以被形成为使基底逻辑半导体裸片136的侧表面136S暴露并且覆盖第一核心半导体裸片至第四核心半导体裸片137A、137B、137C和137D的侧表面。内部保护层139可以被形成为使第四核心半导体裸片137D的顶表面(即,第二半导体芯片130的顶表面131)暴露。
图9至图14是示出根据一个实施例的制造半导体封装体的方法的截面图。
参考图9,第二半导体芯片130、传热板140和第三半导体芯片130A可以设置在第一载体191上。传热板140可以设置在彼此间隔开的第二半导体芯片130与第三半导体芯片130A之间。在这种情况下,如图1中所示,第四半导体芯片和第五半导体芯片(图1的130B和130C)也可以设置为与第二半导体芯片130和第三半导体芯片130A间隔开。第二半导体芯片130可以安装在第一载体191上,使得在第二半导体芯片130的底表面132上的芯片焊盘135面对第一载体191的表面。因此,第二半导体芯片130的顶表面131可以位于第一载体191的相对侧。
第二半导体芯片130、传热板140和第三半导体芯片130A可以使用粘合层而暂时附接到第一载体191的表面。在后续工艺中,第一载体191可以用作支撑件,用于支撑第二半导体芯片130、传热板140和第三半导体芯片130A。第一载体191可以具有晶片形式,使得晶片级封装技术应用于第一载体191。
参考图10,初始模塑层159可以形成在第一载体191上,以覆盖第二半导体芯片130、传热板140和第三半导体芯片130A。初始模塑层159可以固定第二半导体芯片130、传热板140和第三半导体芯片130A的相对位置。初始模塑层159可以由包封层来形成,以保护第二半导体芯片130、传热板140和第三半导体芯片130A。
平坦化工艺可以应用于初始模塑层159的顶表面以去除初始模塑层159的上部。可以使用诸如研磨工艺的去除工艺来执行平坦化工艺。初始模塑层159的上部可以通过平坦化工艺来选择性地去除,以提供具有减小的厚度和平坦化表面的模塑层150。可以执行平坦化工艺以使传热板140的顶表面141暴露。此外,在执行平坦化工艺之后,可以使第二半导体芯片130的顶表面131暴露,并且也可以使第三半导体芯片130A的顶表面131A暴露。
模塑层150可以将第二半导体芯片130、传热板140和第三半导体芯片130A固定到第一载体191,以形成重建晶片(reconstruction wafer)100W。重建晶片100W可以被配置为包括填充第二半导体芯片130、传热板140和第三半导体芯片130A之间的间隙的模塑层150。重建晶片100W可以具有要由处理半导体晶片的装置处置的晶片形状。即,重建晶片100W可以是具有彼此相对的第一表面101W和第二表面102W的晶片形层。因此,可以使用各种半导体工艺在重建晶片100W上形成再分配层和凸块。
在形成重建晶片100W之后,第一载体191可以与重建晶片100W脱离。
参考图11,可以翻转重建晶片100W,使得重建晶片100W的第一表面101W位于比重建晶片100W的第二表面102W高的水平面处。然后第二载体193可以附接到重建晶片100W的第二表面102W以支撑重建晶片100W。在一些其他实施例中,可以省略用于将第二载体193附接到重建晶片100W的工艺。模塑层150的与第二载体193相对的底表面152可以被暴露在重建晶片100W的第一表面101W处。另外,第二半导体芯片130的与第二载体193相对的底表面132可以被暴露在重建晶片100W的第一表面101W处。此外,传热板140的与第二载体193相对的底表面142也可以被暴露在重建晶片100W的第一表面101W处。而且,第三半导体芯片130A的与第二载体193相对的底表面132A可以被暴露在重建晶片100W的第一表面101W处。
参考图12,互连层110可以形成在重建晶片100W的第一表面101W上。互连层110可以被设置为包括电介质层115和嵌入电介质层115中的再分配图案114。互连层110可以形成在重建晶片100W上,使得互连层110的第二表面112与重建晶片100W的第一表面101W接触,并且互连层110的第一表面111被暴露。电介质层115中的一些再分配图案114可以被形成为电连接到第二半导体芯片130。
参考图13,第一半导体芯片120可以使用内部连接器121安装在互连层110的第一表面111上。在这种情况下,内部连接器121可以与互连层110接触以电连接到一些再分配图案114。外部连接器160可以附接到互连层110的第一表面111。外部连接器160可以附接到互连层110,以电连接到互连层110中的一些再分配图案114。
在第二载体193在先前工艺中附接到重建晶片100W的情况下,第二载体193可以在外部连接器160附接到互连层110之后与重建晶片100W脱离。
参考图14,可以使用裸片切割技术来执行分离工艺以将半导体封装体100彼此分离。如图4中所示,散热器(图4的180)可以使用热界面材料层(图4的181)另外附接到每个半导体封装体100。
根据上述实施例,提供了半导体封装体,每个半导体封装体被配置为包括在互连层上面和下面三维地层叠的多个半导体芯片。在平面图中,互连层可以被配置为包括延伸到半导体芯片的外部区域中的再分配图案。由于半导体芯片中的一个被设置为与其余的半导体芯片垂直地且部分地重叠,因此可以减小在半导体芯片中包括的物理层之间的路由路径的长度,并且也可以减小每个半导体封装体的平面面积。
每个半导体封装体还可以包括与多个半导体芯片中的任何一个重叠的传热板。传热板可以穿透半导体封装体的模塑层,以提供从互连层延伸以到达半导体封装体的顶表面的热传导路径。因此,传热板可以提高半导体封装体的冷却效率。
图15是示出包括采用根据实施例的至少一个半导体封装体的存储卡7800的电子系统的框图。存储卡7800可以包括诸如非易失性存储器件的存储器7810和存储器控制器7820。存储器7810和存储器控制器7820可以储存数据或读出所储存的数据。存储器7810和存储器控制器7820中的至少一个可以包括根据实施例的至少一个半导体封装体。
存储器7810可以包括应用本公开的实施例的技术的非易失性存储器件。存储器控制器7820可以控制存储器7810,使得其响应于来自主机7830的读取/写入请求而读出所储存的数据或储存数据。
图16是示出包括根据实施例的至少一个半导体封装体的电子系统8710的框图。电子系统8710可以包括控制器8711、输入/输出单元8712和存储器8713。控制器8711、输入/输出单元8712和存储器8713可以通过总线8715而彼此耦接,该总线8715提供经由其移动数据的路径。
在一个实施例中,控制器8711可以包括微处理器、数字信号处理器、微控制器和/或能够执行与这些组件相同功能的逻辑设备中的一个或更多个。控制器8711或存储器8713可以包括根据本公开实施例的至少一个半导体封装体。输入/输出单元8712可以包括选自小键盘、键盘、显示设备、触摸屏等中的至少一个。存储器8713是用于储存数据的设备。存储器8713可以储存要由控制器8711执行的数据和/或命令等。
存储器8713可以包括诸如DRAM的易失性存储器件和/或诸如快闪存储器的非易失性存储器件。例如,快闪存储器可以被安装到诸如移动终端或台式计算机的信息处理系统。快闪存储器可以构成固态盘(SSD)。在这种情况下,电子系统8710可以将大量数据稳定地储存在快闪存储系统中。
电子系统8710还可以包括被配置为向通信网络传输数据和从通信网络接收数据的接口8714。接口8714可以是有线型或无线型。例如,接口8714可以包括天线或者有线或无线收发器。
电子系统8710可以被实现为移动系统、个人计算机、工业计算机或执行各种功能的逻辑系统。例如,移动系统可以是个人数字助理(PDA)、便携式电脑、平板电脑、移动电话、智能电话、无线电话、膝上型电脑、存储卡、数字音乐系统和信息传输/接收系统中的任意一种。
如果电子系统8710是能够执行无线通信的设备,则电子系统8710可以用于具有以下技术的通信系统中:CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美数字蜂窝)、E-TDMA(增强时分多址)、WCDMA(宽带码分多址)、CDMA2000、LTE(长期演进)或Wibro(无线宽带互联网)。
已经出于说明性目的公开了本公开的实施例。本领域技术人员将理解,在不脱离本公开和所附权利要求的范围和精神的情况下,可以进行各种修改、添加和替换。
Claims (20)
1.一种半导体封装体,包括:
第一半导体芯片,其设置在互连层的第一表面上;
第二半导体芯片和第三半导体芯片,所述第二半导体芯片和所述第三半导体芯片彼此间隔开并且设置在所述互连层的第二表面上;以及
传热板,其设置在所述第二半导体芯片与所述第三半导体芯片之间,与所述互连层的第二表面接触并且与所述第一半导体芯片重叠,
其中,所述传热板提供热散发路径。
2.根据权利要求1所述的半导体封装体,
其中,所述传热板具有底表面,所述底表面与所述互连层的第二表面接触;以及
其中,所述传热板具有面对所述第二半导体芯片的侧表面的一个侧表面和面对所述第三半导体芯片的侧表面的另一个侧表面。
3.根据权利要求1所述的半导体封装体,还包括模塑层,所述模塑层覆盖所述互连层的第二表面以及所述第二半导体芯片和所述第三半导体芯片的侧表面,并且填充所述第二半导体芯片与所述传热板之间的间隙。
4.根据权利要求3所述的半导体封装体,
其中,所述传热板被设置为穿透所述模塑层;以及
其中,所述模塑层将所述传热板的顶表面暴露。
5.根据权利要求4所述的半导体封装体,其中,所述模塑层被设置为使所述第二半导体芯片的顶表面暴露。
6.根据权利要求1所述的半导体封装体,还包括附接到所述传热板的散热器。
7.根据权利要求6所述的半导体封装体,其中,所述散热器延伸至与所述第二半导体芯片的顶表面接触。
8.根据权利要求6所述的半导体封装体,还包括设置在所述散热器与所述传热板之间的热界面材料层。
9.根据权利要求3所述的半导体封装体,其中,所述互连层包括:
再分配图案,其从所述互连层的与所述第二半导体芯片重叠的一部分延伸到所述互连层的与所述模塑层重叠的另一部分;以及
电介质层,其使所述再分配图案彼此绝缘。
10.根据权利要求1所述的半导体封装体,其中,所述第二半导体芯片具有与所述第一半导体芯片的角区域重叠的边缘区域。
11.根据权利要求10所述的半导体封装体,其中,所述互连层包括第一再分配图案,所述第一再分配图案与所述第一半导体芯片的所述角区域和所述第二半导体芯片的所述边缘区域两者重叠,并且所述第一再分配图案将所述第一半导体芯片垂直地电连接到所述第二半导体芯片。
12.根据权利要求10所述的半导体封装体,其中,具有用于在所述第一半导体芯片与所述第二半导体芯片之间的信号传输的接口结构的物理层设置在所述第一半导体芯片的角区域中,而具有用于在所述第一半导体芯片与所述第二半导体芯片之间的信号传输的接口结构的另一个物理层设置在所述第二半导体芯片的边缘区域中。
13.根据权利要求1所述的半导体封装体,还包括附接到所述互连层的第一表面的外部连接器。
14.根据权利要求13所述的半导体封装体,其中,所述互连层包括第二再分配图案,所述第二再分配图案将所述外部连接器中的一个外部连接器电连接到所述第二半导体芯片。
15.根据权利要求14所述的半导体封装体,其中,所述第二再分配图案延伸使得所述第二再分配图案的第一端部连接到所述第二半导体芯片的芯片焊盘,而所述第二再分配图案的第二端部连接到所述外部连接器中的一个外部连接器。
16.根据权利要求14所述的半导体封装体,
其中,所述互连层包括具有第一开口和第二开口的电介质层,所述第一开口使所述第二半导体芯片的芯片焊盘暴露,而所述第二开口使所述第二再分配图案的第二端部暴露;以及
其中,所述第一开口用所述第二再分配图案的第一端部来填充,而所述第二开口用所述一个外部连接器来填充。
17.根据权利要求12所述的半导体封装体,其中,所述互连层还包括第三再分配图案,所述第三再分配图案将所述第二半导体芯片电连接到外部连接器中的一个外部连接器。
18.根据权利要求12所述的半导体封装体,其中,外部连接器被设置为包围所述第一半导体芯片的侧表面。
19.根据权利要求12所述的半导体封装体,其中,从所述互连层的第一表面到所述第一半导体芯片的与所述互连层相对的表面的高度比附接到所述互连层的第一表面的外部连接器的高度小。
20.一种半导体封装体,包括:
第一半导体芯片,其设置在互连层的第一表面上;
第二半导体芯片,其设置在所述互连层的第二表面上,使得所述第一半导体芯片的四个角区域分别与所述第二半导体芯片的边缘区域重叠;以及
传热板,其设置在所述第二半导体芯片之间以与所述互连层的第二表面接触并且与所述第一半导体芯片重叠,
其中,所述传热板提供热散发路径。
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