CN109791948A - 带有背侧本体接触部的深沟槽有源器件 - Google Patents

带有背侧本体接触部的深沟槽有源器件 Download PDF

Info

Publication number
CN109791948A
CN109791948A CN201780054488.8A CN201780054488A CN109791948A CN 109791948 A CN109791948 A CN 109791948A CN 201780054488 A CN201780054488 A CN 201780054488A CN 109791948 A CN109791948 A CN 109791948A
Authority
CN
China
Prior art keywords
backside
layer
gate
integrated circuit
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201780054488.8A
Other languages
English (en)
Chinese (zh)
Inventor
S·格科特佩里
S·法内利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN109791948A publication Critical patent/CN109791948A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223Capacitor integral with wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/12Supports; Mounting means
    • H01Q1/22Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/24Supports; Mounting means by structural association with other equipment or articles with receiving set
    • H01Q1/241Supports; Mounting means by structural association with other equipment or articles with receiving set used in mobile communications, e.g. GSM
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/36Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/62Fin field-effect transistors [FinFET]
    • H10D30/6211Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6704Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H10D30/6711Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6616Vertical connections, e.g. vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6661High-frequency adaptations for passive devices
    • H01L2223/6677High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
CN201780054488.8A 2016-09-06 2017-08-03 带有背侧本体接触部的深沟槽有源器件 Pending CN109791948A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/257,823 US9812580B1 (en) 2016-09-06 2016-09-06 Deep trench active device with backside body contact
US15/257,823 2016-09-06
PCT/US2017/045349 WO2018048529A1 (en) 2016-09-06 2017-08-03 Deep trench active device with backside body contact

Publications (1)

Publication Number Publication Date
CN109791948A true CN109791948A (zh) 2019-05-21

Family

ID=59684050

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201780054488.8A Pending CN109791948A (zh) 2016-09-06 2017-08-03 带有背侧本体接触部的深沟槽有源器件

Country Status (7)

Country Link
US (1) US9812580B1 (enExample)
EP (1) EP3510636A1 (enExample)
JP (1) JP2019530218A (enExample)
KR (1) KR20190045909A (enExample)
CN (1) CN109791948A (enExample)
BR (1) BR112019003900A2 (enExample)
WO (1) WO2018048529A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110504240B (zh) * 2018-05-16 2021-08-13 联华电子股份有限公司 半导体元件及其制造方法
CN109524355B (zh) * 2018-10-30 2020-11-10 上海集成电路研发中心有限公司 一种半导体器件的结构和形成方法
CN109545785B (zh) * 2018-10-31 2023-01-31 上海集成电路研发中心有限公司 一种半导体器件结构和制备方法
CN109545802B (zh) * 2018-12-14 2021-01-12 上海微阱电子科技有限公司 一种绝缘体上半导体器件结构和形成方法
CN109616472B (zh) * 2018-12-14 2022-11-15 上海微阱电子科技有限公司 一种半导体器件结构和形成方法
CN109891585B (zh) * 2019-01-30 2020-03-27 长江存储科技有限责任公司 具有垂直扩散板的电容器结构
CN109923666B (zh) * 2019-01-30 2020-05-26 长江存储科技有限责任公司 具有垂直扩散板的电容器结构
KR102642279B1 (ko) * 2019-02-18 2024-02-28 양쯔 메모리 테크놀로지스 씨오., 엘티디. 새로운 커패시터 구조 및 이를 형성하는 방법
TWI741935B (zh) 2020-04-28 2021-10-01 台灣積體電路製造股份有限公司 半導體元件與其製作方法
DE102020122151A1 (de) * 2020-04-28 2021-10-28 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und verfahren
US11349004B2 (en) * 2020-04-28 2022-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Backside vias in semiconductor device
US11355410B2 (en) * 2020-04-28 2022-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Thermal dissipation in semiconductor devices
US11251308B2 (en) 2020-04-28 2022-02-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
DE102020131611B4 (de) 2020-05-28 2025-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung mit luftspalten und verfahren zu deren herstellung
CN120280431B (zh) * 2025-06-04 2025-09-30 长飞先进半导体(武汉)有限公司 半导体器件及制作方法、功率模块、功率转换电路和车辆

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110244302A1 (en) * 2010-03-30 2011-10-06 Medtronic, Inc. High density capacitor array patterns
US20120007180A1 (en) * 2010-07-06 2012-01-12 Globalfoundries Singapore PTE, LTD. FinFET with novel body contact for multiple Vt applications
US20160172527A1 (en) * 2012-12-03 2016-06-16 Sandia Corporation Photodetector with Interdigitated Nanoelectrode Grating Antenna
US20160254231A1 (en) * 2013-03-27 2016-09-01 Qualcomm Incorporated Methods of Making Integrated Circuit Assembly with Faraday Cage

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2948018B2 (ja) * 1992-03-17 1999-09-13 三菱電機株式会社 半導体装置およびその製造方法
US5889298A (en) 1993-04-30 1999-03-30 Texas Instruments Incorporated Vertical JFET field effect transistor
JP3884266B2 (ja) * 2001-02-19 2007-02-21 株式会社東芝 半導体メモリ装置及びその製造方法
US6838722B2 (en) 2002-03-22 2005-01-04 Siliconix Incorporated Structures of and methods of fabricating trench-gated MIS devices
JP2003309182A (ja) * 2002-04-17 2003-10-31 Hitachi Ltd 半導体装置の製造方法及び半導体装置
US6861701B2 (en) 2003-03-05 2005-03-01 Advanced Analogic Technologies, Inc. Trench power MOSFET with planarized gate bus
JP4869546B2 (ja) * 2003-05-23 2012-02-08 ルネサスエレクトロニクス株式会社 半導体装置
JP2005353657A (ja) * 2004-06-08 2005-12-22 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
DE102005030585B4 (de) * 2005-06-30 2011-07-28 Globalfoundries Inc. Halbleiterbauelement mit einem vertikalen Entkopplungskondensator und Verfahren zu seiner Herstellung
JP2009088241A (ja) * 2007-09-28 2009-04-23 Renesas Technology Corp 半導体装置およびその製造方法
JP5487625B2 (ja) * 2009-01-22 2014-05-07 ソニー株式会社 半導体装置
US9159825B2 (en) 2010-10-12 2015-10-13 Silanna Semiconductor U.S.A., Inc. Double-sided vertical semiconductor device with thinned substrate
US9496255B2 (en) * 2011-11-16 2016-11-15 Qualcomm Incorporated Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
US8735993B2 (en) * 2012-01-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET body contact and method of making same
US9148194B2 (en) * 2012-07-07 2015-09-29 Skyworks Solutions, Inc. Radio-frequency switch system having improved intermodulation distortion performance
US8748245B1 (en) 2013-03-27 2014-06-10 Io Semiconductor, Inc. Semiconductor-on-insulator integrated circuit with interconnect below the insulator

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110244302A1 (en) * 2010-03-30 2011-10-06 Medtronic, Inc. High density capacitor array patterns
US20120007180A1 (en) * 2010-07-06 2012-01-12 Globalfoundries Singapore PTE, LTD. FinFET with novel body contact for multiple Vt applications
US20160172527A1 (en) * 2012-12-03 2016-06-16 Sandia Corporation Photodetector with Interdigitated Nanoelectrode Grating Antenna
US20160254231A1 (en) * 2013-03-27 2016-09-01 Qualcomm Incorporated Methods of Making Integrated Circuit Assembly with Faraday Cage

Also Published As

Publication number Publication date
WO2018048529A1 (en) 2018-03-15
KR20190045909A (ko) 2019-05-03
JP2019530218A (ja) 2019-10-17
US9812580B1 (en) 2017-11-07
BR112019003900A2 (pt) 2019-05-21
EP3510636A1 (en) 2019-07-17

Similar Documents

Publication Publication Date Title
CN109791948A (zh) 带有背侧本体接触部的深沟槽有源器件
CN110088891B (zh) 利用双面处理的逻辑电路块布局
CN109314097B (zh) 用于反向偏置开关晶体管的方法和装置
CN109643691B (zh) 背面半导体生长
EP3443592B1 (en) Switch device performance improvement through multisided biased shielding
US9917062B1 (en) Self-aligned transistors for dual-side processing
US10748934B2 (en) Silicon on insulator with multiple semiconductor thicknesses using layer transfer
US10043752B2 (en) Substrate contact using dual sided silicidation
US10290579B2 (en) Utilization of backside silicidation to form dual side contacted capacitor
HK40009868A (en) Logic circuit block layouts with dual-sided processing
HK40009868B (en) Logic circuit block layouts with dual-sided processing

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20190521

WD01 Invention patent application deemed withdrawn after publication