JP2019530218A - 裏面ボディ接点を有するディープトレンチ能動デバイス - Google Patents

裏面ボディ接点を有するディープトレンチ能動デバイス Download PDF

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JP2019530218A
JP2019530218A JP2019512208A JP2019512208A JP2019530218A JP 2019530218 A JP2019530218 A JP 2019530218A JP 2019512208 A JP2019512208 A JP 2019512208A JP 2019512208 A JP2019512208 A JP 2019512208A JP 2019530218 A JP2019530218 A JP 2019530218A
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Prior art keywords
gate
integrated circuit
layer
backside
coupled
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Pending
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JP2019512208A
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Japanese (ja)
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JP2019530218A5 (enExample
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シナン・ゴクテペリ
スティーヴ・ファネリ
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/24—Supports; Mounting means by structural association with other equipment or articles with receiving set
    • H01Q1/241—Supports; Mounting means by structural association with other equipment or articles with receiving set used in mobile communications, e.g. GSM
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6211—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H10D30/6711—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
JP2019512208A 2016-09-06 2017-08-03 裏面ボディ接点を有するディープトレンチ能動デバイス Pending JP2019530218A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/257,823 US9812580B1 (en) 2016-09-06 2016-09-06 Deep trench active device with backside body contact
US15/257,823 2016-09-06
PCT/US2017/045349 WO2018048529A1 (en) 2016-09-06 2017-08-03 Deep trench active device with backside body contact

Publications (2)

Publication Number Publication Date
JP2019530218A true JP2019530218A (ja) 2019-10-17
JP2019530218A5 JP2019530218A5 (enExample) 2020-08-20

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ID=59684050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019512208A Pending JP2019530218A (ja) 2016-09-06 2017-08-03 裏面ボディ接点を有するディープトレンチ能動デバイス

Country Status (7)

Country Link
US (1) US9812580B1 (enExample)
EP (1) EP3510636A1 (enExample)
JP (1) JP2019530218A (enExample)
KR (1) KR20190045909A (enExample)
CN (1) CN109791948A (enExample)
BR (1) BR112019003900A2 (enExample)
WO (1) WO2018048529A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210133840A (ko) * 2020-04-28 2021-11-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 반도체 디바이스의 방열
US11942390B2 (en) 2020-04-28 2024-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Thermal dissipation in semiconductor devices

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110504240B (zh) * 2018-05-16 2021-08-13 联华电子股份有限公司 半导体元件及其制造方法
CN109524355B (zh) * 2018-10-30 2020-11-10 上海集成电路研发中心有限公司 一种半导体器件的结构和形成方法
CN109545785B (zh) * 2018-10-31 2023-01-31 上海集成电路研发中心有限公司 一种半导体器件结构和制备方法
CN109616472B (zh) * 2018-12-14 2022-11-15 上海微阱电子科技有限公司 一种半导体器件结构和形成方法
CN109545802B (zh) * 2018-12-14 2021-01-12 上海微阱电子科技有限公司 一种绝缘体上半导体器件结构和形成方法
CN109923666B (zh) * 2019-01-30 2020-05-26 长江存储科技有限责任公司 具有垂直扩散板的电容器结构
EP3850665B1 (en) * 2019-01-30 2023-11-15 Yangtze Memory Technologies Co., Ltd. Capacitor structure having vertical diffusion plates
EP3853896B1 (en) * 2019-02-18 2024-10-02 Yangtze Memory Technologies Co., Ltd. Method of forming a novel capacitor structure
DE102020122151A1 (de) * 2020-04-28 2021-10-28 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und verfahren
US11251308B2 (en) 2020-04-28 2022-02-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11349004B2 (en) * 2020-04-28 2022-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Backside vias in semiconductor device
DE102020131611B4 (de) * 2020-05-28 2025-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung mit luftspalten und verfahren zu deren herstellung
CN120280431B (zh) * 2025-06-04 2025-09-30 长飞先进半导体(武汉)有限公司 半导体器件及制作方法、功率模块、功率转换电路和车辆

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267563A (ja) * 1992-03-17 1993-10-15 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2003309182A (ja) * 2002-04-17 2003-10-31 Hitachi Ltd 半導体装置の製造方法及び半導体装置
JP2004349537A (ja) * 2003-05-23 2004-12-09 Renesas Technology Corp 半導体装置
JP2005353657A (ja) * 2004-06-08 2005-12-22 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2009500824A (ja) * 2005-06-30 2009-01-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 垂直デカップリングコンデンサを含む半導体デバイス
JP2009088241A (ja) * 2007-09-28 2009-04-23 Renesas Technology Corp 半導体装置およびその製造方法
JP2010171166A (ja) * 2009-01-22 2010-08-05 Sony Corp 半導体装置およびその製造方法
JP2015503228A (ja) * 2011-11-16 2015-01-29 クアルコム，インコーポレイテッド 絶縁層および第２の層を有する積層されたチップセットおよびそれを形成する方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5889298A (en) 1993-04-30 1999-03-30 Texas Instruments Incorporated Vertical JFET field effect transistor
JP3884266B2 (ja) * 2001-02-19 2007-02-21 株式会社東芝 半導体メモリ装置及びその製造方法
US6838722B2 (en) 2002-03-22 2005-01-04 Siliconix Incorporated Structures of and methods of fabricating trench-gated MIS devices
US6861701B2 (en) 2003-03-05 2005-03-01 Advanced Analogic Technologies, Inc. Trench power MOSFET with planarized gate bus
US8395880B2 (en) * 2010-03-30 2013-03-12 Medtronic, Inc. High density capacitor array patterns
US8735984B2 (en) * 2010-07-06 2014-05-27 Globalfoundries Singapore PTE, LTD. FinFET with novel body contact for multiple Vt applications
US9159825B2 (en) 2010-10-12 2015-10-13 Silanna Semiconductor U.S.A., Inc. Double-sided vertical semiconductor device with thinned substrate
US8735993B2 (en) * 2012-01-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET body contact and method of making same
US9148194B2 (en) * 2012-07-07 2015-09-29 Skyworks Solutions, Inc. Radio-frequency switch system having improved intermodulation distortion performance
US20160172527A1 (en) * 2012-12-03 2016-06-16 Sandia Corporation Photodetector with Interdigitated Nanoelectrode Grating Antenna
US9478507B2 (en) * 2013-03-27 2016-10-25 Qualcomm Incorporated Integrated circuit assembly with faraday cage
US8748245B1 (en) 2013-03-27 2014-06-10 Io Semiconductor, Inc. Semiconductor-on-insulator integrated circuit with interconnect below the insulator

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267563A (ja) * 1992-03-17 1993-10-15 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2003309182A (ja) * 2002-04-17 2003-10-31 Hitachi Ltd 半導体装置の製造方法及び半導体装置
JP2004349537A (ja) * 2003-05-23 2004-12-09 Renesas Technology Corp 半導体装置
JP2005353657A (ja) * 2004-06-08 2005-12-22 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2009500824A (ja) * 2005-06-30 2009-01-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 垂直デカップリングコンデンサを含む半導体デバイス
JP2009088241A (ja) * 2007-09-28 2009-04-23 Renesas Technology Corp 半導体装置およびその製造方法
JP2010171166A (ja) * 2009-01-22 2010-08-05 Sony Corp 半導体装置およびその製造方法
JP2015503228A (ja) * 2011-11-16 2015-01-29 クアルコム，インコーポレイテッド 絶縁層および第２の層を有する積層されたチップセットおよびそれを形成する方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210133840A (ko) * 2020-04-28 2021-11-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 반도체 디바이스의 방열
KR102455200B1 (ko) 2020-04-28 2022-10-14 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 반도체 디바이스의 방열
US11942390B2 (en) 2020-04-28 2024-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Thermal dissipation in semiconductor devices
US12451401B2 (en) 2020-04-28 2025-10-21 Taiwan Semiconductor Manufacturing Co., Ltd. Thermal dissipation in semiconductor devices

Also Published As

Publication number Publication date
KR20190045909A (ko) 2019-05-03
US9812580B1 (en) 2017-11-07
CN109791948A (zh) 2019-05-21
BR112019003900A2 (pt) 2019-05-21
EP3510636A1 (en) 2019-07-17
WO2018048529A1 (en) 2018-03-15

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