BR112019003900A2 - dispositivo ativo de vala profunda com contato da parte posterior do corpo - Google Patents

dispositivo ativo de vala profunda com contato da parte posterior do corpo

Info

Publication number
BR112019003900A2
BR112019003900A2 BR112019003900-7A BR112019003900A BR112019003900A2 BR 112019003900 A2 BR112019003900 A2 BR 112019003900A2 BR 112019003900 A BR112019003900 A BR 112019003900A BR 112019003900 A2 BR112019003900 A2 BR 112019003900A2
Authority
BR
Brazil
Prior art keywords
active device
body contact
deep trench
integrated circuit
trench active
Prior art date
Application number
BR112019003900-7A
Other languages
English (en)
Portuguese (pt)
Inventor
Goktepeli Sinan
Fanelli Steve
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of BR112019003900A2 publication Critical patent/BR112019003900A2/pt

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223Capacitor integral with wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/12Supports; Mounting means
    • H01Q1/22Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/24Supports; Mounting means by structural association with other equipment or articles with receiving set
    • H01Q1/241Supports; Mounting means by structural association with other equipment or articles with receiving set used in mobile communications, e.g. GSM
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/36Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/62Fin field-effect transistors [FinFET]
    • H10D30/6211Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6704Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H10D30/6711Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6616Vertical connections, e.g. vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6661High-frequency adaptations for passive devices
    • H01L2223/6677High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
BR112019003900-7A 2016-09-06 2017-08-03 dispositivo ativo de vala profunda com contato da parte posterior do corpo BR112019003900A2 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/257,823 2016-09-06
US15/257,823 US9812580B1 (en) 2016-09-06 2016-09-06 Deep trench active device with backside body contact
PCT/US2017/045349 WO2018048529A1 (en) 2016-09-06 2017-08-03 Deep trench active device with backside body contact

Publications (1)

Publication Number Publication Date
BR112019003900A2 true BR112019003900A2 (pt) 2019-05-21

Family

ID=59684050

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112019003900-7A BR112019003900A2 (pt) 2016-09-06 2017-08-03 dispositivo ativo de vala profunda com contato da parte posterior do corpo

Country Status (7)

Country Link
US (1) US9812580B1 (enExample)
EP (1) EP3510636A1 (enExample)
JP (1) JP2019530218A (enExample)
KR (1) KR20190045909A (enExample)
CN (1) CN109791948A (enExample)
BR (1) BR112019003900A2 (enExample)
WO (1) WO2018048529A1 (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110504240B (zh) * 2018-05-16 2021-08-13 联华电子股份有限公司 半导体元件及其制造方法
CN109524355B (zh) * 2018-10-30 2020-11-10 上海集成电路研发中心有限公司 一种半导体器件的结构和形成方法
CN109545785B (zh) * 2018-10-31 2023-01-31 上海集成电路研发中心有限公司 一种半导体器件结构和制备方法
CN109545802B (zh) * 2018-12-14 2021-01-12 上海微阱电子科技有限公司 一种绝缘体上半导体器件结构和形成方法
CN109616472B (zh) * 2018-12-14 2022-11-15 上海微阱电子科技有限公司 一种半导体器件结构和形成方法
WO2020154950A1 (en) * 2019-01-30 2020-08-06 Yangtze Memory Technologies Co., Ltd. Capacitor structure having vertical diffusion plates
WO2020154977A1 (en) * 2019-01-30 2020-08-06 Yangtze Memory Technologies Co., Ltd. Capacitor structure having vertical diffusion plates
CN110622305B (zh) * 2019-02-18 2021-03-23 长江存储科技有限责任公司 电容器结构及其形成方法
US11251308B2 (en) 2020-04-28 2022-02-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
DE102020122151A1 (de) * 2020-04-28 2021-10-28 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und verfahren
TWI741935B (zh) 2020-04-28 2021-10-01 台灣積體電路製造股份有限公司 半導體元件與其製作方法
US11355410B2 (en) * 2020-04-28 2022-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Thermal dissipation in semiconductor devices
US11349004B2 (en) * 2020-04-28 2022-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Backside vias in semiconductor device
DE102020131611B4 (de) 2020-05-28 2025-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung mit luftspalten und verfahren zu deren herstellung
US20240097657A1 (en) * 2022-09-16 2024-03-21 Apple Inc. Systems and methods for impedance tuning
CN120280431B (zh) * 2025-06-04 2025-09-30 长飞先进半导体(武汉)有限公司 半导体器件及制作方法、功率模块、功率转换电路和车辆

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2948018B2 (ja) * 1992-03-17 1999-09-13 三菱電機株式会社 半導体装置およびその製造方法
US5889298A (en) 1993-04-30 1999-03-30 Texas Instruments Incorporated Vertical JFET field effect transistor
JP3884266B2 (ja) * 2001-02-19 2007-02-21 株式会社東芝 半導体メモリ装置及びその製造方法
US6838722B2 (en) 2002-03-22 2005-01-04 Siliconix Incorporated Structures of and methods of fabricating trench-gated MIS devices
JP2003309182A (ja) * 2002-04-17 2003-10-31 Hitachi Ltd 半導体装置の製造方法及び半導体装置
US6861701B2 (en) 2003-03-05 2005-03-01 Advanced Analogic Technologies, Inc. Trench power MOSFET with planarized gate bus
JP4869546B2 (ja) * 2003-05-23 2012-02-08 ルネサスエレクトロニクス株式会社 半導体装置
JP2005353657A (ja) * 2004-06-08 2005-12-22 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
DE102005030585B4 (de) * 2005-06-30 2011-07-28 Globalfoundries Inc. Halbleiterbauelement mit einem vertikalen Entkopplungskondensator und Verfahren zu seiner Herstellung
JP2009088241A (ja) * 2007-09-28 2009-04-23 Renesas Technology Corp 半導体装置およびその製造方法
JP5487625B2 (ja) * 2009-01-22 2014-05-07 ソニー株式会社 半導体装置
US8395880B2 (en) * 2010-03-30 2013-03-12 Medtronic, Inc. High density capacitor array patterns
US8735984B2 (en) * 2010-07-06 2014-05-27 Globalfoundries Singapore PTE, LTD. FinFET with novel body contact for multiple Vt applications
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US20160172527A1 (en) * 2012-12-03 2016-06-16 Sandia Corporation Photodetector with Interdigitated Nanoelectrode Grating Antenna
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Also Published As

Publication number Publication date
WO2018048529A1 (en) 2018-03-15
EP3510636A1 (en) 2019-07-17
JP2019530218A (ja) 2019-10-17
CN109791948A (zh) 2019-05-21
KR20190045909A (ko) 2019-05-03
US9812580B1 (en) 2017-11-07

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Legal Events

Date Code Title Description
B350 Update of information on the portal [chapter 15.35 patent gazette]
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 5A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: EM VIRTUDE DO ARQUIVAMENTO PUBLICADO NA RPI 2681 DE 24-05-2022 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDO O ARQUIVAMENTO DO PEDIDO DE PATENTE, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.