CN109778289B - Electroplating clamp and circuit board electroplating method using same - Google Patents
Electroplating clamp and circuit board electroplating method using same Download PDFInfo
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- CN109778289B CN109778289B CN201910144606.5A CN201910144606A CN109778289B CN 109778289 B CN109778289 B CN 109778289B CN 201910144606 A CN201910144606 A CN 201910144606A CN 109778289 B CN109778289 B CN 109778289B
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Abstract
The invention relates to the field of electroplating of printed circuit boards, and discloses an electroplating clamp and a circuit board electroplating method using the same. Anchor clamps include anchor clamps handle, connection firmware, electrically conductive support and electrically conductive pinch point, electrically conductive support includes that one row at least that distributes on vertical direction contains two relative electrically conductive strakes, two relative electrically conductive strakes are in same level, and the connection firmware that sets up electrically conductive strake in vertical direction is fixed with electrically conductive strake to with the anchor clamps handle fixed connection of top, set up an electrically conductive pinch point on every electrically conductive strake at least, the part except that contacting with electrically conductive pinch point on the electrically conductive strake all wraps insulating overcoat. And (3) clamping the test circuit chip relatively by adopting a clamp, wherein the back surface of the test circuit chip is opposite, the front surface of the test circuit chip faces the outer side of the clamp, electroplating is carried out, and the relative growth coefficient of a plating layer is calculated. And calculating the normalized total electroplating area and the normalized total electroplating current according to the relative growth coefficient of the plating layer, and electroplating the formal product.
Description
Technical Field
The invention relates to the field of electroplating of printed circuit boards, in particular to an electroplating clamp and a circuit board electroplating method using the same.
Background
The gold electroplating layer is very suitable for microwave transmission because of good corrosion resistance, weldability, low surface contact resistance, high infrared radiation coefficient and reflection coefficient, and is one of the widely adopted ways for plating the surface of a microwave printed circuit board. Gold electroplating for microwave printed circuits is typically performed directly on the surface trace copper layer without a nickel barrier layer in between. This is because nickel has room temperature ferromagnetism, adversely affects microwave transmission, and is not generally used in microwave and millimeter wave circuits. Gold and copper both belong to a face-centered cubic lattice structure system, and the gold and the copper are easy to diffuse mutually. When gold is directly plated on copper, if the gold plating layer is thin, copper and gold may diffuse into each other during storage, high-temperature assembly, and long-term use, resulting in a decrease in wire weldability. According to IPC-2252-2002 guidance on RF/microwave circuit board design, the thickness of gold plating layer is usually required to be more than 3.8 μm to ensure the long-term reliability of gold wire bonding.
The microwave printed circuit board is widely applied at present in a mode that the back surface of the circuit board is fixedly adhered to a metal shell by conductive adhesive, and the front surface of the circuit board is welded by gold wires and gold bands to realize interconnection with other circuits and chips. The front gold layer needs to have a certain thickness to meet the requirement of gold wire and gold belt welding; the back gold layer generally only functions well for oxidation protection and grounding.
In most microwave printed circuit products, the back side is required to retain a large area of metal (copper foil). The presence of these large areas of metal (copper foil) causes unnecessary consumption of precious metal (gold) by the electroplating process. In order to reduce the consumption of noble metal (gold) by the back plating layer as much as possible, the back plating layer is usually formed by attaching an insulating layer to the back surface and performing electroplating twice. The first electroplating is carried out in a short time, so that a layer of thin gold is plated on both sides of the front surface of the circuit piece, then an insulating protective layer is pasted on the back surface of the circuit piece, and the second electroplating is carried out, so that the gold layer on the front surface continuously grows to the required thickness.
This mode of operation has the following limitations in production: (1) the front gold layer is subjected to twice electroplating, and the middle part of the front gold layer is interrupted and paused, so that the front gold layer is used for links such as cleaning, drying, film pasting and the like, and hidden troubles of discontinuous plating layer and poor adhesive force exist; (2) for the circuit board with the metallized via hole, the through hole is changed into a blind hole structure due to the existence of the back insulation protective film during the second electroplating, the solution exchange is difficult, so that the effect of gold plating in the hole is poor, the cleaning in the blind hole is more difficult, and plating solution residue is easy to exist; (3) the temperature of the gold electroplating solution is as high as 60 ℃, long-term electroplating causes the dissolution of the insulating film to pollute the plating solution, and the service life of the plating solution is reduced; (4) the gold plating solution generally adopts a highly toxic potassium aurous cyanide solution system, and the plating solution remains in the holes and the insulating film is discarded, so that the potential safety hazard in the electroplating process is further increased.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: in view of the above existing problems, a plating jig and a circuit board plating method using the same are provided.
The technical scheme adopted by the invention is as follows: the utility model provides an electroplating clamp, includes anchor clamps handle, connection firmware, electrically conductive support and electrically conductive pinch point, electrically conductive support includes that at least one row that distributes in vertical direction contains two relative electrically conductive strakes, two relative electrically conductive strakes are in same level, and the connection firmware that sets up electrically conductive strake in vertical direction is fixed with electrically conductive strake to with the anchor clamps handle fixed connection of top, set up an electrically conductive pinch point on every electrically conductive strake at least, the part except that contact with electrically conductive pinch point on the electrically conductive strake all wraps the insulating overcoat.
Furthermore, the range of the distance between the two opposite conductive edge strips is 3-60 mm.
Further, the distance between the adjacent conductive pinch points is set as follows: the size of the electroplating solution is the same as or slightly smaller than that of a circuit piece to be electroplated in the horizontal direction.
Furthermore, the mode of clamping the circuit piece by the conductive clamping points is thread fixing or elastic sheet fixing.
Furthermore, the conductive clamping point is suitable for clamping a circuit chip with the size and thickness ranging from 0.05mm to 5 mm.
Further, connect the firmware including electrically conductive support extension connecting piece, fastener, electrically conductive support extension connecting piece is half section setting down and is connected the electrically conductive strake of different rows with electrically conductive strake in vertical direction fixedly, electrically conductive support extension connecting piece is first section setting and is used for fixed connection between electrically conductive support and anchor clamps handle, the fastener adopts T type bolt, sets up at electrically conductive support extension connecting piece first section, and it is fixed and realize the electric conductance with electroplating anchor clamps and negative pole.
Furthermore, during electroplating, the electroplating liquid level is arranged at the upper half section of the conductive support extension connecting piece, and the parts of the electroplating hanger below the electroplating liquid level are provided with insulating jackets.
The invention also discloses a circuit board electroplating method using the electroplating clamp, which comprises the following steps:
step S1, clamping at least two test circuit pieces oppositely by using opposite conductive edge strips, wherein the back surfaces of the test circuit pieces are opposite, and the front surfaces of the test circuit pieces face the outer side of the clamp;
step S2, electroplating the clamped test circuit chip, and calculating the relative growth coefficient of the thickness of the plating layer
Wherein the content of the first and second substances,
the average thickness of the gold layers on the back and the front of the circuit chip is respectively;
step S3, calculating a normalized total electroplating area and a normalized total current according to the relative growth coefficient;
and step S4, electroplating the formal product according to the clamping mode of the step S1 and the normalized total current of the step S3.
Further, if the ratio of the plating areas on the back surface and the front surface of the circuit-required circuit chip product has a large variation range, before the step S3, the steps S1 and S2 are repeated to determine a trend relation graph of the plating thickness relative growth coefficient and the area ratio; determining the relative growth coefficient of the thickness of the coating according to the coating area ratio of the formal product; step S3 and step S4 are performed again.
Further, in the step S3, the total electroplating area S is normalizedNormalization＝SIs just+T×SBack of bodyNormalized total current INormalization＝D×SNormalizationIn which S isIs just、SBack of bodyThe areas of the front and back plating layers of the circuit chip are respectively; d is the current density.
Compared with the prior art, the beneficial effects of adopting the technical scheme are as follows: the invention adopts the electroplating clamp hung in double rows, realizes mutual shielding of the circuit pieces structurally, and reduces the distribution of power lines on the back of the circuit pieces in the electroplating process. The invention also provides a calculation and clamping method for electroplating by using the electroplating clamp, which comprises the following steps: calculating the normalized electroplating total surface according to the relative growth coefficient T of the thickness of the plating layerProduct SNormalizationNormalized total current INormalizationAnd clamping the circuit piece in a mode that the front surface of the circuit piece faces outwards. The circuit piece to be plated only needs to be plated once in the whole process, so that the effects of thick (gold) front surface and thin (gold) back surface can be achieved, and unnecessary consumption of precious metal (gold) plated on the back surface is effectively reduced. Meanwhile, the problems of discontinuous plating layer, inapplicability to metallized via hole products, pollution of plating solution, treatment of waste highly toxic substances and the like in the conventional secondary electroplating technology are avoided.
Drawings
FIG. 1 is a schematic view of a plating jig according to the present invention.
FIG. 2 is a schematic view of the plating jig of FIG. 1 during plating.
FIG. 3 is a graph showing the relationship between the thickness of a plating layer and the growth coefficient and the area ratio, which are determined when the embodiment of the present invention is applied to the plating of various products.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
As shown in figure 1, the electroplating clamp comprises a clamp handle 4-1, a connecting fastener, a conductive bracket 1 and a conductive clamping point 2, the conductive support comprises at least one row of two opposite conductive bars 1-1 (the embodiment of fig. 1 shows three rows in the top, middle and bottom) distributed in the vertical direction, each row of two opposite conductive bars being at the same level (one conductive bar inside cannot be seen in the figure), there being a total of 6 conductive bars, the connecting and fixing piece which is provided with the conductive edge strip in the vertical direction fixes the conductive edge strip and is fixedly connected with the clamp handle 4-1 above, each conductive edge strip is provided with at least one conductive clamping point 2 (3 conductive clamping points are arranged in the embodiment of figure 1), the conductive clamping points 2 are electrically communicated with the conductive edge strips, the conductive edge strip 1-1 is used for clamping a circuit piece to be plated, and the parts except the parts contacted with the conductive clamping points 2 are all wrapped with insulating outer sleeves.
Preferably, the distance between the two opposite conductive edge strips ranges from 3 mm to 60 mm.
Preferably, when the number of the conductive clamping points on the same conductive edge strip is greater than 1, the distance between the adjacent conductive clamping points is set as follows: the size of the electroplating solution is the same as or slightly smaller than that of the circuit piece to be electroplated in the horizontal direction, namely the circuit piece to be electroplated is close to or slightly overlapped in the horizontal direction. When there is overlap, the graphics on the die should not be covered. The distance of the conductive clamping points is set, so that the power line can be better prevented from reaching the back surface through the gap between the circuit pieces in the electroplating process, and the increase of the thickness of the plating layer on the back surface of the circuit piece is restrained.
Preferably, the conductive clamping points clamp the circuit piece in a threaded fixing mode or a spring plate fixing mode.
Preferably, the conductive clamping point is suitable for clamping a circuit chip with the size and the thickness ranging from 0.05mm to 5 mm.
Preferably, the connecting and fixing part comprises a conductive support extending connecting piece 4-3 and a fastening piece 4-2, the lower half section of the conductive support extending connecting piece is arranged in the vertical direction and is connected with the conductive edge strips to fix the conductive edge strips 1-1 of different rows, the upper half section of the conductive support extending connecting piece is arranged between the conductive support 1 and the clamp handle for fixed connection, and the fastening piece 4-2 adopts a T-shaped bolt and is arranged on the upper half section of the conductive support extending connecting piece to fix the electroplating clamp and the cathode rod 7 and realize electric conduction.
In the embodiment shown in fig. 1 and fig. 2, the dotted line is the plating liquid level 3, during plating, the plating liquid level 3 is at the upper half section of the conductive bracket extension connecting piece, and the parts of the plating hanger below the plating liquid level 3 are all provided with insulating outer sleeves, so that redundant plating layers are prevented from being plated during plating. In fig. 2, 5 is an electroplating tank body, and 6 is a circuit chip to be electroplated. 6-1 is the front side of the circuit chip, and 6-2 is the back side of the circuit chip.
The invention also discloses a method for electroplating the circuit board by using the electroplating clamp, wherein the electroplating clamp used in the method can be the electroplating clamp in the invention or is not limited to the circuit clamp in the invention, but the circuit clamp needs to have opposite conductive edgings to oppositely clamp two circuit pieces, and the method comprises the following processes:
step S1, clamping at least two test circuit pieces oppositely by using opposite conductive edge strips, wherein the back surfaces of the two test circuit pieces are opposite, and the front surfaces of the test circuit pieces face the outer side of the clamp;
the front side of the circuit chip refers to a pattern surface which needs gold wire gold belt welding and needs a thicker plating layer in the later period. In the embodiment of fig. 2, each conductive clip holds 1 die 6 for a total of 18 dies; when clamping, the front surfaces 6-1 of the circuit chips face the outer side of the clamp, so that the back surfaces 6-2 of the two rows of circuit chips are opposite.
Secondly, preparing a circuit piece to be plated for testing, wherein the circuit patterns of the front surface and the back surface of the circuit piece are similar to those of a formal product.
Step S2, the electroplating clamp is fixed on the conductive cathode rod 7, the clamped test circuit chip is electroplated, and the relative growth coefficient of the thickness of the plating layer is calculated
Wherein the content of the first and second substances,
the average thickness of the gold layers on the back and the front of the circuit chip is respectively;
during testing, the calculation method of the current required by electroplating comprises the following steps: according to the total area (S) of the test circuit chip platingGeneral assembly＝SIs just+SBack of body) The required current density D, and the total current (I) required by electroplatingGeneral assembly＝D×SGeneral assembly)。
Step S3, calculating a normalized total electroplating area and a normalized total current according to the relative growth coefficient;
normalized total electroplating area SNormalization＝SIs just+T×SBack of bodyNormalized total current INormalization＝D×SNormalizationIn which S isIs just、SBack of bodyThe areas of the front and back plating layers of the circuit chip are respectively; d is the current density.
And step S4, electroplating the formal product according to the clamping mode of the step S1 and the normalized total current of the step S3.
Preferably, the plating method when involving a plurality of types of products is adjusted:
the ratio of the relative growth coefficient T of the thickness of the plating layer to the area of the pattern of the circuit chip to be plated (S)Ratio of＝SBack of body/SIs just) And the relative spacing L of the electrogilding fixtures are closely related. Relative to each otherThe spacing L is constant, SRatio ofThe larger the thickness of the plating layer is, the smaller the relative growth coefficient T is; when the pattern area ratio is constant, the larger L is, the larger T is the relative growth coefficient of the plating thickness.
When the types of the related circuit chip products are more and the range of the area ratio of the patterns is larger, multiple times of tests and calculations of the step S1 and the step S2 are needed to determine a trend relation graph of the plating thickness relative growth coefficient and the area ratio. And when the formal product is electroplated, determining the relative growth coefficients of different coating thicknesses according to the graph area ratio and the trend relation graph of the product to be plated. Then, calculating the normalized total electroplating area and the normalized total current according to the step S3; electroplating is performed as per step S4. When the relative distance L of the fixture is changed, the trend relation graph of the thickness of the coating relative to the growth coefficient and the area ratio is also correspondingly tested and adjusted.
In the embodiment shown in fig. 3, an example of a trend relation graph of the plating thickness relative growth coefficient and the area ratio is obtained by performing multiple tests and calculations on various products under the condition that the relative distance L of a certain clamp is fixed. When the formal product is electroplated, the area ratio S of the patterns of the product to be electroplated is determinedRatio ofAnd determining the corresponding plating thickness relative growth coefficient in the trend relation graph. Then, calculating the normalized total electroplating area and the normalized total current according to the step S3; electroplating is performed as per step S4.
The invention is not limited to the foregoing embodiments. The invention extends to any novel feature or any novel combination of features disclosed in this specification and any novel method or process steps or any novel combination of features disclosed. Insubstantial changes or modifications, such as changes in the range of relative distances L, changes in the type of plating, changes in the number of pinch points and the manner of clamping, which would occur to those skilled in the art without departing from the spirit of the invention, are intended to be covered by the claims of this invention.
Claims (9)
1. An electroplating clamp is characterized by comprising a clamp handle, a connecting fixing piece, a conductive support and conductive clamping points, wherein the conductive support comprises at least one row of two opposite conductive edge strips distributed in the vertical direction, the two opposite conductive edge strips are positioned at the same horizontal height, the conductive edge strips are fixed by the connecting fixing piece which is provided with the conductive edge strips in the vertical direction and are fixedly connected with the clamp handle above the conductive edge strips, at least one conductive clamping point is arranged on each conductive edge strip, the opposite conductive edge strips are used for relatively clamping at least two circuit boards, and parts of the conductive edge strips except the contact with the conductive clamping points are wrapped with insulating outer sleeves.
2. The plating jig of claim 1, wherein the distance between the two opposing conductive edge strips ranges from 3 mm to 60 mm.
3. The plating jig of claim 2, wherein the distance between adjacent conductive pinch points is set to: the size of the electroplating solution is the same as that of a circuit piece to be electroplated in the horizontal direction.
4. The plating jig of claim 3, wherein the conductive clip holds the circuit chip by screw fastening or spring fastening.
5. The plating jig of claim 4, wherein the conductive clip is adapted to hold a die having a dimension and thickness in the range of 0.05mm to 5 mm.
6. The electroplating jig of claim 5, wherein the connecting member comprises an electrically conductive frame extension connecting member, and a fastening member, wherein the lower half section of the electrically conductive frame extension connecting member is vertically connected with the electrically conductive edge strip to fix the electrically conductive edge strip of different rows, the upper half section of the electrically conductive frame extension connecting member is arranged between the electrically conductive frame and the jig handle for fixed connection, and the fastening member is a T-shaped bolt arranged on the upper half section of the electrically conductive frame extension connecting member to fix the electroplating jig and the cathode rod and realize electric conduction.
7. The plating jig of claim 6, wherein the plating liquid level is in the upper half of the extended connector of the conductive bracket during plating, and the portions of the plating jig below the plating liquid level are provided with insulating jackets.
8. A plating method of a circuit board using the plating jig of claim 1, comprising the steps of:
step S1, clamping at least two test circuit pieces oppositely by using opposite conductive edge strips, wherein the back surfaces of the test circuit pieces are opposite, and the front surfaces of the test circuit pieces face the outer side of the clamp;
step S2, electroplating the clamped test circuit chip, and calculating the relative growth coefficient of the thickness of the plating layer
Wherein the content of the first and second substances,
the average thickness of the gold layers on the back and the front of the circuit chip is respectively;
step S3, calculating a normalized total electroplating area and a normalized total current according to the relative growth coefficient; normalized total electroplating area SNormalization＝SIs just+T×SBack of bodyNormalized total current INormalization＝D×SNormalizationIn which S isIs just、SBack of bodyThe areas of the front and back plating layers of the circuit chip are respectively; d is the current density;
and step S4, electroplating the formal product according to the clamping mode of the step S1 and the normalized total current of the step S3.
9. A plating method for a circuit board using a plating jig according to claim 8, wherein if the plating area ratio of the back surface and the front surface of the circuit chip product to be wired is changed in a wide range, before step S3, steps S1 and S2 are repeated to determine a trend graph of the plating thickness versus growth coefficient versus area ratio; determining the relative growth coefficient of the thickness of the coating according to the coating area ratio of the formal product; step S3 and step S4 are performed again.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910144606.5A CN109778289B (en) | 2019-02-27 | 2019-02-27 | Electroplating clamp and circuit board electroplating method using same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910144606.5A CN109778289B (en) | 2019-02-27 | 2019-02-27 | Electroplating clamp and circuit board electroplating method using same |
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| CN109778289B true CN109778289B (en) | 2020-06-12 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP7421302B2 (en) | 2019-10-07 | 2024-01-24 | 上村工業株式会社 | Holding jig |
| CN111893549A (en) * | 2020-06-24 | 2020-11-06 | 黄石广合精密电路有限公司 | Method for realizing automatic indication of electroplating parameters of PCB (printed circuit board) |
| CN113238106B (en) * | 2021-04-25 | 2023-04-07 | 四川英创力电子科技股份有限公司 | Method for rapidly checking electrical conductivity of electroplating clamp |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201534890U (en) * | 2009-08-27 | 2010-07-28 | 佛山市蓝箭电子有限公司 | Pure tin electroplating device |
| CN102080253A (en) * | 2010-12-23 | 2011-06-01 | 北大方正集团有限公司 | Electroplating fixture and printed wiring board electroplating system |
| CN102400192A (en) * | 2011-11-10 | 2012-04-04 | 深南电路有限公司 | Method for electroplating gold to circuit boards |
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2019
- 2019-02-27 CN CN201910144606.5A patent/CN109778289B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201534890U (en) * | 2009-08-27 | 2010-07-28 | 佛山市蓝箭电子有限公司 | Pure tin electroplating device |
| CN102080253A (en) * | 2010-12-23 | 2011-06-01 | 北大方正集团有限公司 | Electroplating fixture and printed wiring board electroplating system |
| CN102400192A (en) * | 2011-11-10 | 2012-04-04 | 深南电路有限公司 | Method for electroplating gold to circuit boards |
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