CN109727869A - 半导体装置结构的制造方法 - Google Patents

半导体装置结构的制造方法 Download PDF

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Publication number
CN109727869A
CN109727869A CN201810272560.0A CN201810272560A CN109727869A CN 109727869 A CN109727869 A CN 109727869A CN 201810272560 A CN201810272560 A CN 201810272560A CN 109727869 A CN109727869 A CN 109727869A
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China
Prior art keywords
layer
source
fin
gate
drain
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CN201810272560.0A
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Inventor
沈香谷
鄞金木
萧琮介
庄家霖
游力蓁
陈殿豪
王士玮
余德伟
陈建豪
卢柏全
李志鸿
徐志安
洪敏修
黄鸿仪
周俊诚
庄英良
黄彦钧
彭治棠
赵晟博
陈燕铭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN109727869A publication Critical patent/CN109727869A/zh
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    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

根据本公开一些实施例，提供半导体装置结构的制造方法。上述方法包含形成鳍结构于基底上。上述方法亦包含形成栅极结构于鳍结构上。上述方法还包含形成鳍间隙物于鳍结构的侧壁上，及形成栅极间隙物于栅极结构的侧壁上。此外，上述方法包含形成源/漏极结构于鳍结构上，及沉积虚置材料层以覆盖源/漏极结构。上述方法亦包含移除虚置材料层以露出源/漏极结构及鳍间隙物。上述方法还包含形成硅化物层于源/漏极结构及鳍间隙物上，且形成接触物于硅化物层上。虚置材料层包含锗、非晶硅或旋涂碳。

Description

半导体装置结构的制造方法
技术领域
本公开实施例系有关于半导体装置结构及其制造方法，特别系有关于具有较大表面积的硅化物层的半导体装置结构及其制造方法。
背景技术
半导体集成电路(integrated circuit,IC)工业持续地成长。IC材料和设计的技术进步制造了许多世代的IC。每一个世代具有比之前世代更小且更复杂的电路。
在集成电路革新的课题中，功能密度(例如，单位芯片面积内彼此相连的装置数目)持续的增加，而几何尺寸(例如，制造工艺所能创造出的最小组件(或线))持续的缩小。微缩工艺提供了较大的制造效率及降低成本的好处。
微缩尺寸也增加工艺和制造IC的复杂度，并且，为了实现上述的优点，IC工艺和制造也同样的需要更多发展。例如，三维晶体管，例如导入具有鳍式场效晶体管(fin field-effect transistor)以取代平面晶体管。这些型态相对较新颖的半导体IC装置面临工艺挑战，且并不能在所有方面令人满意。
发明内容
根据本公开一些实施例，提供半导体装置结构的制造方法。上述方法包含形成鳍结构于基底上。上述方法亦包含形成栅极结构于鳍结构上。上述方法还包含形成鳍间隙物于鳍结构的侧壁上及栅极间隙物于栅极结构的侧壁上。此外，上述方法包含形成源/漏极结构于鳍结构上及沉积虚置材料层以覆盖源/漏极结构。上述方法亦包含移除虚置材料层以露出源/漏极结构及鳍间隙物。上述方法还包含形成硅化物层于源/漏极结构及鳍间隙物上，且形成接触物于硅化物层上。虚置材料层包含锗、非晶硅或旋涂碳。
附图说明
本公开的各种样态最好的理解方式为阅读以下说明书的详说明并配合所附附图。应该注意的是，本公开的各种不同特征部件并未依据工业标准作业的尺寸而绘制。事实上，为使说明书能清楚叙述，各种不同特征部件的尺寸可以任意放大或缩小。
图1是根据一些实施例，示出形成半导体装置结构的工艺的其中一阶段的立体图。
图2A-图2O是根据一些实施例，示出形成半导体装置结构的工艺的各阶段的剖面图。
图3A-图3O是根据一些实施例，示出形成半导体装置结构的工艺的各阶段的剖面图。
图4是根据一些实施例，示出半导体装置结构的剖面图。
图5是根据一些实施例，示出半导体装置结构的剖面图。
附图标记说明：
100 半导体基底
110a 鳍结构
110b 鳍结构
120 隔离部件
130 栅极介电层
132 栅极电极
140 栅极结构
150 栅极间隙物
160 鳍间隙物
170a 源/漏极结构
170b 源/漏极结构
170c 源/漏极结构
180 衬层
190 虚置材料层
200 栅极结构
202 栅极介电层
204 栅极电极
210 掩模结构
220 金属层
230 硅化物层
240 覆盖层
250 第一介电层
260 第二介电层
270 硅化物层
280 接触物
290 接触物
1000 半导体装置结构
2000 半导体装置结构
3000 半导体装置结构
S1 第一表面
S2 第二表面
S3 第三表面
T 表面
T1 沟槽
T2 沟槽
W1 宽度
W2 宽度
W3 宽度
具体实施方式
要了解的是本说明书以下的公开内容提供许多不同的实施例或范例，以实施本公开的不同特征部件。而本说明书以下的公开内容是叙述各个构件及其排列方式的特定范例，以求简化发明的说明。当然，这些特定的范例并非用以限定本公开。例如，若是本说明书以下的公开内容叙述了将一第一特征部件形成于一第二特征部件之上或上方，即表示其包含了所形成的上述第一特征部件与上述第二特征部件是直接接触的实施例，亦包含了将附加的特征部件形成于上述第一特征部件与上述第二特征部件之间，而使上述第一特征部件与上述第二特征部件可能未直接接触的实施例。另外，本公开的说明中不同范例可能使用重复的参考符号和/或用字。这些重复符号或用字系为了简化与清晰的目的，并非用以限定各个实施例和/或所述外观结构之间的关系。
再者，为了方便描述附图中一元件或特征部件与另一(复数)元件或(复数)特征部件的关系，可使用空间相关用语，例如”在…之下”、”下方”、”下部”、”上方”、”上部”及类似的用语。除了附图所示出的方位之外，空间相关用语涵盖使用或操作中的装置的不同方位。例如，若翻转附图中的装置，描述为位于其他元件或特征部件”下方”或”在…之下”的元件，将定位为位于其他元件或特征部件”上方”。因此，范例的用语”下方”可涵盖上方及下方的方位。所述装置也可被另外定位(例如，旋转90度或者位于其他方位)，并对应地解读所使用的空间相关用语的描述。
本公开实施例形成具有较大表面积的硅化物层的半导体装置结构。本公开一些实施例如下所述。图1是根据一些实施例，示出形成半导体装置结构的工艺的其中一阶段的立体图。为了更容易了解本公开实施例所述的半导体装置结构，图1提供X-Y-Z坐标。X轴指向半导体装置结构的基底表面的侧面方向。Y轴指向基底表面之垂直于X轴的方向。Z轴指向与X-Y平面垂直的方向。
图2A-图2O是根据一些实施例，示出形成半导体装置结构的工艺的各阶段的的剖面图。在一些实施例，图2A-图2O是沿图1所示的线段I-I’的剖面图。线段I-I’可大抵上平行于Y轴。图3A-图3O是根据一些实施例，示出形成半导体装置结构的工艺的各阶段的剖面图。在一些实施例，图3A-图3O是沿图1所示的线段II-II’的剖面图。线段II-II’可大抵上平行于X轴。
更具体而言，图2A-图2O是示出栅极结构、鳍结构和源/漏极结构的剖面图，图3A-图3O示出两个栅极结构之间的剖面图，其示出鳍结构及源/漏极结构。
可在图1、图2A-图2O、图3A-图3O、图4及图5的之前、期间和/或之后提供额外的操作。在不同的实施例，一些描述的阶段可以被取代或省略。可在半导体装置结构增加额外的部件。在不同的实施例，一些描述的部件可以被取代或省略。
如图1、图2A及图3A所示，提供半导体基底100。半导体基底100的表面大抵上平行于X-Y平面。在一些实施例，半导体基底100例如为块材半导体基底，例如为半导体晶片。在一些实施例，半导体基底100包含硅或其他元素半导体材料，例如锗。例如，半导体基底100为硅晶片。在其他实施例，半导体基底100包含化合物半导体。化合物半导体可包含砷化锗、碳化硅、砷化铟、磷化铟、其他适合的化合物半导体，或上述组合。
在一些实施例，半导体基底100包含绝缘上覆半导体(semiconductor-on-insulation,SOI)基底。SOI基底可利用晶片接合工艺、硅膜转移工艺、植氧分离(separation by implantation of oxygen,SIMOX)工艺、其他适合的方法，或上述组合形成。
在一些实施例，如图3A所示，形成多个鳍结构110于半导体基底100上。鳍结构110a可通过适合的方法而图案化。例如，鳍结构110a可利用一或多个黄光光刻工艺图案化，其包含双图案化或多重图案化工艺。一般而言，相较于直接使用单一黄光光刻工艺，双图案化或多重图案化工艺结合黄光光刻及自我对准工艺，能借此得到具有较小间距的图案。例如，在一实施例，形成牺牲层于基底上，并使用黄光光刻工艺图案化。使用自我对准工艺，沿着经图案化的牺牲层形成间隙物。之后，移除牺牲层，而剩下的间隙物可用来图案化鳍。
在一些实施例，如图1及图3A所示，隔离部件120形成在半导体基底100的凹陷内，以围绕鳍结构110a的下部。隔离部件120用来定义并且电性隔离形成在半导体基底100内和/或上的不同的装置元件。在一些实施例，隔离部件120包含浅沟槽隔离(shallow trenchisolation,STI)、局部氧化硅(local oxidation of silicon,LOCOS)部件、其他适合的隔离部件或上述组合。
在一些实施例，隔离部件120由介电材料形成。介电材料可包含氧化硅、氮化硅，氮氧化硅、旋涂玻璃(spin-on glass)、低介电常数(low-K)介电材料、其他适合的材料，或上述组合。在一些实施例，每一个隔离部件120具有多重层结构。在一些实施例，沉积介电材料层于半导体基底100上。介电材料层覆盖鳍结构110且填入鳍结构110a之间的凹陷内。在一些实施例，介电材料层通过化学气相沉积(chemical vapor deposition,CVD)工艺、旋转涂布工艺、其他适合的工艺，或上述组合沉积。在一些实施例，执行平坦化工艺来薄化介电材料层，直到露出鳍结构110的上表面。平坦化工艺可包含化学机械研磨(chemicalmechanical polishing,CMP)工艺、研磨工艺、蚀刻工艺、其他适合的工艺，或上述组合。之后，回蚀刻(etching back)介电材料层以形成隔离部件120。在一些实施例，如图1及图3A所示，鳍结构110a凸出隔离部件120。
在一些实施例，如图1及图2A所示，形成栅极结构140于半导体基底100上。栅极结构140覆盖多个鳍结构110a及多个隔离部件120的一部分。在一些实施例，如图1所示，每一个栅极结构140沿着X轴延伸，且上述多个栅极结构140排列的方向大抵上平行于Y轴。栅极结构140可为牺牲栅极结构，将在后续的工艺被移除。在一些实施例，如图2A所示，栅极结构140的一部分形成在鳍结构110a上。
在一些实施例，每一个栅极结构140包含栅极介电层130及栅极电极132。栅极介电层130在鳍结构110a及隔离部件120上方延伸。在一些实施例，栅极介电层130为牺牲或虚置栅极介电层，并且将会被另一个栅极介电层取代。在一些实施例，栅极介电层130由高介电常数介电材料形成。高介电常数介电材料的例子包含氧化铪、氧化锆、氧化铝、氮氧化硅、二氧化铪-氧化铝合金、氧化铪硅、氮氧化铪硅、氧化铪、氧化铪钛、氧化铪锆、其他适合的高介电常数材料及上述组合。
栅极电极132形成在栅极介电层130上方。在一些实施例，栅极电极132包含多晶硅、金属材料、其他适合的导电材料，或上述组合。在一些实施例，栅极电极132为牺牲或虚置栅极电极层，并且将会被另一个导电材料(例如金属材料)取代。牺牲栅极电极层由牺牲材料形成，例如多晶硅。
在一些实施例，栅极结构140包含硬掩模(未示出)，其形成在栅极电极132上方。硬掩模可用来协助形成栅极介电层130和栅极电极132的图案化工艺。在一些实施例，硬掩模包含氧化硅、氮化硅、氮氧化硅、碳化硅、其他适合的材料，或上述组合。在一些实施例，硬掩模具有多重层结构。
例如，在一些实施例，通过适合的沉积方法来沉积栅极介电材料层和栅极电极材料层。适合的沉积方法可例如为CVD工艺、原子层(atomic layer deposition,ALD)工艺、热氧化工艺、物理气相沉积(physical vapor deposition,PVD)工艺、其他适合的工艺，或上述组合。接下来，执行黄光光刻工艺及蚀刻工艺，以图案化硬掩模层。通过使用经图案化的硬掩模，可蚀刻并图案化栅极介电材料层和栅极电极层。然后，形成栅极介电层130和栅极电极132。
在一些实施例，如图1及图2A所示，形成栅极间隙物150于栅极结构140的侧壁上。栅极间隙物150可包含四族元素、五族元素和/或六族元素。在一些实施例，栅极间隙物150由氮化硅、氮氧化硅、碳化硅、碳氧化硅，其他适合的材料，或上述组合形成。在一些实施例，间隙物层通过使用CVD工艺、PVD工艺、旋转涂布工艺、其他适合的工艺或上述组合形成。接下来，执行蚀刻工艺，例如各向异性蚀刻工艺，来移除部分的间隙物层。然后，位于栅极结构140的侧壁上的间隙物层的剩余部分形成了栅极间隙物150。
如图2A所示，在一些实施例，每一个栅极间隙物150为单一层。在一些实施例，每一个栅极间隙物150具有多重层结构。例如，每一个栅极间隙物150可包含多个氮化物层。可在本公开实施例作各种变化和/或调整。在其他实施例，栅极间隙物150并未形成。
在一些实施例，如图3A所示，形成鳍间隙物160于鳍结构110a的侧壁上。鳍间隙物160用来定义后续形成的源/漏极结构的轮廓。鳍间隙物160可包含四族元素、五族元素和/或六族元素。在一些实施例，鳍间隙物160由氮化硅、氮氧化硅、碳化硅、碳氧化硅，其他适合的材料，或上述组合形成。在一些实施例，鳍间隙物160和栅极间隙物150由相同的材料形成。在一些实施例，鳍间隙物160和栅极间隙物150由不同的材料形成。
在一些实施例，间隙物层通过使用CVD工艺、PVD工艺、旋转涂布工艺、其他适合的工艺，或上述组合沉积。接下来，执行蚀刻工艺，例如各向异性蚀刻工艺，以移除部分的间隙物层。然后，位于鳍结构110a的侧壁上的间隙物层的剩余部分形成了鳍间隙物160。
之后，在一些实施例，如图1、图2A及图3A所示，形成源/漏极(source/drain,S/D)结构170a于鳍结构110a上方。源/漏极结构170a可用来提供应力或应变至鳍结构110a之位于栅极结构140的下方的沟道区。
在一些实施例，如图2A及图3A所示，移除鳍结构110a以形成凹陷，并且在鳍结构110a的凹陷上方外延生长一半导体材料(或者是两个或更多个半导体材料)。持续地生长半导体材料以形成源/漏极结构170a。在一些实施例，如图1及图3A所示，源/漏极结构170a为单一层。在一些实施例，源/漏极结构170a具有多重层，且每一层具有彼此不同的成分及组成。
如图2A所示，源/漏极结构170a形成在两个栅极结构140之间。在一些实施例，如图2A及图3A所示，源/漏极结构170a邻接两个鳍结构110a和栅极间隙物150。在一些实施例，鳍结构110a的一部分由鳍间隙物160露出，且鳍结构110a的上表面比鳍间隙物160的顶部低。如图3A所示，源/漏极结构170a生长在鳍结构110a之中未被鳍间隙物160覆盖部分的上方。在一些实施例，源/漏极结构170a直接接触鳍间隙物160，且部分的源/漏极结构170a形成在鳍结构110a的凹陷内。
在一些实施例，如图2A所示，在沿着Y轴的剖面，由于结晶的结构关系，源/漏极结构170a具有钻石形状。在一些实施例，如图3A所示，在沿着X轴的剖面，源/漏极结构170a为鹅蛋形。
在一些实施例，如图3A所示，源/漏极结构170a具有第一表面S1，上述第一表面S1覆盖两个鳍结构110a的上表面。第一表面S1是源/漏极结构170a的上表面，其由一个鳍结构110a的侧壁向外延伸朝向另一个鳍结构110a的侧壁。在一些实施例，如图2A所示，第一表面S1的一部分在两个相邻的栅极结构140的栅极间隙物150之间延伸。在一些实施例，如图2A所示，源/漏极结构170a的第一表面S1具有宽度W1，上述宽度W1指的是两个栅极间隙物150之间的间距。
在一些实施例，如图3A所示，源/漏极结构170a具有第二表面S2，上述第二表面S2在两个鳍结构110a之间延伸。更具体而言，第二表面S2是源/漏极结构170a的底部表面，其在相邻的两个不同的鳍结构110a的侧壁之间延伸。此外，如图3A所示，第二表面S2在第一表面S1下方。
在一些实施例，源/漏极结构170a是P型半导体材料。例如，源/漏极结构170a可包含外延生长硅或外延生长硅锗。源/漏极结构170a并不限于P型半导体材料。在一些实施例，源/漏极结构170a为N型半导体材料。源/漏极结构170a可包含外延成硅、硅锗(SiGe)、外延生长掺杂磷的硅(SiP)、掺杂硼的硅锗(SiGeB)或其他适合的外延生长半导体材料。
在一些实施例，源/漏极结构170a通过选择性外延生长(selective epitaxygrowth,SEG)工艺、CVD工艺(例如，气相外延(vapor-phase epitaxy,VPE)工艺、低压化学气相沉积(low pressure chemical vapor deposition,LPCVD)工艺，和/或超高真空化学气相沉积(ultra-high vacuum chemical vapor deposition,UHV-CVD)工艺)、分子束外延工艺，沉积经掺杂的非晶半导体(例如，Si、Ge或SiGe)之后固相外延再结晶(solid-phaseepitaxial recrystallization,SPER)步骤、其他适合的工艺，或上述组合形成。源/漏极结构170a的形成工艺可使用气态和/或液态的前驱物。在一些实施例，源/漏极结构170a在相同的工艺腔室内原位(in-situ)生长。换句话说，源/漏极结构170a通过使用原位外延生长工艺形成。在其他实施例，源/漏极结构170a的一些部分由分开的工艺生成。
在一些实施例，使用一种或多种适合的掺杂质掺杂源/漏极结构170a。例如，源/漏极结构170a是经磷、砷或其他适合的掺杂质掺杂的硅源极或漏极部件。或者，源/漏极结构170a是经由硼或其他适合的掺杂质掺杂的硅锗源极或漏极部件。在一些实施例，执行多个注入工艺以掺杂源/漏极结构170a。
在一些实施例，在源/漏极结构170a的生长期间，源/漏极结构170a为原位掺杂。在其他实施例，在源/漏极结构170a的生长期间，并未对源/漏极结构170a掺杂。外延生长后，源/漏极结构170a在后续的工艺掺杂。在一些实施例，通过离子注入工艺、等离子体浸入(plasma immersion)离子注入工艺、气态和/或固态源扩散工艺、其他适合的工艺，或上述组合执行掺杂。在一些实施例，进一步对源/漏极结构170a执行退火工艺，以活化掺杂质。例如，执行快速热退火工艺。
在一些实施例，如图2B及图3B所示，形成衬层180在栅极间隙物150的侧壁上，且共形地形成在源/漏极结构170a上方。衬层180可用来减少位于源/漏极结构170a和后续形成的虚置材料层之间的界面的缺陷。在一些实施例，源/漏极结构170a的底部并未被衬层180覆盖，且源/漏极结构170a的顶部与衬层180直接接触。更具体而言，如图3B所示，衬层180并未完全地环绕源/漏极结构170a。
在一些实施例，衬层180由介电材料层形成，其包含氮化硅、氮氧化硅、碳化硅、碳氧化硅、其他适合的材料或上述组合。在一些实施例，介电材料层通过使用CVD工艺、PVD工艺、旋转涂布工艺、其他适合的工艺或上述组合沉积。在一些实施例，执行平坦化工艺，以薄化介电材料层，直到露出栅极结构140和栅极间隙物150的上表面，以形成衬层180。平坦化工艺可包含CMP工艺、研磨工艺、蚀刻工艺、其他适合的工艺或上述组合。
在一些实施例，如图2C及图3C所示，沉积虚置或牺牲材料层190于衬层180和源/漏极结构170a的上方，且位于两个栅极结构140之间。在一些实施例，虚置材料层190并未填入鳍结构110a之间。虚置材料层190将在后续的工艺被移除。
在一些实施例，虚置材料层190的材料包含Ge、非晶硅、旋涂碳(spin-on carbon,SOC)、其他适合的半导体和/或介电材料。在一些实施例，虚置材料层190的材料相对于栅极间隙物150及鳍间隙物160，具有较高的蚀刻选择性。更具体而言，执行后续的蚀刻工艺时，相对于栅极间隙物150及鳍间隙物160，蚀刻剂对于虚置材料层190具有较高的蚀刻选择性。因此，虚置材料层190被蚀刻的速率比栅极间隙物150和鳍间隙物160被蚀刻的速率快。在一些实施例，虚置材料层190具有多重层结构。在一些实施例，虚置材料层190通过使用CVD工艺、PVD工艺、旋转涂布工艺、其他适合的工艺，或上述组合沉积。
在一些实施例，如图2D及图3D所示，栅极结构140被栅极结构200取代。在一些实施例，每一个栅极结构200包含栅极介电层202及栅极电极204。在一些实施例，栅极结构140a的栅极介电层130和栅极电极132通过干蚀刻工艺、湿蚀刻工艺或其他适合的蚀刻工艺。在一些实施例，栅极介电层202和栅极电极204的材料和形成方法分别与栅极介电层130和栅极电极132的材料和形成方法相同或相似。
在其他实施例，栅极介电层202及栅极电极204的材料分别与栅极介电层130和栅极电极132的材料不同。在一些实施例，栅极电极204由金属材料形成，例如TiN、TaN、TaC、Co、Ru、Al、W或上述组合。
此外，可增加额外的层来形成栅极结构200。栅极电极204可包含一或多个金属栅极堆叠层(未示出)。金属栅极堆叠层的例子包含阻挡层、功函数层、阻隔层、粘着层、金属填充层、其他适合的金属栅极层及上述组合。在不同的实施例，这些金属栅极堆叠层的一部分可以被取代或省略。可增加额外的层来形成金属栅极堆叠层。
在一些实施例，如图2E及图3E所示，形成掩模结构210于栅极结构200上方，以覆盖栅极结构200的上表面。掩模结构210用来保护栅极结构200，避免其在后续的蚀刻工艺或其他的工艺受到损害。在一些实施例，掩模结构210覆盖栅极结构200，并未覆盖栅极间隙物150、衬层180及虚置材料层190。
在一些实施例，掩模结构210包含氧化硅、氮化硅、氮氧化硅、碳化硅或上述组合。在一些实施例，硬掩模210具有多重层结构。可在本公开实施例作各种变化和/或调整。在其他实施例，掩模结构210并未形成。
在一些实施例，如图2F及图3F所示，执行蚀刻工艺，以移除衬层180及虚置材料层190。在一些实施例，移除衬层180及虚置材料层190，露出源/漏极结构170a的第一表面S1。在一些实施例，移除衬层180及虚置材料层190后，露出栅极间隙物150的侧壁。在一些实施例，移除衬层180及虚置材料层190后，露出鳍间隙物160的侧壁。在一些实施例，在移除衬层180及虚置材料层190的过程中，虚置材料层190的移除速率比栅极间隙物150和鳍间隙物的移除速率快。
在一些实施例，蚀刻工艺包含干蚀刻工艺(例如等离子体蚀刻工艺)或其他适合的蚀刻工艺。在一些实施例，蚀刻工艺所使用的蚀刻剂包含碳、氟或其他适合的蚀刻气体。例如，蚀刻工艺所使用的蚀刻剂可包含四氟化碳(CF4)、三氟化碳(CH3F)，六氟丁二烯(C4F6)或其他适合的蚀刻气体。
在一些实施例，如图2G及图3G所示，露出源/漏极结构170a的第一表面S1后，沉积金属层220于掩模结构210、栅极间隙物150、源/漏极结构170a及鳍间隙物160上方。金属层220包含钛、钴、钨、镍或其他适合的金属材料，或由上述材料形成。金属层210通过使用PVD工艺(例如为溅镀工艺)、CVD工艺、旋转涂布工艺，其他适合的工艺或上述组合形成。
在一些实施例，如图3G所示，源/漏极结构170a的第一表面S1被金属层220完全覆盖。在一些实施例，如图3G所示，金属层220并未形成在源/漏极结构170a的第二表面S2上。
在一些实施例，如图2H及图3H所示，沉积金属层220后，形成硅化物(salicide或silicide)层230于源/漏极结构170a上方。在一些实施例，沉积金属层220于源/漏极结构170a上方后，执行退火工艺。接下来，金属层220与源/漏极结构170a反应，以形成硅化物层230于金属层220和源/漏极结构170a之间的界面。如图2H及图3H所示，金属层220未反应的部分留在隔离部件120、掩模结构210、栅极间隙物150的侧壁和鳍间隙物160的侧壁上。
在一些实施例，如图2H及图3H所示，源/漏极结构170a的第一表面S1被硅化物层230完全地覆盖且环绕。在一些实施例，如图3H所示，硅化物层230覆盖鳍结构110a的上表面。如图3H所示，硅化物层230具有第三表面S3，上述第三表面S3由鳍结构110的侧壁向外延伸朝向另一个鳍结构110a的侧壁。在一些实施例，硅化物层230延伸至鳍间隙物160。在一些实施例，源/漏极结构170a的上表面被硅化物层230完全覆盖。
更具体而言，第一表面S1被硅化物层230连续地环绕。在一些实施例，源/漏极结构170a的上表面被硅化物层230环绕。在一些实施例，硅化物层230并未形成在源/漏极结构170a的第二表面S2上，且源/漏极结构170a的第二表面S2未被硅化物层230覆盖。在一些实施例，如图3H所示，硅化物层230邻接鳍间隙物160。由于硅化物层230的第三表面S3的轮廓与源/漏极结构170a的轮廓相似，硅化物层230可以提供更多的面积与后续形成的接触物电性连接。在一些实施例，硅化物层230的厚度介于约5nm至约7nm的范围间。
在一些实施例，如图2I及图3I所示，形成硅化物层230后，移除金属层220剩下未与源/漏极结构170a反应的部分。金属层220剩下未反应的部分可通过蚀刻工艺移除，例如湿蚀刻工艺、干蚀刻工艺、一或多个其他适合的工艺，或上述组合。在一些实施例，如图2I及图3I所示，移除金属层220后，露出硅化物层230的第三表面S3。在一些实施例，如图2I所示，硅化物层230的第三表面S3具有第二宽度W2，第二宽度W2大抵上与第一宽度W1相同。在一些实施例，如图2I所示，硅化物层230延伸至栅极间隙物150。在一些实施例，如图2I所示，硅化物层230邻接栅极间隙物150。
在一些实施例，如图2J及图3J所示，移除金属层220未反应的部分后，沉积覆盖层240。覆盖层240覆盖第三表面S3，并且环绕硅化物层230。在一些实施例，覆盖层240直接接触硅化物层230。
覆盖层240可包含绝缘材料，其包含四族元素、五族元素和/或六族元素。在一些实施例，覆盖层240由氮化硅、氮氧化硅、碳化硅、碳氧化硅(SiOC)或上述组合形成。可在本公开实施例作各种变化和/或调整。在其他实施例，覆盖层240并未形成。
在一些实施例，如图2J及图3J所示，覆盖层240邻接硅化物层230和栅极间隙物150。在一些实施例，如图3J所示，源/漏极结构170a通过硅化物层230与覆盖层240分隔。
在一些实施例，如图2K及图3K所示，沉积覆盖层240后，沉积第一介电层250。第一介电层250环绕且覆盖源/漏极结构170a，且位于两个栅极结构200之间。
在一些实施例，第一介电层250包含氧化硅、氮氧化硅、硼硅酸盐玻璃(Boro-Silicate Glass,BSG)、磷酸硅酸盐玻璃(Phospho-Silicate Glass,PSG)、硼掺杂磷酸硅酸盐玻璃(Boron-Doped Phospho-Silicate Glass,BPSG)、氟硅酸盐玻璃(fluorinatedsilicate glass,FSG)、低介电常数材料、多孔介电材料、其他适合的介电材料，或上述组合。可选择第一介电层250的材料，以减小相邻的导电部件之间的传导延迟(propagationdelay)。在一些实施例，第一介电层250通过流动式CVD工艺、旋转涂布工艺、ALD工艺、PVD工艺、其他适合的工艺，或上述组合沉积。在一些实施例，沉积工艺的温度小于约450℃，且大于约20℃，以减小硅化物层230受到损害的风险。
接下来，可薄化第一介电层250直到露出栅极结构200。然后，移除了掩模结构210和覆盖层240位于栅极结构200及栅极间隙物150上方的部分。在一些实施例，执行平坦化工艺以薄化第一介电层250。平坦化工艺可包含CMP工艺、研磨工艺、蚀刻工艺或上述组合。在一些实施例，蚀刻工艺包含干蚀刻工艺、湿蚀刻工艺或其他适合的蚀刻工艺。在一些实施例，如图2K所示，薄化第一介电层250，直到露出栅极结构200的栅极电极204。
在一些实施例，如图2L及图3L所示，沉积第一介电层250后，沉积第二介电层260于第一介电层250上方，并覆盖栅极结构200。
在一些实施例，第二介电层260包含氧化硅、氮氧化硅、BSG、PSG、BPSG、FSG、低介电常数材料、多孔介电材料、其他适合的介电材料，或上述组合。可选择第二介电层260的材料，以减小相邻的导电部件之间的传导延迟。在一些实施例，第二介电层260通过使用CVD工艺、旋转涂布工艺、ALD工艺、PVD工艺、其他适合的工艺或上述组合而沉积。
在一些实施例，如图2M及图3M所示，沉积第二介电层260后，在第一介电层250及第二介电层260内形成沟槽(或开口)T1。沟槽T1可沿着X轴(如图1所示)延伸，且排列的方向大抵上平行于Y轴(如图1所示)。在一些实施例，沟槽T1贯穿第一介电层250、第二介电层260及覆盖层240，以露出硅化物层230的第三表面S3。
如图2M及图3M所示，沟槽T1具有倒锥形(倒梯形)轮廓，在一些实施例。倒锥形轮廓具有大于底部宽度的顶部宽度。更具体而言，沟槽T1在顶部朝向底部的方向逐渐变窄。在一些实施例，沿第二介电层260朝向第一介电层250的方向，沟槽T1逐渐变窄。在一些实施例，沟槽T1的侧壁和底部表面之间的角度介于约91度至约110度的范围间。在一些实施例，如图2M所示，沟槽T1的底部表面具有第三宽度W3，其小于第一宽度W1及第二宽度W2。
在一些实施例，使用蚀刻工艺来移除第二介电层260、第一介电层250及覆盖层240的一部分，以形成沟槽T1。蚀刻工艺可为各向异性蚀刻工艺。在一些实施例，蚀刻工艺包含干蚀刻工艺(例如等离子体蚀刻工艺)或其他适合的蚀刻工艺。在一些实施例，蚀刻工艺使用的蚀刻剂包含碳、氟或其他适合的蚀刻气体。例如，蚀刻工艺使用的蚀刻剂可包含四氟化碳、三氟化碳，六氟丁二烯或其他适合的蚀刻气体。
在一些实施例，在执行蚀刻第一介电层250、第二介电层260和覆盖层240的蚀刻工艺的期间，蚀刻了一部分的硅化物层230，且并未蚀刻源/漏极结构170a。更具体而言，在执行蚀刻第一介电层250、第二介电层260和覆盖层240的蚀刻工艺的期间，蚀刻了硅化物层230，而源/漏极结构170a被硅化物层230覆盖。由于在蚀刻工艺的期间并未蚀刻源/漏极结构170a，可避免源/漏极结构170的材料损耗。因此，改善半导体装置结构的效能。
在一些实施例，如图2N及图3N所示，形成沟槽T1后，形成多个沟槽T2于栅极结构200上方。如图2N所示，沟槽T2穿过第二介电层260，并露出栅极电极204的上表面。在一些实施例，沟槽T2的形成方法与沟槽T1的形成方法相同或相似。在一些实施例，沟槽T2具有倒锥形(倒梯形)轮廓，且在沿着由第二介电层260朝向栅极结构200的方向，沟槽T2逐渐变窄。
在其他实施例，形成沟槽T1后，形成沟槽T2。在其他实施例，形成沟槽T2后，形成沟槽T1。
在一些实施例，如图2N及图3N所示，形成硅化物(salicide或silicide)层270于栅极结构200上方。形成沟槽T2后，沉积金属层(未示出)于沟槽T2内，且执行退火工艺使得金属层形成硅化物层270。在一些实施例，硅化物层270的材料与硅化物层230的材料相同或相似。
在一些实施例，如图2O及图3O所示，将导电材料填入沟槽T1及沟槽T2内，以形成接触物280和290，并形成半导体装置结构1000。如图2O所示，接触物280电性连接至源/漏极结构170a，且接触物290电性连接至栅极结构200。在一些实施例，导电材料层沉积在第二介电层260上方，并填入沟槽T1及T2。之后执行平坦化工艺来移除导电材料层之位于沟槽T1及T2外面的部分。然后，导电材料层留在沟槽T1及T2内的剩余部分分别形成了接触物280及290。在一些实施例，接触物280邻接硅化物层230。在一些实施例，接触物280通过第一介电层250与栅极间隙物150分隔。
在一些实施例，导电材料层由钨、铝、铜、金、钯、钛、其他适合的材料，或上述组合形成。在一些实施例，导电材料层通过使用CVD工艺、PVD工艺、电镀工艺、无电镀工艺、其他适合的工艺，或上述组合沉积。
在一些实施例，如图2O所示，接触物280的底部表面具有宽度W3，其小于第一宽度W1及第二宽度W2。在一些实施例，硅化物层230的第三表面S3的一部分并未与接触物280直接接触，而是与覆盖层240接触。在一些实施例，如图2O所示，一部分的硅化物层230位于接触物280及源/漏极结构170a之间，硅化物层230其他的部分位于覆盖层240及源/漏极结构170a之间。在一些实施例，如图2O所示，一部分的覆盖层240位于硅化物层230和第一介电层250之间。在一些实施例，如图3O所示，硅化物层230具有第一部分，上述第一部分与接触物280直接接触，并具有第二部分，其覆盖源/漏极结构170a之未与接触物280重叠的侧壁。
在其他实施例，用分开的工艺形成接触物280和290。例如，接触物280可在形成接触物290的之前或之后形成。
图4是根据一些实施例，半导体装置结构2000的剖面示意图。除了半导体装置结构2000的源/漏极结构170b形成在一个鳍结构110a上方以外，半导体装置结构2000可与上述的半导体装置结构1000相同或相似。
在一些实施例，如图4所示，硅化物层230由鳍结构110a的一个侧壁延伸至相同的鳍结构110a的另一个侧壁。更具体而言，如图4所示，硅化物层230完整地覆盖或包围源/漏极结构170b的第一表面S1。
图5是根据一些实施例，半导体装置结构3000的剖面示意图。除了半导体装置结构3000的鳍结构110b并未被凹蚀，且一部分的鳍结构110b嵌入于源/漏极结构170c以外，半导体装置结构3000可与上述的半导体装置结构1000相同或相似。
在一些实施例，如图5所示，源/漏极结构170c的第一表面S1的一部分在鳍结构110b的上表面T的下方，而另一部分在鳍结构110b的上表面T的上方。在一些实施例，如图5所示，一部分的硅化物层230低于鳍结构110b的上表面T，而另一部分的硅化物层230高于鳍结构110b的上表面T。
本公开实施例形成的半导体装置结构具有较大面积的硅化物层与接触物电性连接。由于在形成硅化物层的期间，源/漏极结构并未被蚀刻，借此避免了因源/漏极结构的流失所导致的源/漏极结构的轮廓受损。因此，改善了半导体装置结构的电阻及增益值。
本公开实施例不只可应用在N型或P型晶体管的半导体装置结构，亦可应用在复合式晶体管的半导体装置结构或其他适合的装置。本公开实施例并不限于此，并且可应用在任何适合的技术世代的制造工艺。上述技术世代包含例如16nm节点、10nm节点、7nm节点或其他适合的节点。
根据本公开一些实施例，提供半导体装置结构的制造方法。上述方法包含形成鳍结构于基底上。上述方法亦包含形成栅极结构于鳍结构上。上述方法还包含形成鳍间隙物于鳍结构的侧壁上及栅极间隙物于栅极结构的侧壁上。此外，上述方法包含形成源/漏极结构于鳍结构上及沉积虚置材料层以覆盖源/漏极结构。上述方法亦包含移除虚置材料层以露出源/漏极结构及鳍间隙物。上述方法还包含形成硅化物层于源/漏极结构及鳍间隙物上，且形成接触物于硅化物层上。虚置材料层包含锗、非晶硅或旋涂碳。
在一些实施例，上述方法还包含：沉积介电层于硅化物层上、蚀刻介电层以形成沟槽露出硅化物层，以及形成接触物于沟槽内。
在一些实施例，在形成沟槽的期间，蚀刻一部分的硅化物层。
在一些实施例，上述方法还包含：沉积金属层于源/漏极结构及鳍间隙物上、执行退火工艺以形成硅化物层于源/漏极结构上方，以及移除鳍间隙物上方的金属层。
在一些实施例，通过执行干蚀刻工艺，以移除虚置材料层，且执行干蚀刻工艺时，使用蚀刻剂，其包含四氟化碳(CF4)、三氟化碳(CH3F)，六氟丁二烯(C4F6)。
在一些实施例，形成硅化物层后，硅化物层邻接鳍间隙物。
在一些实施例，一部的硅化物层延伸至鳍间隙物的侧壁上，且未直接接触接触物。
在一些实施例，提供半导体装置结构的制造方法。上述方法包含形成栅极结构于基底上。上述方法亦包含形成与栅极结构相邻的源/漏极结构。上述方法还包含形成硅化物层以覆盖源/漏极结构。此外，上述方法包含形成第一介电层于硅化物层上。上述方法亦包含蚀刻介电层以形成沟槽，而露出硅化物层。上述方法还包含形成接触物于沟槽内。
在一些实施例，还包含：形成虚置材料层以覆盖源/漏极结构、形成虚置材料层后，以金属栅极结构取代栅极结构，以及移除虚置材料层以露出源/漏极结构。
在一些实施例，一部分的硅化物层并未直接接触接触物。
在一些实施例，形成硅化物层还包含：形成金属层于栅极间隙物和源/漏极结构上方，以及执行退火工艺以形成该硅化物层于源/漏极结构上方。
在一些实施例，上述方法还包含：在形成硅化物层后，移除位于栅极间隙物上方的金属层。
在一些实施例，上述方法还包含：形成第一鳍结构和第二鳍结构于基底上方，其中源/漏极结构覆盖第一鳍结构和第二鳍结构两者。
在一些实施例，提供半导体装置结构。上述半导体装置结构包含位于基底上的鳍结构。上述半导体装置结构亦包含位于鳍结构上的第一栅极结构和第二栅极结构。上述半导体装置结构还包含第一栅极间隙物及第二栅极间隙物，其分别位于第一栅极结构和第二栅极结构的侧壁上。此外，上述半导体装置结构包含位于基底上的源/漏极结构，且半导体装置结构亦包含位于源/漏极结构上方的硅化物层。硅化物层由第一栅极间隙物延伸至第二栅极间隙物。
在一些实施例，上述半导体装置结构还包含：位于硅化物层的第一部分的上方的接触物。
在一些实施例，硅化物层的第二部分覆盖源/漏极结构之未与接触物重叠的侧壁。
在一些实施例，上述半导体装置结构还包含：位于鳍结构的侧壁上的鳍间隙物，其中硅化物层邻接鳍间隙物。
在一些实施例，上述半导体装置结构还包含：位于硅化物层上方的介电层，且上述介电层位于第一栅极结构和第二栅极结构之间、并包含位于硅化物层上方的接触物，其中接触物通过介电层与第一栅极间隙物隔开。
在一些实施例，硅化物层具有第一宽度，且接触物的底部表面具有第二宽度，其中第二宽度小于第一宽度。
在一些实施例，硅化物层直接接触第一栅极间隙物和第二栅极间隙物。
以上叙述许多实施例的特征，使本领域技术人员能够清楚理解本公开的概念。本领域技术人员能够理解，其可利用本公开公开内容作为基础，以设计或更动其他工艺及结构而完成相同于上述实施例的目的和/或达到相同于上述实施例的优点。本领域技术人员亦能够理解，不脱离本公开的构思和范围的等效构造可在不脱离本公开的构思和范围内作各种的更动、替代与润饰。

Claims (1)

1.一种半导体装置结构的制造方法，包括：
形成一鳍结构于一基底上；
形成一栅极结构于该鳍结构上；
形成鳍间隙物于该鳍结构的侧壁上及栅极间隙物于该栅极结构的侧壁上；
形成一源/漏极结构于该鳍结构上；
沉积一虚置材料层以覆盖该源/漏极结构；
移除该虚置材料层以露出该源/漏极结构及该鳍间隙物；
形成一硅化物层于该源/漏极结构及该鳍间隙物上；以及
形成一接触物于该硅化物层上，
其中该虚置材料层包括锗、非晶硅或旋涂碳。
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