CN109698168B - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

Info

Publication number
CN109698168B
CN109698168B CN201711121672.8A CN201711121672A CN109698168B CN 109698168 B CN109698168 B CN 109698168B CN 201711121672 A CN201711121672 A CN 201711121672A CN 109698168 B CN109698168 B CN 109698168B
Authority
CN
China
Prior art keywords
substrate
electronic package
antenna
support
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201711121672.8A
Other languages
English (en)
Other versions
CN109698168A (zh
Inventor
周世民
陈汉宏
林荣政
余国华
林长甫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN109698168A publication Critical patent/CN109698168A/zh
Application granted granted Critical
Publication of CN109698168B publication Critical patent/CN109698168B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/12Supports; Mounting means
    • H01Q1/22Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/144Stacked arrangements of planar printed circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/368Assembling printed circuits with other printed circuits parallel to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/0243Printed circuits associated with mounted high frequency components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04Assemblies of printed circuits
    • H05K2201/042Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04Assemblies of printed circuits
    • H05K2201/049PCB for one component, e.g. for mounting onto mother PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09063Holes or slots in insulating substrate not used for electrical connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10545Related components mounted on both sides of the PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036Permanent spacer or stand-off in a printed circuit or printed circuit assembly

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Waveguide Aerials (AREA)
  • Details Of Aerials (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

一种电子封装件及其制法,通过将天线板堆叠于线路板上,并于该天线板与线路板之间形成固接该天线板与线路板的支撑体,以于封装制程中,通过该支撑体使该天线板与线路板之间的距离保持不变,确保该天线板的天线功能正常,进而提升产品的良率。

Description

电子封装件及其制法
技术领域
本发明关于一种电子封装件,特别是关于一种具有天线结构的电子封装件。
背景技术
目前无线通讯技术已广泛应用于各式各样的消费性电子产品以利接收或发送各种无线讯号,而为满足消费性电子产品的外观设计需求,无线通讯模组的制造与设计朝轻、薄、短、小的需求作开发,其中,平面天线(Patch Antenna)因具有体积小、重量轻与制造容易等特性而广泛利用在如手机(cell phone)的电子产品的无线通讯模组中。
如图1所示,其为悉知无线通讯模组1的剖面示意图。该无线通讯模组1于一下侧设有半导体晶片11的线路板10的上侧通过多个焊锡凸块18堆叠一具有天线(图略)的基板12,且该线路板10具有接地片(图略)及天线回馈线路(antenna feed lines)(图略),并于该线路板10下方形成多个焊球19,其中,该线路板10与该基板12之间需于特定区域定义为空旷区A(即该些焊锡凸块18环绕的区域,其内部不可有点胶或模压填入物),且需控制该线路板10与该基板12之间的距离L,以确保该天线与该半导体晶片之间的传接讯号品质。
然而,悉知无线通讯模组1中,当该线路板10与该基板12堆叠后,会翻转整体结构(可将图1上下颠倒视之)以回焊该些焊球19,此时该些焊锡凸块18会呈熔融状态,故该基板12会因受重力而下降,以拉伸该些焊锡凸块18,导致该线路板10与该基板12之间的距离L变大,因而影响该天线的功能,进而造成产品的良率下降。
因此,如何克服上述悉知技术的问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述悉知技术的缺失,本发明提供一种电子封装件及其制法,可提升产品的良率。
本发明的电子封装件,包括:第一基板,其具有天线结构;第二基板,其具有线路层且与该第一基板相堆叠;数导电元件,其设于该第一基板与第二基板之间,用以电性连接该第一基板与第二基板;以及至少一支撑体,其设于该第一基板与第二基板之间,用以固接但未电性连接该第一基板与第二基板。
本发明还提供一种电子封装件的制法,其包括:将具有天线结构的第一基板透过多个导电元件堆叠于具有线路层的第二基板上;以及形成至少一支撑体于该第一与第二基板之间,使该支撑体固接但未电性连接该第一基板与该第二基板。
前述的制法中,该支撑体的制程用于将胶材填入于该第一基板与该第二基板之间以接触该第一与第二基板,再使该胶材固化,以形成该支撑体。
前述的电子封装件及其制法中,该第一基板通过多个导电元件堆叠于该第二基板上并电性连接该第二基板。
前述的电子封装件及其制法中,该第一基板与第二基板之间所包围的区域由中心向外依序定义有空旷区、导接区及支撑区,该导电元件位于该导接区,该支撑体位于该支撑区。
前述的电子封装件及其制法中,该第一基板还具有至少一贯通的穿孔,且该支撑体对应该穿孔的位置。例如,该穿孔位于该第一基板的外围区域。进一步,该穿孔连通该第一基板的侧面。
前述的电子封装件及其制法中,该支撑体凸出该第一基板的侧面。
前述的电子封装件及其制法中,该第一基板的宽度小于该第二基板的宽度。
前述的电子封装件及其制法中,该支撑体为绝缘材。
前述的电子封装件及其制法中,该支撑体未电性连接该第一基板与第二基板。
前述的电子封装件及其制法中,该支撑体为热固性胶材。
前述的电子封装件及其制法中,还包括设置电子元件于该第二基板上。例如,该第二基板具有相对的第一侧与第二侧,且该第一基板堆叠于该第一侧上,而该电子元件设置于该第二侧上。
前述的电子封装件及其制法中,该导电元件未电性连接该天线结构。
前述的电子封装件及其制法中,该第二基板还具有天线体。例如,该天线体与该线路层电性隔绝、或者该导电元件未电性连接该天线体。
由上可知,本发明的电子封装件及其制法中,通过该支撑体连接该第一与第二基板,使该第一与第二基板之间的距离保持不变,以于封装制程(如进行回焊制程)中,该第一基板不会因重力下降而拉伸该些导电元件,故相较于悉知技术,本发明的电子封装件不会因该第一与第二基板之间的距离变大而影响该天线结构的功能,因而能避免产品良率下降的问题。
附图说明
图1为悉知无线通讯模组的剖面示意图;
图2A至图2D为本发明的电子封装件的制法的剖面示意图;
图3A为图2C的第一基板的上视示意图;
图3B为图3A的另一实施例;以及
图4及图5为本发明的电子封装件的其它实施例的剖面示意图。
符号说明:
1 无线通讯模组
10 线路板
11 半导体晶片
12 基板
18 焊锡凸块
19,29 焊球
2 电子封装件
20 电子元件
200 导电凸块
21,51 第一基板
21a 第一表面
21b 第二表面
21c,51c 侧面
210,310 穿孔
211 天线结构
212 第一电性接点
22 第二基板
22a 第一侧
22b 第二侧
220 接地片
221 线路层
222 第二电性接点
223 植球垫
224 天线体
23 支撑体
28 导电元件
A 空旷区
B 导接区
C 支撑区
D,T 宽度
L 距离
S 区域。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“第一”、“第二”、及“一”等用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2A至图2D为本发明的电子封装件2的制法的剖面示意图。
如图2A所示,堆叠一第一基板21与一第二基板22,其中,该第一基板21具有相对的第一表面21a与第二表面21b、邻接该第一与第二表面21a,21b的侧面21c及至少一连通该第一与第二表面21a,21b的穿孔210。
于本实施例中,该第一基板21为天线板,其设有天线结构211及多个第一电性接点212,且该天线结构211为线路型天线,其与该第一电性接点212电性隔绝。应可理解地,该第一基板21也可为其它类型的天线板,并不限于上述。
此外,该第二基板22为线路板,其定义有相对的第一侧22a与第二侧22b,且具有天线体224、接地片220及电性连接该接地片220的线路层221,其中,该天线体224为线路型天线,其与该线路层221(或该接地片220)电性隔绝。例如,该线路层221包含多个第二电性接点222与多个植球垫223。应可理解地,该第二基板22也可为其它承载晶片的承载件,并不限于上述。
又,该穿孔210位于该第一基板21的外围区域而未连通该侧面21c,如图3A所示的圆形;或者,该穿孔310连通该第一基板21的侧面21c,如图3B所示的半圆形。应可理解地,有关该穿孔的形状与配置可依需求设计,并不限于上述。
如图2B所示,将该第一基板21以其第一表面21a通过多个导电元件28堆叠于该第二基板22的第一侧22a。
于本实施例中,该些导电元件28接合于该第一电性接点212与第二电性接点222之间,以电性连接该第一基板21与该第二基板22,且该天线结构211感应该天线体224,以讯号传输于两者之间。
此外,该导电元件28例如为铜柱、焊锡材或其它构造,并无特别限制。
又,该导电元件28无法电性导通该天线结构211及天线体224,但该导电元件28可电性连接该接地片220或虚垫(dummy pad),即该第一电性接点212或第二电性接点222作为无电性功能的虚垫。
另外,如图2B及图3A所示,该第一基板21与该第二基板22之间所包围的区域S由中心向外依序可定义有空旷区A、导接区B及支撑区C,其中,该空旷区A内不可有点胶、模压填入物或其它物体,以确保该天线结构211的传接讯号品质,且该导接区B用以布设该些导电元件28,以令该些导电元件28环绕该空旷区A,而该支撑区C环绕该导接区B。
如图2C所示,经由该穿孔210将支撑体23形成于该第一基板21的第一表面21a与该第二基板22的第一侧22a之间的支撑区C,使该支撑体23固接该第一基板21与该第二基板22,且该支撑体23未电性连接该第一与第二基板21,22。
于本实施例中,该支撑体23为如胶体的绝缘材,且令该支撑体23外露于该穿孔210或外露于该第一基板21的第二表面21b。例如,该支撑体23的制程以点胶针将热固性胶材经由该穿孔210灌入于该第一基板21与该第二基板22之间以接触该第一基板21的第一表面21a与第二基板22的第一侧22a(还可接触该穿孔210的壁面),再加热使该热固性胶材固化,以作为该支撑体23。
此外,当该穿孔310呈现如图3B所示的半圆形时,可使用较大的点胶针头,以降低成本。
又,该支撑体23可部分位于该穿孔210中。
如图2D所示,将该第一基板21与该第二基板22的位置上、下翻转,再于该第二基板22的第二侧22b上设置至少一电子元件20,且于该植球垫223上形成多个如焊球29的导电元件,并回焊该些焊球29以接置如电路板或另一线路板的电子结构,进而制得电子封装件2。
于本实施例中,该电子元件20设于该第二基板22的第二侧22b,其为主动元件、被动元件或其二者组合等,其中,该主动元件为例如半导体晶片,且该被动元件为例如电阻、电容及电感。例如,该电子元件20通过多个如焊锡材料的导电凸块200以覆晶方式电性连接该线路层221;或者,该电子元件20可通过多个焊线(图略)以打线方式电性连接该线路层221;抑或,该电子元件20可直接接触该线路层221以电性连接该线路层221。然而,有关该电子元件20电性连接该第二基板22的方式不限于上述。
此外,该电子元件20虽未设于该第一基板21与该第二基板22之间,但有关该电子元件的配置方式繁多(如设于该第二基板22的第一侧22a),并不限于上述。
又,如图4所示,当使用图3B所示的穿孔310连通该第一基板21的侧面21c时,该支撑体23可凸出该第一基板21的侧面21c(如接触该第一基板21的侧面21c与该穿孔310的壁面)或不凸出该第一基板21的侧面21c(图略)。
另外,如图5所示,也可令该第一基板51的宽度T小于该第二基板22的宽度D,使该支撑体23凸出该第一基板51的侧面51c(如接触该第一基板21的侧面21c),藉此无需制作该穿孔210,310。
本发明的电子封装件的制法主要通过该支撑体23连接该第一基板21,51与该第二基板22,使该第一基板21,51与该第二基板22之间的距离L保持不变,以于回焊该些焊球29或后续高温烘烤制程时,该第一基板21,51不会因重力下降而拉伸该些熔融状态的导电元件28,故相较于悉知技术,本发明的电子封装件2不会因该第一基板21,51与该第二基板22之间的距离L变大而影响该天线结构211与天线体224的功能,因而能有效控制天线品质,进而能提高产品良率。
本发明还提供一种电子封装件2,其包括:第一基板21,51、第二基板22以及至少一支撑体23。
所述的第一基板21,51具有天线结构211。
所述的第二基板22具有线路层221且与该第一基板21,51相堆叠。
所述的支撑体23连接该第一基板21,51与该第二基板22并位于该第一基板21,51与该第二基板22之间,其中,该支撑体23未电性连接该第一基板21,51与该第二基板22。
于一实施例中,该第一基板21,51通过多个导电元件28堆叠于该第二基板22上。
于一实施例中,该第一基板21还具有至少一贯通的穿孔210,310,且该支撑体23对应该穿孔210,310的位置。例如,该穿孔210,310位于该第一基板21的外围区域,进一步,该穿孔310连通该第一基板21的侧面21c。
于一实施例中,该支撑体23凸出该第一基板21,51的侧面
21c,51c。
于一实施例中,该第一基板51的宽度T小于该第二基板22的宽度D。
于一实施例中,该支撑体23为绝缘材。
于一实施例中,该支撑体23未电性连接该第一基板21,51与第二基板22。
于一实施例中,该支撑体23为热固性胶材。
于一实施例中,所述的电子封装件2还包括至少一电子元件20,其设于该第二基板22上。例如,该第二基板22具有相对的第一侧22a与第二侧22b,且该第一基板22堆叠于该第一侧22a上,而该电子元件20设置该第二侧22b上。
于一实施例中,该导电元件28未电性连接该天线结构211。
于一实施例中,该第二基板22还具有天线体224。例如,该天线体224与该线路层221为电性隔绝、或者该导电元件28未电性连接该天线体224。
综上所述,本发明的电子封装件及其制法,通过该支撑体的设计,使该第一与第二基板之间的距离于高温制程后仍可保持不变,故本发明的电子封装件能确保该天线结构的功能正常,因而能确保产品良率符合预期。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何所属领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。

Claims (29)

1.一种电子封装件,其特征为,该电子封装件包括:
第一基板,其具有天线结构;
第二基板,其具有线路层及感应该天线结构的天线体且与该第一基板相堆叠,其中,该第一基板与该第二基板之间所包围的区域由中心向外依序定义有空旷区、导接区及支撑区,该天线结构对应该空旷区设置,以讯号传输于该天线结构与该天线体之间;
多个导电元件,其设于该第一基板与第二基板之间的该导接区;以及
至少一支撑体,其设于该第一基板与第二基板之间的该支撑区,用以固接该第一基板与第二基板。
2.根据权利要求1所述的电子封装件,其特征为,该第一基板还具有至少一贯通的穿孔,且该支撑体对应该穿孔的位置。
3.根据权利要求2所述的电子封装件,其特征为,该穿孔位于该第一基板的外围区域。
4.根据权利要求3所述的电子封装件,其特征为,该穿孔连通该第一基板的侧面。
5.根据权利要求1所述的电子封装件,其特征为,该支撑体凸出该第一基板的侧面。
6.根据权利要求1所述的电子封装件,其特征为,该第一基板的宽度小于该第二基板的宽度。
7.根据权利要求1所述的电子封装件,其特征为,该支撑体为绝缘材。
8.根据权利要求1所述的电子封装件,其特征为,该支撑体未电性连接该第一基板与第二基板。
9.根据权利要求1所述的电子封装件,其特征为,该支撑体为热固性胶材。
10.根据权利要求1所述的电子封装件,其特征为,该电子封装件还包括电子元件,其设于该第二基板上。
11.根据权利要求10所述的电子封装件,其特征为,该第二基板具有相对的第一侧与第二侧,且该第一基板堆叠于该第一侧上,而该电子元件设置于该第二侧上。
12.根据权利要求1所述的电子封装件,其特征为,该导电元件未电性连接该天线结构。
13.根据权利要求1所述的电子封装件,其特征为,该天线体与该线路层为电性隔绝。
14.根据权利要求1所述的电子封装件,其特征为,该导电元件未电性连接该天线体。
15.一种电子封装件的制法,其特征为,该制法包括:
将具有天线结构的第一基板透过多个导电元件堆叠于具有线路层及天线体的第二基板上,其中,该天线体感应该天线结构,该第一基板与该第二基板之间所包围的区域由中心向外依序定义有空旷区、导接区及支撑区,该天线结构对应该空旷区设置,以讯号传输于该天线结构与该天线体之间,该导电元件位于该导接区;以及
接着,形成至少一支撑体于该第一基板与第二基板之间的该支撑区,使该支撑体固接该第一基板与该第二基板。
16.根据权利要求15所述的电子封装件的制法,其特征为,该第一基板还具有至少一贯通的穿孔,且该支撑体对应该穿孔的位置。
17.根据权利要求16所述的电子封装件的制法,其特征为,该穿孔位于该第一基板的外围区域。
18.根据权利要求17所述的电子封装件的制法,其特征为,该穿孔连通该第一基板的侧面。
19.根据权利要求15所述的电子封装件的制法,其特征为,该支撑体凸出该第一基板的侧面。
20.根据权利要求15所述的电子封装件的制法,其特征为,该第一基板的宽度小于该第二基板的宽度。
21.根据权利要求15所述的电子封装件的制法,其特征为,该支撑体为绝缘材。
22.根据权利要求15所述的电子封装件的制法,其特征为,该支撑体未电性连接该第一基板与第二基板。
23.根据权利要求15所述的电子封装件的制法,其特征为,该支撑体为热固性胶材。
24.根据权利要求15所述的电子封装件的制法,其特征为,该制法还包括设置电子元件于该第二基板上。
25.根据权利要求24所述的电子封装件的制法,其特征为,该第二基板具有相对的第一侧与第二侧,且该第一基板堆叠于该第一侧上,而该电子元件设置于该第二侧上。
26.根据权利要求15所述的电子封装件的制法,其特征为,该支撑体的制程用于将胶材填入于该第一基板与该第二基板之间以接触该第一与第二基板,再使该胶材固化,以形成该支撑体。
27.根据权利要求15所述的电子封装件的制法,其特征为,该导电元件未电性连接该天线结构。
28.根据权利要求15所述的电子封装件的制法,其特征为,该天线体与该线路层为电性隔绝。
29.根据权利要求15所述的电子封装件的制法,其特征为,该导电元件未电性连接该天线体。
CN201711121672.8A 2017-10-20 2017-11-14 电子封装件及其制法 Active CN109698168B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW106136127A TWI667743B (zh) 2017-10-20 2017-10-20 電子封裝件及其製法
TW106136127 2017-10-20

Publications (2)

Publication Number Publication Date
CN109698168A CN109698168A (zh) 2019-04-30
CN109698168B true CN109698168B (zh) 2021-01-22

Family

ID=66170173

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711121672.8A Active CN109698168B (zh) 2017-10-20 2017-11-14 电子封装件及其制法

Country Status (3)

Country Link
US (1) US11380978B2 (zh)
CN (1) CN109698168B (zh)
TW (1) TWI667743B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202103284A (zh) * 2019-07-11 2021-01-16 矽品精密工業股份有限公司 電子封裝件

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633535A (en) * 1995-01-27 1997-05-27 Chao; Clinton C. Spacing control in electronic device assemblies
US20150340765A1 (en) * 2014-05-20 2015-11-26 International Business Machines Corporation Integration of area efficient antennas for phased array or wafer scale array antenna applications

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0964519A (ja) * 1995-08-22 1997-03-07 Hitachi Ltd 電子部品の実装方法
EP1168445A1 (en) * 1999-12-27 2002-01-02 Mitsubishi Denki Kabushiki Kaisha Integrated circuit
CN1316858C (zh) * 2001-04-27 2007-05-16 日本电气株式会社 高频电路基板及其制造方法
JP2004119909A (ja) * 2002-09-30 2004-04-15 Kyocera Corp 配線基板
US6940408B2 (en) * 2002-12-31 2005-09-06 Avery Dennison Corporation RFID device and method of forming
TWI255560B (en) * 2004-01-16 2006-05-21 Siliconware Precision Industries Co Ltd Semiconductor package with photosensitive chip and fabrication method thereof
US7242084B2 (en) * 2005-05-27 2007-07-10 Intel Corporation Apparatuses and associated methods for improved solder joint reliability
DE102005026243B4 (de) * 2005-06-07 2018-04-05 Snaptrack, Inc. Elektrisches Bauelement und Herstellungsverfahren
CN1992239A (zh) * 2005-12-26 2007-07-04 力成科技股份有限公司 球栅阵列封装结构
US7830312B2 (en) * 2008-03-11 2010-11-09 Intel Corporation Wireless antenna array system architecture and methods to achieve 3D beam coverage
US7830301B2 (en) * 2008-04-04 2010-11-09 Toyota Motor Engineering & Manufacturing North America, Inc. Dual-band antenna array and RF front-end for automotive radars
US8058714B2 (en) * 2008-09-25 2011-11-15 Skyworks Solutions, Inc. Overmolded semiconductor package with an integrated antenna
US20170117214A1 (en) * 2009-01-05 2017-04-27 Amkor Technology, Inc. Semiconductor device with through-mold via
US8072384B2 (en) * 2009-01-14 2011-12-06 Laird Technologies, Inc. Dual-polarized antenna modules
JP4858559B2 (ja) * 2009-03-18 2012-01-18 株式会社デンソー レーダ装置
US8558637B2 (en) * 2010-05-12 2013-10-15 Mediatek Inc. Circuit device with signal line transition element
KR20120007840A (ko) * 2010-07-15 2012-01-25 삼성전자주식회사 두 개의 패키지 기판 사이에 배치된 스페이서를 가진 pop 반도체 패키지
US8907469B2 (en) * 2012-01-19 2014-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package assembly and method of forming the same
US9153542B2 (en) * 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US9196951B2 (en) * 2012-11-26 2015-11-24 International Business Machines Corporation Millimeter-wave radio frequency integrated circuit packages with integrated antennas
US8928134B2 (en) * 2012-12-28 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package bonding structure and method for forming the same
US9172131B2 (en) * 2013-03-15 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor structure having aperture antenna
US9520635B2 (en) * 2013-03-22 2016-12-13 Peraso Technologies Inc. RF system-in-package with microstrip-to-waveguide transition
US20140367854A1 (en) * 2013-06-17 2014-12-18 Broadcom Corporation Interconnect structure for molded ic packages
TWI520285B (zh) * 2013-08-12 2016-02-01 矽品精密工業股份有限公司 半導體封裝件及其製法
US9806422B2 (en) * 2013-09-11 2017-10-31 International Business Machines Corporation Antenna-in-package structures with broadside and end-fire radiations
US9819098B2 (en) * 2013-09-11 2017-11-14 International Business Machines Corporation Antenna-in-package structures with broadside and end-fire radiations
US9634641B2 (en) * 2013-11-06 2017-04-25 Taiyo Yuden Co., Ltd. Electronic module having an interconnection substrate with a buried electronic device therein
TWI556332B (zh) * 2014-03-17 2016-11-01 矽品精密工業股份有限公司 封裝堆疊結構及其製法
TWI529883B (zh) * 2014-05-09 2016-04-11 矽品精密工業股份有限公司 封裝堆疊結構及其製法暨無核心層式封裝基板及其製法
US9620464B2 (en) * 2014-08-13 2017-04-11 International Business Machines Corporation Wireless communications package with integrated antennas and air cavity
WO2016063759A1 (ja) * 2014-10-20 2016-04-28 株式会社村田製作所 無線通信モジュール
US9597752B2 (en) * 2015-03-13 2017-03-21 Mediatek Inc. Composite solder ball, semiconductor package using the same, semiconductor device using the same and manufacturing method thereof
US20170040266A1 (en) * 2015-05-05 2017-02-09 Mediatek Inc. Fan-out package structure including antenna
US20160329299A1 (en) * 2015-05-05 2016-11-10 Mediatek Inc. Fan-out package structure including antenna
US9711459B2 (en) * 2015-07-20 2017-07-18 Qorvo Us, Inc. Multi-layer substrate with an embedded die
TWI611542B (zh) * 2016-08-24 2018-01-11 矽品精密工業股份有限公司 電子封裝結構及其製法
TWI601219B (zh) * 2016-08-31 2017-10-01 矽品精密工業股份有限公司 電子封裝件及其製法
US10468355B2 (en) * 2017-12-08 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. EMI Shielding structure in InFO package
US11024954B2 (en) * 2018-05-14 2021-06-01 Mediatek Inc. Semiconductor package with antenna and fabrication method thereof
US20190348747A1 (en) * 2018-05-14 2019-11-14 Mediatek Inc. Innovative air gap for antenna fan out package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633535A (en) * 1995-01-27 1997-05-27 Chao; Clinton C. Spacing control in electronic device assemblies
US20150340765A1 (en) * 2014-05-20 2015-11-26 International Business Machines Corporation Integration of area efficient antennas for phased array or wafer scale array antenna applications

Also Published As

Publication number Publication date
US20190123424A1 (en) 2019-04-25
TWI667743B (zh) 2019-08-01
US11380978B2 (en) 2022-07-05
CN109698168A (zh) 2019-04-30
TW201917834A (zh) 2019-05-01

Similar Documents

Publication Publication Date Title
CN106450659B (zh) 电子模块
US10438907B2 (en) Wireless package with antenna connector and fabrication method thereof
US20090032927A1 (en) Semiconductor substrates connected with a ball grid array
KR20160012589A (ko) 인터포저 기판을 갖는 반도체 패키지 적층 구조체
CN110828429B (zh) 电子封装件
EP3217429A1 (en) Semiconductor package assembly
US20180331027A1 (en) Electronic package and method for fabricating the same
US11869829B2 (en) Semiconductor device with through-mold via
CN108962878B (zh) 电子封装件及其制法
CN110896056B (zh) 电子封装件及其制法
TWI698046B (zh) 電子封裝件及其製法
US11101566B2 (en) Method for fabricating electronic package
CN109698168B (zh) 电子封装件及其制法
CN107622981B (zh) 电子封装件及其制法
TWI705549B (zh) 電子封裝件
CN103400826A (zh) 半导体封装及其制造方法
TWI789977B (zh) 電子裝置及其製造方法
US8546942B2 (en) Flip-chip semiconductor device having anisotropic electrical interconnection and substrate utilized for the package
CN112447690A (zh) 天线置顶的半导体封装结构
CN112216687A (zh) 电子封装件
KR100881024B1 (ko) 고주파 특성을 개선하는 칩 스케일 패키지 및 그 제조방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant