CN109686789A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN109686789A
CN109686789A CN201811210323.8A CN201811210323A CN109686789A CN 109686789 A CN109686789 A CN 109686789A CN 201811210323 A CN201811210323 A CN 201811210323A CN 109686789 A CN109686789 A CN 109686789A
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barrier layer
surface electrode
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平林康弘
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Denso Corp
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Abstract

本发明提供一种半导体装置，其具有半导体基板、上表面电极和下表面电极。半导体基板具有：与上表面电极接触的p型阳极区、与下表面电极接触的n型阴极区、以及位于阳极区与阴极区之间的漂移区。半导体基板还具有位于阳极区与漂移区之间的势垒区、以及在势垒区和上表面电极之间延伸的n型柱区。势垒区具有多层结构，所述多层结构包括n型第一势垒层、p型第二势垒层、以及n型第三势垒层，所述第二势垒层位于第一势垒层与第三势垒层之间。第一势垒层与阳极区相接，并且隔着柱区与上表面电极连接。

Description

半导体装置
技术领域
本说明书中公开的技术涉及一种半导体装置，特别是涉及一种具有二极管构造的半导体装置。
背景技术
日本特开2016-162897号公报中公开了一种具有二极管构造的半导体装置。该半导体装置具有半导体基板、设置在半导体基板的上表面的上表面电极、以及设置在半导体基板的位于上表面相对侧的下表面的下表面电极。半导体基板具有与上表面电极接触的p型阳极区、与下表面电极接触的n型阴极区、以及位于阳极区与阴极区之间并且载流子密度低于阴极区的n型漂移区。
该半导体装置还具有位于阳极区与漂移区之间的n型势垒区、以及在势垒区和上表面电极之间延伸且与上表面电极进行肖特基接触的n型柱区。势垒区的载流子密度高于漂移区的载流子密度。根据这一结构，由于正向偏置时从阳极区向漂移区注入的空穴被抑制，因此能够降低向反向偏置切换时产生的恢复电流。
另一方面，上述势垒区及柱区的存在有可能成为导致回滞现象的主要原因，该回滞现象为在向正向偏置切换时，与正向电压增加相对而正向电流的增加发生暂时延迟的现象。为了抑制所述回滞现象，优选降低势垒区的载流子密度。但是，如果降低势垒区的载流子密度，则会导致前述抑制空穴注入的效果降低。针对这一点，在日本特开2016-162897号公报记载的半导体装置中，使势垒区的载流子密度沿着半导体基板的横向(即平行于半导体基板的方向)变化。根据这一结构，势垒区能够利用载流子密度较高的部分抑制空穴的注入，同时利用载流子密度较低的部分抑制回滞现象的发生。
发明内容
如上所述，在具有二极管构造的半导体装置中，能够通过设置势垒区而降低恢复电流。另一方面，设置势垒区有可能成为发生回滞现象这一问题的主要原因。本说明书提供一种新技术，其能够在降低恢复电流的同时抑制回滞现象。
本说明书中公开的技术具体体现在一种半导体装置中。该半导体装置具有：半导体基板、设置在半导体基板的上表面的上表面电极、以及设置在半导体基板的位于上表面相对侧的下表面的下表面电极。半导体基板具有：与上表面电极接触的p型阳极区、与下表面电极接触的n型阴极区、以及位于阳极区与阴极区之间并且载流子密度低于阴极区的n型漂移区。半导体基板还具有位于阳极区与漂移区之间的势垒区、以及在势垒区和上表面电极之间延伸且与上表面电极进行肖特基接触的n型柱区。势垒区具有多层结构，所述多层结构包括n型第一势垒层、p型第二势垒层、以及n型第三势垒层，所述第二势垒层位于所述第一势垒层与所述第三势垒层之间。第一势垒层及第三势垒层的各自的载流子密度高于漂移区中的载流子密度。此外，第一势垒层与阳极区相接，并且隔着柱区与上表面电极连接。
在上述半导体装置中，在半导体基板内形成有二极管构造。所述二极管容许从上表面电极向下表面电极流动的电流，禁止从下表面电极向上表面电极流动的电流。在阳极区与漂移区之间设置有势垒区。势垒区具有多层结构，p型第二势垒层位于n型第一势垒层及n型第三势垒层之间。在正向偏置时，n型第一势垒层及n型第三势垒层抑制从阳极区向漂移区注入的空穴。由此，能够降低在向反向偏置切换时产生的恢复电流。此外，在向正向偏置切换时，p型第二势垒层能够抑制从漂移区通过柱区向上表面电极流动的电子。由此，由于注入阳极区的电子增加，能够抑制回滞现象产生。
n型第一势垒层及n型第三势垒层通过p型第二势垒层彼此分隔。从而，可以使第一势垒层与第三势垒层的载流子密度互不相同。举例来说，对于与柱区连接的第一势垒层，可以使其载流子密度较低。由此，能够抑制在向正向偏置切换时从漂移区通过柱区向上表面电极流动的电子，进一步抑制回滞现象的发生。与此相对，可以使第三势垒层的载流子密度较高。由此，能够增强势垒区降低恢复电流这一功能。由于第三势垒层通过第二势垒层而与柱区分隔开，因此，即使提高第三势垒层的载流子密度，也不会增加回滞现象发生的可能性。
在本技术的一个实施方式中，半导体基板还可以具有：与上表面电极接触的p型体区、与上表面电极接触并且通过体区与漂移区分隔开的n型发射极区、设置于上表面并且到达漂移区的沟道、以及与下表面电极接触并且通过漂移区与体区分隔开的p型集电极区。在此情况下，沟道内可以设置有隔着栅极绝缘膜而与发射极区、体区及漂移区相对的栅极，并且势垒区位于体区与漂移区之间。根据这一结构，在半导体基板上还形成有IGBT(Insulated Gate Bipolar Transistor)的结构。即，半导体装置形成同时具有二极管构造和IGBT构造的RC(Reverse Conducting)-IGBT构造。
在上述半导体装置中，如果对栅极施加规定的驱动电压而使IGBT导通，则电流能够从下表面电极向上表面电极流动。在半导体基板内，从发射极区向漂移区注入电子，从集电极区向漂移区注入空穴，发生漂移区的电导调制。此时，由于载流子密度较高的n型第三势垒层接近漂移区，因此易于在漂移区中积累大量的空穴。从而，能够促进漂移区的电导调制，降低IGBT的导通电阻。这样一来，势垒区的第三势垒层不仅能够改善二极管中的恢复特性，还有助于改善IGBT中的导通电阻。
附图说明
图1是示意性地示出了实施例1的半导体装置10的构成的剖视图。
图2示出了实施例1的半导体装置10中正向偏置时的二极管区域12X。
图3示意性地示出了实施例1的半导体装置10中二极管区域12X的正向电压Vf和正向电流If的关系。
图4示出了实施例1的半导体装置10中在导通时的IGBT区域12Y。
图5示意性地示出了实施例2的半导体装置110的结构的剖视图。
图6示意性地示出了实施例3的半导体装置210的结构的剖视图。
具体实施方式
在本技术的一个实施方式中，在半导体基板具有前述IGBT构造的情况下，势垒区还可以具有位于第三势垒层与漂移层之间的p型第四势垒层。根据这一结构，能够减小栅极隔着栅极绝缘膜与漂移区相对的面积。由此，由于栅极与下表面电极之间的寄生电容降低，从而能够在短时间内进行IGBT的断开(即从栅极放电)。
在本技术的一个实施方式中，第三势垒层的载流子密度可以高于第一势垒层的载流子密度。根据这一结构，当半导体装置作为二极管起作用时，能够在抑制回滞现象发生的同时降低恢复电流。此外，当半导体装置作为IGBT起作用时，通过载流子密度较高的第三势垒层，能够促进漂移区的电导调制，降低IGBT的导通电阻。举例来说，第三势垒层中的载流子密度可以为第一势垒层中的载流子密度的三倍以上。
在本技术的一个实施方式中，第三势垒层中的载流子密度也可以是沿着平行于半导体基板的方向均匀分布。根据这一结构，能够使得半导体基板的电气特性整体一致。特别是，当半导体装置作为IGBT起作用时，由于漂移区的电导调制整体一致，因此能够有效地降低导通电阻。
以下，参照附图详细说明本发明的代表性且非限定性的具体实施例。该详细说明仅用于向本领域技术人员示出用于实施本发明的优选实施例的细节，并不意图限定本发明的范围。另外，以下公开的追加的技术特征及发明是用于提供进一步改进后的半导体装置、使用方法及制造方法，能够与其他特征及发明一起使用或独立于其他特征及发明单独使用。
另外，在以下详细说明中公开的特征或工序的组合，并非是最大范围角度下实施本发明时所必需的，其仅仅是为了特别说明本发明的代表性具体例所记载的例子。另外，上述及下述代表性具体例的各种特征、以及独立权利要求及从属权利要求中记载的各种特征，都无需按照提供本发明的附加性的实用实施方式时所记载的具体例、或所列举的顺序进行组合。
记载在本说明书和/或权利要求书的范围内的所有特征的目的在于，在实施例和/或权利要求中记载的特征的构成之外，还作为对本发明的原始公开的内容以及要求保护的特定内容的限定而单独且彼此独立地公开的技术特征。此外，所有数值范围、以及涉及组或群的记载的目的在于，都是作为对本发明的原始公开以及要求保护的特定内容的限定而公开了其中的构成。
【实施例】
参照附图对实施例1的半导体装置10进行说明。本实施例的半导体装置10并不特别限定，其属于功率半导体装置，例如能够在电动汽车中用作变压器及逆变器的开关元件。这里所说的电动汽车包括例如混合动力车辆、燃料电池车辆或可充电式电动汽车等通过电动机驱动车轮的各种汽车。
如图1所示，半导体装置10具有半导体基板12、设置在半导体基板12的上表面12a的上表面电极14、以及设置在半导体基板12的下表面12b的下表面电极16。半导体基板12是由硅(Si)构成的硅基板。但是，半导体基板12不限于硅基板，也可以是碳化硅(SiC)基板或者由其他半导体材料构成的基板(结晶体)。上表面电极14和下表面电极16分别由具有导电性的材料构成。构成上表面电极14和下表面电极16的材料不作特别限定，例如可以为铝(Al)、镍(Ni)、钛(Ti)、金(Au)等金属材料。
此外，半导体基板12的上表面12a是指半导体基板12的一个表面，半导体基板12的下表面12b是指半导体12的另一个表面且位于上表面12a相对侧的表面。在本说明书中，“上表面”及“下表面”这一表达是为了方便区分彼此位于相对侧的两个表面，并不限定半导体装置10被制造时或者在使用时的姿态。
半导体基板12具有二极管区域12X和IGBT区域12Y。二极管区域12X和IGBT区域12Y分别从半导体基板12的上表面12a延伸至下表面12b，并且在俯视观察半导体基板12下相互邻接。如从后述说明中能够理解的，二极管区域12X中形成有pn结二极管和肖特基二极管这两种构造，IGBT区域12Y中形成有IGBT构造。即，半导体装置10是兼具二极管构造和IGBT构造的半导体装置，通常称作RC-IGBT。
二极管区域12X具有阳极区22、阴极区24、漂移区26、势垒区28、以及柱区30。阳极区22为p型半导体区，与上表面电极14接触。此外，阳极区22中与上表面电极14接触的部分22a，载流子密度(即空穴的密度)与阳极区22的其他部分相比更高，与上表面电极14欧姆接触。阴极区24为n型半导体区，与下表面电极16接触。阴极区24的载流子密度充分高，阴极区24与下表面电极16欧姆接触。
漂移区26与阴极区24同样地为n型半导体区。但是，漂移区26的载流子密度(即自由电子的密度)低于阴极区24的载流子密度。漂移区26位于阳极区22与阴极区24之间。即，阳极区22和阴极区24至少通过漂移区26而彼此分隔开。漂移区26不仅位于二极管区域12X，还位于IGBT区域12Y。
势垒区28位于阳极区22与漂移区26之间。即，阳极区22和漂移区26至少通过势垒区28彼此分隔开。柱区30为n型半导体区。柱区30的载流子密度低于阴极区24的载流子密度、且与漂移区26的载流子密度相比大致相同或者更高。柱区30在势垒区28与上表面电极14之间延伸，与上表面电极4进行肖特基接触。势垒区28及柱区30不仅设置于二极管区域12X，还设置于IGBT区域12Y。
本实施例中的势垒区28具有多层结构，所述多层结构包括n型第一势垒层28a、p型第二势垒层28b、以及n型第三势垒层28c，第二势垒层28b位于第一势垒层28a与第三势垒层28c之间。第一势垒层28a及第三势垒层28c中的各自的载流子密度高于漂移区26中的载流子密度、且低于阴极区24中的载流子密度。第一势垒层28a与阳极区22相接，并且经由柱区30与上表面电极14连接。第三势垒层28c通过第二势垒层28b与第一势垒层28a及柱区30分隔开。虽然并未特别限定，但在本实施例的势垒区28中，第三势垒层28c的载流子密度高于第一势垒层28a的载流子密度。此外，势垒区28的厚度(图1中的上下方向的尺寸)与阳极区22的厚度及漂移区26的厚度很小。
二极管区域12X中还设置有沟道32。沟道32设置于半导体基板12的上表面12a，具有到达漂移区26的深度。沟道32内设置有沟道绝缘膜34和伪电极36。伪电极36通过沟道绝缘膜34与半导体基板12(即沟道32的内表面)分隔开。另外，伪电极36与上表面电极14之间设置有层间绝缘膜38。伪电极36配置为保持与上表面电极14相同的电位。前述柱区30位于相邻的两条沟道32之间，阳极区22位于各条沟道32与柱区30之间。此外，沟道32、沟道绝缘膜34、伪电极36、以及层间绝缘膜38均并非是必须在二极管区域12X中所必须的构成，可以省略。
接下来，对IGBT区域12Y进行说明。IGBT区域12Y具有体区52、发射极区54、集电极区56、漂移区26、势垒区28、以及柱区30。体区52为p型半导体区，与上表面电极14接触。此外，体区52中与上表面电极14接触的部分52a，载流子密度(即空穴的密度)与体区52的其他部分相比更高，与上表面电极14欧姆接触。势垒区28位于体区52与漂移区26之间。即，体区52通过势垒区28与漂移区26分隔开。在IGBT区域12Y中，柱区30也在势垒区28与上表面电极14之间延伸，与上表面电极14进行肖特基接触。
发射极区54为n型半导体区，与上表面电极14接触。发射极区54的载流子密度充分高，发射极区54与上表面电极14欧姆接触。发射极区54通过体区52而与漂移区26及柱区30分隔开。此外，在本实施例的半导体装置10中，在二极管区域12X还设置有与发射极区54相同的n型半导体区，但在二极管区域12X中该n型半导体区并不是必须的构成，可以省略。
集电极区56为p型半导体区，与下表面电极16接触。集电极区56的载流子密度充分高，集电极区56与下表面电极16欧姆接触。集电极区56通过漂移区26及势垒区28而与体区52分隔开。如图1所示，与前述二极管区域12X中沿着半导体基板12的下表面12b设置有n型阴极区24相对，在IGBT区域12Y中沿着半导体基板12的下表面12b设置有p型集电极区56，在这一点上，二极管区域12X与IGBT区域12Y彼此不同。
IGBT区域12Y中设置有沟道62。沟道62设置于半导体基板12的上表面12a，具有到达漂移区26的深度。沟道62内设置有栅极绝缘膜64和栅极66。栅极66通过栅极绝缘膜64与半导体基板12(即沟道62的内表面)分隔开。另外，在栅极66与上表面电极14之间设置有层间绝缘膜68。栅极66隔着栅极绝缘膜64而与发射极区54、体区52及漂移区26相对。栅极66配置为由外部驱动电路施加规定的栅极电压。
通过以上构成，本实施例的半导体装置10能够在二极管区域12X中作为二极管起作用。二极管区域12X容许电流从上表面电极14向下表面电极16流动，禁止电流从下表面电极16向上表面电极14流动。即，如图2所示，如果在上表面电极14与下表面电极16之间施加正向电压Vf，则在半导体装置10中流过正向电流If。图3所示的曲线图A示意性地示出了正向电压Vf与正向电流If之间的关系。
在本实施例的半导体装置10中，在阳极区22与漂移区26之间设置有势垒区28。势垒区28具有多层结构，p型第二势垒层28b位于n型第一势垒层28a与n型第三势垒层28c之间。在图2所示的正向偏置时，n型第一势垒层28a及n型第三势垒层28c抑制从阳极区22向漂移区26注入的空穴。由此，能够降低在向反向偏置切换时产生的恢复电流。此外，在向正向偏置时，p型第二势垒层28b能够抑制从漂移区26通过柱区30向上表面电极14流动的电子E。由此，由于向阳极区22注入的电子增加，能够抑制回滞现象的发生。回滞现象是指，如图3中的曲线图B所示，当向正向偏置切换时，与正向电压Vf增加相对而正向电流If的增加暂时延迟的现象，例如可能导致不必要的损耗。
此外，n型第一势垒层28a及n型第三势垒层28c通过p型第二势垒层28b彼此分隔开。从而，能够使第一势垒层28a与第三势垒层28c的载流子密度互不相同。如前所述，在本实施例的势垒区28中，第三势垒层28c的载流子密度高于第一势垒层28a的载流子密度。与柱区30连接的第一势垒层28a的载流子密度越低，则在向正向偏置切换时就越能够抑制从漂移区26通过柱区30向上表面电极14流动的电子E，进一步抑制回滞现象的发生。另一方面，对于第三势垒层28c，通过提高其载流子密度，能够提高势垒区28的降低恢复电流这一功能。由于第三势垒层28c通过第二势垒层28b与柱区30分隔开，因此，即使提高第三势垒层28c的载流子密度，也不会增加回滞现象发生的可能性。这样一来，具有多层结构的势垒区28就能够在二极管区域12X中降低恢复电流并且抑制回滞现象的发生。
本实施例的半导体装置10还能够在IGBT区域12Y中作为IGBT起作用。如图4所示，如果向栅极66施加规定的栅极电压Vg而使IGBT导通，则电流Ic就能够从下表面电极16向上表面电极14流动。在半导体基板12内，从发射极区54向漂移区26注入电子，从集电极区56向漂移区26注入空穴，产生漂移区26的电导调制。此时，由于载流子密度较高的n型第三势垒层28c接近漂移区26，因而易于在漂移区26积累大量的空穴。从而，能够促进漂移区26的电导调制，降低IGBT的导通电阻。这样一来，势垒区28的第三势垒层28c不仅能够改善二极管中的恢复特征，还有助于改善IGBT中的导通电阻。
参照图5，对实施例2的半导体装置110进行说明。与实施例1的半导体装置10相比，本实施例的半导体装置110的势垒区28的结构进行了变更。对于其他结构，由于在实施例1、2之间是相同的，因此通过标注相同的标记而在此省略重复的说明。
如图5所示，本实施例中的势垒区28除了第一势垒层28a、第二势垒层28b、以及第三势垒层28c之外，还具有第四势垒层28d。第四势垒层28d为p型半导体区，位于第三势垒层28c与漂移区26之间。第四势垒层28d的载流子密度低于集电极区56的载流子密度，与体区52的载流子密度相比大致相同或更低。第四势垒层28d的载流子密度可以与第二势垒层28b的载流子密度相同，也可以不同。
如果势垒区28具有第四势垒层28d，则能够减小栅极66隔着栅极绝缘膜64与漂移区26相对的面积S。由此，由于栅极66与下表面电极16之间的寄生电容降低，因此能够在短时间内进行IGBT的断开(即从栅极66放电)。
参照图6，对实施例3的半导体装置210进行说明。本实施例的半导体装置210不具有IGBT构造，仅具有二极管构造。此外，在本实施例的半导体装置210的构成中，对于与实施例1、2的半导体装置10、110相同的部分，标注相同的标记而省略重复的说明。
半导体装置210具有半导体基板12、设置于半导体基板12的上表面12a的上表面电极14、以及设置于半导体基板12的下表面12b的下表面电极16。半导体基板12具有与上表面电极14接触的p型阳极区22、以及与下表面电极16接触的n型阴极区24。阳极区22中与上表面电极14接触的部分22a，载流子密度与阳极区22的其他部分相比更高，与上表面电极14欧姆接触。阴极区24的载流子密度充分高，阴极区24与下表面电极16欧姆接触。
半导体基板12还具有：位于阳极区22与阴极区24之间且载流子密度与阴极区24相比更低的n型漂移区26、位于阳极区22与漂移区26之间的势垒区28、以及在势垒区28与上表面电极14之间延伸且与上表面电极14进行肖特基接触的n型柱区30。
势垒区28具有多层结构，所述多层结构包括n型第一势垒层28a、p型第二势垒层28b、以及n型第三势垒层28c，第二势垒层28b位于第一势垒层28a与第三势垒层28c之间。第一势垒层28a及第三势垒层28c的各自的载流子密度均高于漂移区26中的载流子密度。第一势垒层28a与阳极区22相接，并且通过柱区30与上表面电极14连接。
本实施例的半导体装置210具有与实施例1的半导体装置10的二极管区域12X类似的构成，能够与该二极管区域12X同样地起作用。此外，本实施例的半导体装置210不具有沟道32、沟道绝缘膜34、伪电极36以及层间绝缘膜38，在这一点上与实施例1中的二极管区域12X不同。但是，在本实施例的半导体装置210中，通过具有多层结构的势垒区28也能够降低恢复电流并且抑制回滞现象的发生。

Claims (6)

1.一种半导体装置，其特征在于，具有：
半导体基板；
上表面电极，其设置于所述半导体基板的上表面；以及
下表面电极，其设置在所述半导体基板的位于所述上表面相对侧的下表面，
所述半导体基板具有：
p型阳极区，其与所述上表面电极接触；
n型阴极区，其与所述下表面电极接触；
n型漂移区，其位于位于所述阳极区与所述阴极区之间，且载流子密度低于所述阴极区；
势垒区，其位于所述阳极区与所述漂移区之间；以及
n型柱区，其在所述势垒区和所述上表面电极之间延伸，且与所述上表面电极进行肖特基接触，
所述势垒区具有多层结构，所述多层结构包括n型第一势垒层、p型第二势垒层、以及n型第三势垒层，所述第二势垒层位于所述第一势垒层与所述第三势垒层之间，
所述第一势垒层及所述第三势垒层各自的载流子密度高于所述漂移区中的载流子密度，
所述第一势垒层与所述阳极区相接，并且隔着所述柱区与所述上表面电极连接。
2.根据权利要求1所述的半导体装置，其特征在于，
所述半导体基板还具有：
p型体区，其与所述上表面电极接触；
n型发射极区，其与所述上表面电极接触，且通过所述体区与所述漂移区分隔开；
沟道，其设置于所述上表面，且到达所述漂移区；以及
P型集电极区，其与所述下表面电极接触，并且通过所述漂移区与所述体区分隔开，
所述沟道内设置有栅极，该栅极隔着栅极绝缘膜与所述发射极区、所述体区、以及所述漂移区相对，
所述势垒区位于所述体区与所述漂移区之间。
3.根据权利要求2所述的半导体装置，其特征在于，所述势垒区还具有位于所述第三势垒层与所述漂移区之间的p型第四势垒层。
4.根据权利要求1至3中任意一项所述的半导体装置，其特征在于，所述第三势垒层的所述载流子密度与所述第一势垒层的所述载流子密度相比更高。
5.根据权利要求4所述的半导体装置，其特征在于，所述第三势垒层的所述载流子密度为所述第一势垒层的所述载流子密度的三倍以上。
6.根据权利要求1至5中任意一项所述的半导体装置，其特征在于，所述第三势垒层的所述载流子密度沿着平行于所述半导体基板的方向均匀分布。
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