CN109643646B - 半导体装置的制造方法 - Google Patents
半导体装置的制造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 221
- 238000000034 method Methods 0.000 title claims description 57
- 238000004519 manufacturing process Methods 0.000 title claims description 42
- 239000000758 substrate Substances 0.000 claims abstract description 123
- 239000002344 surface layer Substances 0.000 claims abstract description 15
- 238000005468 ion implantation Methods 0.000 claims description 34
- 239000012535 impurity Substances 0.000 claims description 32
- 230000001678 irradiating effect Effects 0.000 claims description 14
- 230000004913 activation Effects 0.000 claims description 13
- 230000003213 activating effect Effects 0.000 claims description 12
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 238000005224 laser annealing Methods 0.000 abstract description 34
- 238000002310 reflectometry Methods 0.000 abstract description 4
- 238000009826 distribution Methods 0.000 description 20
- 230000008569 process Effects 0.000 description 14
- 238000000137 annealing Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 230000001133 acceleration Effects 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- JNDMLEXHDPKVFC-UHFFFAOYSA-N aluminum;oxygen(2-);yttrium(3+) Chemical compound [O-2].[O-2].[O-2].[Al+3].[Y+3] JNDMLEXHDPKVFC-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 229910002092 carbon dioxide Inorganic materials 0.000 description 2
- 239000001569 carbon dioxide Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 229910019901 yttrium aluminum garnet Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005187 foaming Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
从n‑型半导体基板(10)的背面照射短波长激光器的激光(31),使p+型集电区(12)和n+型阴极区(13)活化。此时,n‑型半导体基板(10)的背面的表面层熔融而再结晶化,几乎不存在无定形化了的部分。其后,从n‑型半导体基板(10)的背面照射长波长激光器的激光(32),使n型FS区域(11)活化。由于在n‑型半导体基板(10)的背面的表面层几乎不存在无定形化了的部分,所以能够抑制长波长激光器的激光(32)的吸收率降低和/或高反射率化,由长波长激光器的激光(32)产生的热传递到n型FS区域(11),能够使n型FS区域(11)可靠地活化。由此,能够通过更低能量下的激光退火使预定区域活化。
Description
技术领域
本发明涉及半导体装置的制造方法。
背景技术
以往,作为通过激光退火使距半导体基板(半导体晶片)的主面深的区域活化的方法之一,可举出使用波长比较长的例如红外(IR:infrared)激光器等长波长激光器的方法。使用波长越长的激光器,激光的侵入深度越深,激光会到达半导体基板的更深的区域。因此,通过使用长波长激光器,从而与使用波长较短的例如绿(Green)激光器等短波长激光器的情况相比,能够实现深的区域的活化。
另外,作为通过激光退火使预定区域活化的其他方法,已知在使用长波长激光器使距半导体基板的主面相对深的区域活化之后,使用短波长激光器使距半导体基板的同一主面相对浅的区域活化的方法。距半导体基板的主面相对深的区域是指例如场截止(FS:Field Stop)区域。距半导体基板的主面相对浅的区域是指例如集电区和/或阴极区。
以制作(制造)RC-IGBT(Reverse Conducting Insulated Gate BipolarTransistor:反向导通型的绝缘栅双极型晶体管)的情况为例对使用波长不同的2种激光器的现有的激光退火进行说明。图10A、图10B是表示现有的半导体装置的制造过程中的状态的截面图。在此,使用IR激光器作为长波长激光器,使用Green激光器作为短波长激光器。
首先,如图10A所示,在成为n-型漂移区101的n-型的半导体基板110的正面侧形成RC-IGBT的正面元件结构和正面电极109。RC-IGBT的正面元件结构是指配置于IGBT区域121的IGBT的MOS栅极和配置于FWD(Free Wheeling Diode:续流二极管)区域122的FWD的p型阳极区。IGBT区域121和FWD区域122并列地配置于同一半导体基板110。
IGBT的MOS栅极由p型基区102、n+型发射区103、p+型接触区104、沟槽105、栅极绝缘膜106和栅电极107构成。p型基区102兼作FWD的p型阳极区。正面电极109兼作发射电极和阳极电极。接下来,以不同的条件从半导体基板110的背面进行多次离子注入,分别形成n型FS区域111、p+型集电区112和n+型阴极区113。
接下来,对距半导体基板110的背面相对深的n型FS区域111照射IR激光器的激光131,使n型FS区域111活化。接下来,如图10B所示,对距半导体基板110的背面相对浅的p+型集电区112和n+型阴极区113照射Green激光器的激光132,使p+型集电区112和n+型阴极区113活化。其后,通过在半导体基板110的背面形成背面电极(未图示),从而完成RC-IGBT。
作为通过激光退火使预定区域活化的其他方法,提出了在向半导体基板持续照射从半导体激光振荡器出射的第一激光的状态下,向半导体基板的同一主面照射从固体激光振荡器出射的第二激光的方法(例如,参照下述专利文献1(第0011、0022段))。在下述专利文献1中,第一激光的波长为950nm以下,第二激光的波长为绿色的波长区域,照射第一激光、第二激光的区域几乎重叠。
另外,作为通过激光退火使预定区域活化的其他方法,提出了对半导体基板的离子注入面同时照射YAG2ω激光(YAG(Yttrium Aluminum Garnet:钇铝石榴石)激光的二次谐波,波长:500nm)和GaAs(砷化镓)类的半导体激光(波长:808nm)的方法(例如,参照下述专利文献2(第0057段))。在下述专利文献2中,通过同时照射波长不同的2种激光器的激光,从而能够在不对基板正面的MOS栅极造成不良影响的情况下在距半导体基板的背面深的位置处形成预定区域。
现有技术文献
专利文献
专利文献1:日本特开2014-036110号公报
专利文献2:日本特开2009-176892号公报
发明内容
技术问题
然而,在现有的激光退火(参照图10A、图10B)中,产生了如下问题。图8、图9是表示现有的半导体装置的激光退火后的载流子浓度分布的特性图。在图8、图9中示出图10B的切割线AA-AA’处的载流子浓度分布。为了在FWD区域122形成n+型阴极区113而需要以高剂量从半导体基板110的背面进行离子注入,但是如果以高剂量进行离子注入,则导致半导体基板110的背面的表面层的结晶性被破坏而无定形化。长波长激光器的激光131会照射到比无定形化了的区域更深的区域。
在向无定形化了的区域和比无定形化了的区域更深的区域照射长波长激光器的激光131的情况下,激光131的吸收率降低,或者激光131的反射率变高。这样,热无法传导到距离半导体基板110的背面比无定形化了的区域深的区域,如图8所示难以使预定区域(这里为n型FS区域111)活化。因此,n型FS区域111的载流子浓度比n-型漂移区101的载流子浓度低,无法得到n型FS区域111的预定的载流子浓度。
该问题通过以更高的能量(例如5.8J/cm2以上的程度)照射长波长激光器的激光131而得以解决。即,如图9所示,利用高能量的激光131使n型FS区域111活化,n型FS区域111的载流子浓度变得比n-型漂移区101的载流子浓度高。然而,以越高的能量照射长波长激光器的激光131,半导体基板110的背面发热到越高的温度。
在上述专利文献1、2中,都由于从半导体基板的一个主面向同一区域同时照射波长不同的2种激光器的激光,所以半导体基板的背面发热为高温度。具体而言,由于半导体基板的背面的表面温度上升到例如200℃~300℃的程度,所以例如会发生半导体基板110的正面的表面层变质,或者覆盖半导体基板110的正面的抗蚀剂膜的图案变形(抗蚀剂烧蚀)和/或粘接带的变形/发泡/粘合剂残留等对半导体基板110的正面侧的各部分造成不良影响。
本发明为了消除上述的现有技术的问题点,目的在于提供能够通过更低能量下的激光退火使预定区域活化的半导体装置的制造方法。
技术方案
为了解决上述的课题,实现本发明的目的,本发明的半导体装置的制造方法具有如下特征。首先,进行从半导体基板的一个主面进行杂质的离子注入来形成第一半导体区的第一工序。接下来,进行从上述半导体基板的一个主面进行杂质的离子注入而在比上述第一半导体区浅的区域形成杂质浓度比上述第一半导体区的杂质浓度高的第二半导体区的第二工序。接下来,进行从上述半导体基板的一个主面照射第一激光而使上述第二半导体区活化,并且将上述半导体基板的一个主面的表面层熔融而使其再结晶化的第三工序。接下来,在上述第三工序之后,进行从上述半导体基板的一个主面照射波长比上述第一激光的波长长的第二激光而使上述第一半导体区活化的第四工序。
另外,本发明的半导体装置的制造方法的特征在于,在上述的发明中,在上述第三工序中,将上述第一激光的能量设为1J/cm2以上且2J/cm2以下。
另外,本发明的半导体装置的制造方法的特征在于,在上述的发明中,在上述第四工序中,将上述第二激光的能量设为4J/cm2以上且8J/cm2以下。
另外,本发明的半导体装置的制造方法的特征在于,在上述的发明中,在上述第三工序中,将通过上述第一激光使杂质活化时的活化深度设为小于1μm。
另外,本发明的半导体装置的制造方法的特征在于,在上述的发明中,在上述第四工序中,将通过上述第二激光使杂质活化时的活化深度设为1μm以上且4μm以下。
另外,本发明的半导体装置的制造方法的特征在于,在上述的发明中,上述第一激光的波长为500nm以上且550nm以下。
另外,本发明的半导体装置的制造方法的特征在于,在上述的发明中,上述第二激光的波长为800nm以上。
另外,本发明的半导体装置的制造方法的特征在于,在上述的发明中,还包括第五工序、第六工序。在上述第五工序中,在第一导电型的上述半导体基板的另一个主面侧形成预定的元件结构。在上述第六工序中,在上述第三工序之前,从上述半导体基板的一个主面进行第二导电型杂质的离子注入,在比上述第一半导体区浅的区域形成在与上述半导体基板的一个主面平行的方向上与上述第二半导体区并列地配置的第二导电型的第三半导体区。在上述第一工序中,进行第一导电型杂质的离子注入而形成第一导电型的上述第一半导体区。在上述第二工序中,进行第一导电型杂质的离子注入而形成第一导电型的上述第二半导体区。在上述第三工序中,照射上述第一激光而使上述第二半导体区和上述第三半导体区活化。
另外,本发明的半导体装置的制造方法的特征在于,在上述的发明中,在上述第一工序中,将离子注入的剂量设为5×1011/cm2以上且1×1014/cm2以下。
另外,本发明的半导体装置的制造方法的特征在于,在上述的发明中,在上述第二工序中,将离子注入的剂量设为1×1014/cm2以上且1×1016/cm2以下。
另外,本发明的半导体装置的制造方法的特征在于,在上述的发明中,在上述第六工序中,将离子注入的剂量设为1×1012/cm2以上且1×1015/cm2以下。
根据上述的发明,通过利用短波长激光器实现的激光退火使因为用于形成距离半导体基板的背面浅且杂质浓度相对高的第二半导体区的离子注入而无定形化了的部分熔融并再结晶化。因此,其后,在从半导体基板的背面利用长波长激光器实现的第一半导体区的激光退火时,能够抑制长波长激光器的激光的吸收率降低和/或高反射率化。
发明效果
根据本发明的半导体装置的制造方法,起到能够通过更低能量下的激光退火使预定区域活化的效果。
附图说明
图1是表示通过实施方式的半导体装置的制造方法制造的半导体装置的一个例子的截面图。
图2是表示实施方式的半导体装置的制造方法的概要的流程图。
图3A是表示实施方式的半导体装置的制造过程中的状态的截面图。
图3B是表示实施方式的半导体装置的制造过程中的状态的截面图。
图4是表示实施方式的半导体装置的激光退火后的载流子浓度分布的特性图。
图5是表示实施例的激光退火后的载流子浓度分布的特性图。
图6是表示现有例的激光退火后的载流子浓度分布的特性图。
图7是比较了实施例和现有例的激光退火后的载流子浓度分布而得的特性图。
图8是表示现有的半导体装置的激光退火后的载流子浓度分布的特性图。
图9是表示现有的半导体装置的激光退火后的载流子浓度分布的特性图。
图10A是表示现有的半导体装置的制造过程中的状态的截面图。
图10B是表示现有的半导体装置的制造过程中的状态的截面图。
符号说明
1:n-型漂移区
2:p型基区
3:n+型发射区
4:p+型接触区
5:沟槽
6:栅极绝缘膜
7:栅电极
8:层间绝缘膜
9:正面电极
10:n-型半导体基板
11:n型FS区域
12:p+型集电区
13:n+型阴极区
14:背面电极
21:IGBT区域
22:FWD区域
31:短波长激光器的激光
32:长波长激光器的激光
具体实施方式
以下,参照附图详细说明本发明的半导体装置及半导体装置的制造方法的优选的实施方式。在本说明书和附图中,在前缀有n或p的层和区域中,分别表示电子或空穴为多数载流子。另外,标记于n或p的+和-分别表示杂质浓度比未标记+和-的层或区域的杂质浓度高和低。应予说明,在以下的实施方式的说明和附图中,对同样的结构标记相同的符号,并省略重复的说明。
(实施方式)
首先,作为通过实施方式的半导体装置的制造方法制作(制造)的半导体装置的一个例子,对RC-IGBT的结构进行说明。图1是表示通过实施方式的半导体装置的制造方法制造的半导体装置的一个例子的截面图。图1所示的实施方式的半导体装置是在与绝缘栅双极型晶体管(IGBT)相同的n-型半导体基板(半导体芯片)10配置了与该IGBT反向并联连接的续流用二极管(FWD)的RC-IGBT。
具体而言,在成为n-型漂移区1的同一n-型半导体基板(半导体芯片)10,并列地配置有IGBT区域21和FWD区域22。在IGBT区域21配置有IGBT。在FWD区域22配置有FWD。在IGBT区域21中,在n-型半导体基板10的正面侧设置有由p型基区2、n+型发射区3、p+型接触区4、沟槽5、栅极绝缘膜6和栅电极7构成的通常的沟槽栅型的MOS栅极(由金属-氧化膜-半导体构成的绝缘栅)。
正面电极9与n+型发射区3和p+型接触区4接触,且与这些n+型发射区3和p+型接触区4电连接。另外,正面电极9通过层间绝缘膜8与栅电极7电绝缘。p型基区2、沟槽5、层间绝缘膜8和正面电极9从IGBT区域21一直设置到FWD区域22。n+型发射区3和p+型接触区4未设置于FWD区域22。
即,在FWD区域22中,与IGBT区域21同样地在n-型半导体基板10的正面的表面层设置有p型基区2、沟槽5、层间绝缘膜8和正面电极9。p型基区2在FWD区域22中作为p型阳极区发挥功能。正面电极9兼作发射电极和阳极电极。在图1中示出在IGBT区域21并列地配置有IGBT的多个单位单元(元件的构成单位)、在FWD区域22并列地配置有FWD的多个单位单元的状态。
在n-型半导体基板10的背面的表面层设置有n型场截止(FS)区域(第一半导体区)11。n型FS区域11从IGBT区域21一直设置到FWD区域22。n型FS区域11具有抑制在IGBT的关断时从p型基区2与n-型漂移区1的pn结延伸的耗尽层延伸的功能。另外,在n-型半导体基板10的背面的表面层,在距n-型半导体基板10的背面比n型FS区域11浅的位置分别选择性地设置有p+型集电区(第三半导体区)12和n+型阴极区(第二半导体区)13。
p+型集电区12设置于IGBT区域21,n+型阴极区13设置于FWD区域22。p+型集电区12和n+型阴极区13与n型FS区域11接触。另外,p+型集电区12与n+型阴极区13相互接触,且在与n-型半导体基板10的主面平行的方向并列地配置。n-型半导体基板10的p型基区2、n型FS区域11、p+型集电区12和n+型阴极区13以外的部分为n-型漂移区1。
背面电极14设置于n-型半导体基板10的整个背面,且与p+型集电区12和n+型阴极区13接触,且与p+型集电区12和n+型阴极区13电连接。背面电极14兼作集电极和阴极电极。
接下来,对实施方式的半导体装置的制造方法进行说明。图2是表示实施方式的半导体装置的制造方法的概要的流程图。图3A、图3B是表示实施方式的半导体装置的制造过程中的状态的截面图。图4是表示实施方式的半导体装置的激光退火后的载流子浓度分布的特性图。在图4中示出图3B的剖切线A-A’处的载流子浓度分布。首先,利用通常的方法,在成为n-型漂移区1的n-型半导体基板(半导体晶片)10的正面侧形成MOS栅极、层间绝缘膜8和正面电极9等正面元件结构(步骤S1)。
接下来,使n-型半导体基板10薄化(步骤S2)。n-型半导体基板10的薄化工序包括以下的工序。在n-型半导体基板10的正面形成表面保护膜。表面保护膜例如涂布抗蚀剂,利用抗蚀剂膜(未图示)保护n-型半导体基板10的正面侧的正面元件结构。接下来,在n-型半导体基板10的正面,贴附在后述的背面研磨时保护n-型半导体基板10的正面不受异物等影响的背面研磨带(粘接带:未图示)。接着,使与n-型半导体基板10的正面元件结构的凹凸相应地产生凹凸的背面研磨带平坦化。接下来,从背面侧遍及整个背面地对n-型半导体基板10进行磨削(背面研磨),使n-型半导体基板10的厚度均匀地变薄。
接下来,从背面侧仅磨削n-型半导体基板10的中央部(例如所谓的TAIKO(注册商标)工艺),不改变n-型半导体基板10的外周的厚度地仅使n-型半导体基板10的中央部成为用作半导体装置的产品厚度。接着,从n-型半导体基板10的正面剥离背面研磨带。应予说明,可以利用保护带保护n-型半导体基板10的正面,来代替将抗蚀剂膜用作保护膜的手段。另外,可以使用在通过支撑基板将n-型半导体基板10加固的状态下使整个n-型半导体基板10的厚度变薄的WSS(Wafer Support System:晶片支持系统)工艺来代替TAIKO工艺。
接下来,在背面研磨后,通过利用药液实现的蚀刻来除去残留在n-型半导体基板10的背面的损伤层。接着,利用SC-1溶液(NH4OH、H2O2与H2O的混合溶液)等清洗n-型半导体基板10的背面。应予说明,步骤S2的使n-型半导体基板10薄化的处理不限于上述的工序,只要能够从背面侧对n-型半导体基板10调整厚度而薄化到所希望的厚度即可。
接下来,对n-型半导体基板10的整个背面进行例如磷(P)等n型杂质的离子注入,形成n型FS区域11(步骤S3)。可以将用于形成该n型FS区域11的离子注入的剂量设为例如5×1011/cm2以上且1×1014/cm2以下的程度,并将加速能量设为例如0.6MeV以上且3MeV以下的程度。
接下来,对n-型半导体基板10的整个背面进行例如硼(B)等p型杂质的离子注入,在距n-型半导体基板10的背面比n型FS区域11浅的区域形成p+型集电区12(步骤S4)。可以将用于形成该p+型集电区12的离子注入的剂量设为例如1×1012/cm2以上且1×1015/cm2以下的程度,并将加速能量设为例如5keV以上且50keV以下的程度。接下来,在n-型半导体基板10的背面形成与n+型阴极区13的形成区域相对应的部分开口的掩模,例如抗蚀剂掩模(未图示)(步骤S5)。
接下来,将抗蚀剂掩模作为掩模,对n-型半导体基板10的背面进行例如磷等n型杂质的离子注入,使p+型集电区12的在抗蚀剂掩模的开口部露出的部分反转为n型而形成n+型阴极区13(步骤S6)。可以将用于形成该n+型阴极区13的离子注入的剂量设为例如1×1014/cm2以上且1×1016/cm2以下的程度,并将加速能量设为例如5keV以上且150keV以下的程度。由于用于形成n+型阴极区13的离子注入以高剂量进行,所以会因为该离子注入而导致n-型半导体基板10的背面的表面层的结晶性被破坏而无定形化。
用于形成n型FS区域11的离子注入只要在使用后述的长波长激光器(长波长激光振荡器)的激光退火之前进行即可。用于形成p+型集电区12和n+型阴极区13的各离子注入只要在使用后述的短波长激光器(短波长激光振荡器)的激光退火之前进行即可。另外,用于形成p+型集电区12的离子注入可以仅对与p+型集电区12的形成区域相对应的部分选择性地进行。接下来,除去n+型阴极区13的形成中使用的掩模(步骤S7)。例如在步骤S5的处理中形成的掩模为抗蚀剂掩模的情况下,进行灰化(Ashing)处理。
接下来,如图3A所示,从n-型半导体基板10的背面向n-型半导体基板10的整个背面照射短波长激光器的激光31,以例如1000℃以上的温度使p+型集电区12和n+型阴极区13活化(激光退火:步骤S8)。通过向n-型半导体基板10的背面照射短波长激光器的激光31,使因为用于形成p+型集电区12和n+型阴极区13的离子注入而无定形化了的部分(n-型半导体基板10的背面的表面层)熔融并固化,从而使其再结晶化。短波长激光器的激光31的能量例如为1J/cm2以上且2J/cm2以下的程度。
短波长激光器可以是例如通过能够照射1000nm以上且1100nm以下的程度的激光31的激光振荡器而得到的500nm以上且550nm以下的程度的二次谐波。具体而言,短波长激光器例如是YAG、YLF的二次谐波(绿色(Green))激光器。
优选地,可以使用YLF的二次谐波等Green激光器作为短波长激光器。Green激光器是指能够照射绿色的波长区域的激光的激光振荡器。Green激光器的波长例如是500nm以上且550nm以下的程度,例如可以是在退火处理中通常使用的532nm或527nm。
通过短波长激光器使杂质活化时的活化深度例如可以是与用于形成p+型集电区12或n+型阴极区13的离子注入的射程相同的程度。具体而言,通过短波长激光器使杂质活化时的活化深度例如小于1μm。因此,短波长激光器的脉冲宽度例如可以为50ns以上且300ns以下的程度,更优选为100ns以上且200ns以下的程度。另外,使杂质活化时的活化深度表示为了形成p+型集电区12或n+型阴极区13等而注入的杂质通过热处理而活化了时的杂质浓度分布的峰位置(杂质浓度最高的位置)。应予说明,使杂质活化时的活化深度是指从n-型半导体基板10的背面起算的深度。
接下来,如图3B所示,从n-型半导体基板10的背面向n-型半导体基板10的整个背面照射长波长激光器的激光32,使n型FS区域11活化(激光退火:步骤S9)。通过长波长激光器使杂质活化时的活化深度例如可以是与用于形成n型FS区域11的离子注入的射程相同的程度。
具体而言,通过长波长激光器使杂质活化时的活化深度例如为1μm以上且4μm以下的程度,优选为1.0μm以上且2.5μm以下的程度。因此,重要的是使长波长激光器的激光32向n-型半导体基板10的背面照射比步骤S8的处理时的照射时间长的时间。因此,长波长激光器的脉冲宽度优选例如为10μs以上的程度。
长波长激光器是指能够照射红外的波长区域(例如800nm以上的程度)的激光32的激光振荡器。优选地,长波长激光器的激光32的波长例如可以为1100nm以下的程度。应予说明,该长波长激光器的激光32的波长是具备红外的波长区域的激光振荡器的通常的波长。具体而言,长波长激光器例如是YAG激光器、气体激光器(例如二氧化碳(CO2)激光器)等红外(IR)激光器、或者半导体激光器。
优选地,可以使用半导体激光器(波长:808nm)作为长波长激光器。其理由是能够容易地设定所希望的脉冲宽度等条件。通过这样在步骤S8的处理之后进行步骤S9的处理,从而能够以预定温度(例如1000℃以上)使n型FS区域11活化,使n型FS区域11的载流子浓度成为比n-型漂移区1的载流子浓度高的预定的载流子浓度(参照图4)。
能够使步骤S9的处理中的退火温度成为预定温度的理由如下所述。如上所述,n-型半导体基板10的背面的表面层在步骤S8的处理中被再结晶化,几乎不存在无定形化了的部分。因此,在其后的步骤S9的处理时,长波长激光器的激光32的吸收率降低和/或高反射率化得到抑制。由此,通过照射长波长激光器的激光32而产生的热容易从n-型半导体基板10的背面传递到深的区域。由此,能够使n型FS区域11的载流子浓度从IGBT区域21一直到FWD区域22成为预定的载流子浓度。另外,与除了短波长激光器和长波长激光器的激光照射顺序以外为相同条件的现有方法相比,能够以低能量(优选例如为4J/cm2以上且8J/cm2以下的程度)使用长波长激光器。因此,与该现有方法相比,因以高能量照射长波长激光器的激光32而产生的问题被抑制。
接下来,除去保护n-型半导体基板10的正面的表面保护膜(步骤S10)。接着,通过溅射在n-型半导体基板10的整个背面形成背面电极14(步骤S11)。其后,通过将半导体晶片切割(切断)而单片化成单个的芯片状,从而完成图1所示的RC-IGBT。
如上所说明,根据实施方式,在通过利用短波长激光器实现的退火使距半导体基板的背面浅且杂质浓度相对高的区域(集电区和阴极区)活化之后,通过利用长波长激光器实现的退火使距半导体基板的背面深的区域(FS区域)活化。由此,首先,通过利用短波长激光器实现的退火使因为用于形成距半导体基板的背面浅的区域的离子注入而无定形化了的部分熔融并再结晶化。因此,其后,在从半导体基板的背面利用长波长激光器实现的激光退火时,能够抑制长波长激光器的激光的吸收率降低和/或高反射率化。由此,因长波长激光器的激光而产生的热可从半导体基板的背面传递到深的区域,该深的区域的温度达到为了活化而需要的预定的退火温度。因此,能够以比以往更低的能量进行利用长波长激光器实现的退火。因此,与以往相比,能够抑制因使用长波长激光器的退火而导致的对半导体基板的正面侧的各部分的不良影响。
另外,特别是由于以高剂量进行用于形成FWD的阴极区的离子注入,所以无定形化容易在FWD区域中的半导体基板的背面的表面层发展。因此,在现有方法中,由于与IGBT区域中的FS区域相比难以使FWD区域中的FS区域活化,所以需要以高能量进行利用长波长激光器实现的退火。与此相对,根据实施方式,如上所述,通过利用短波长激光器实现的退火使半导体基板的背面的表面层再结晶化而几乎消除无定形化了的部分,之后再进行利用长波长激光器实现的退火。因此,能够可靠地使FWD区域中的FS区域也活化。
另外,如果照射高能量的长波长激光器的激光,则因激光照射面的表面粗糙而导致半导体基板的背面的表面状态变差,但是根据实施方式,由于以比以往低的能量照射长波长激光器的激光,所以能够抑制长波长激光器的激光的照射面的表面粗糙。另外,根据实施方式,能够利用因长波长激光器的激光而从半导体基板的背面传递到了深的区域的热使SR(Spreading Resistance:扩展电阻测定)等中未被发现而残留在半导体基板内的缺陷恢复。另外,根据实施方式,在不同的时间进行利用短波长激光器实现的退火和利用长波长激光器实现的退火,执行这些激光退火的期间不重合。因此,与例如像上述专利文献1、2那样两个激光退火的执行期间重合的现有方法相比,能够抑制因激光退火而导致的半导体基板的发热。
(实施例)
接下来,对长波长激光器的激光32的能量值进行验证。图5是表示实施例的激光退火后的载流子浓度分布的特性图。在图5中示出图3B的切割线A-A’处的载流子浓度分布。图5的横轴为从n-型半导体基板10的背面(深度=0μm)起算的深度,纵轴为n型的载流子浓度(在图6、图7中也是同样)。图6是表示现有例的激光退火后的载流子浓度分布的特性图。在图6中示出图10B的切割线AA-AA’处的载流子浓度分布。
将根据上述的实施方式的半导体装置的制造方法(参照图2、图3A、图3B)制作的RC-IGBT(以下,称为实施例)的n-型半导体基板10的背面侧的载流子浓度分布示于图5。即,在实施例中,按照短波长激光器和长波长激光器的顺序依次照射激光31、32来进行n-型半导体基板10的背面侧的激光退火。图5所示的多个试样的长波长激光器的激光32的能量值各不相同。
作为比较,将在与实施例相同的条件下根据现有的半导体装置的制造方法(参照图10A、图10B)制作的RC-IGBT(以下,称为现有例)的n-型半导体基板110的背面侧的载流子浓度分布示于图6。即,在现有例中,按照长波长激光器和短波长激光器的顺序依次照射激光131、132来进行n-型半导体基板110的背面侧的激光退火。图6所示的多个试样的长波长激光器的激光131的能量值各不相同。
另外,除了激光退火中使用的波长不同的激光器的激光的照射顺序以外,实施例和现有例均为相同条件。具体而言,将用于形成n型FS区域11、111的离子注入的剂量设为1.0×1012/cm2,并将加速能量设为2.0MeV。将用于形成p+型集电区12、112的离子注入的剂量设为1.0×1013/cm2,并将加速能量设为例如20keV。将用于形成n+型阴极区13、113的离子注入的剂量设为例如3×1015/cm2,并将加速能量设为30keV。使用IR激光器作为长波长激光器,使用Green激光器作为短波长激光器。将Green激光器的能量设为1J/cm2。将IR激光器和Green激光器的激光的重复频率设为3kHz以下。将IR激光器的脉冲宽度设为20μsec。另外,IR激光器和Green激光器的激光的重叠率均是长轴50%,短轴50%。也可以不特别指定重叠率。在利用IR激光器和Green激光器实现的激光退火中使用住友重机械工业(注册商标)的激光退火装置。
根据图5所示的结果确认了,在实施例中,在针对Si厚(n-型半导体基板10的厚度)120μm的器件将IR激光器的激光的能量设为5.3J/cm2以上的试样(用符号41标记的载流子浓度分布)中,n型FS区域11被活化。另一方面,确认了在现有例中,在将IR激光器的激光的能量设为5.8J/cm2以上的高能量的试样(用符号42标记的载流子浓度分布)中n型FS区域111被活化,在将IR激光器的激光的能量设为低能量的情况下,n型FS区域111并未得到活化。即,确认了实施例与除了长波长激光器的激光131的能量值以外均与实施例为相同条件的现有例相比,能够使长波长激光器的激光32的能量低0.5J/cm2左右。
在图5、图6中,也有本发明的长波长激光器的激光32的能量的上述的优选范围(4J/cm2以上且8J/cm2以下的程度)中的省略了图示的数据,本发明通过发明人确认了在改变了离子注入条件和/或激光退火条件的情况下,在长波长激光器的激光32的能量的该优选范围能够使n型FS区域11活化,且与相同条件的现有例相比能够降低长波长激光器的激光32的能量。具体而言,本发明无论长波长激光器的激光32的能量值以外的条件如何,与现有例相比,均能够使长波长激光器的激光32的能量降低9%(≈(1-5.3[J/cm2]/5.8[J/cm2])×100%)左右。另外,在实施例中虽然以120μm来设定器件的Si厚,但是即使是使用不同的Si厚且与该厚度相应的不同的能量密度[J/cm2],也得到相同的效果。
在图7中示出在上述的实施例和比较例中,将长波长激光器的激光32、131的能量设为5.3J/cm2的情况下的载流子浓度分布。图7是比较了实施例和现有例的激光退火后的载流子浓度分布而得到的特性图。根据图7所示的结果确认了,在将长波长激光器的激光32、131的能量设为5.3J/cm2的情况下,在现有例中,长波长激光器的激光131的能量过弱,n型FS区域111(特别是FWD区域122中的n型FS区域111)无法活化。另一方面,确认了在实施例中,即使长波长激光器的激光32弱,n型FS区域11也被活化。
以上,本发明不限于上述的实施方式,在不脱离本发明的主旨的范围内可以进行各种改变。例如,在上述的实施方式中,以RC-IGBT为例进行了说明,但是可以适用于在距半导体基板(半导体芯片)的同一主面不同的深度配置有区域的各种结构的半导体装置。具体而言,例如本发明可以适用于在半导体基板仅配置有具备FS区域的FWD的结构的半导体装置、在构成电路部的多个半导体元件中的1个以上包括具备FS区域的FWD的结构的半导体装置。另外,本发明使导电型(n型,p型)反转也同样成立。
产业上的可利用性
如上所述,本发明的半导体装置的制造方法对于利用激光退火使通过离子注入而形成的区域活化而制作的半导体装置有用,特别是适于在距离半导体基板的背面比集电区和阴极区深的位置处具备FS区域的RC-IGBT。
Claims (9)
1.一种半导体装置的制造方法,其特征在于,包括:
第一工序,从半导体基板的一个主面以离子方式注入杂质而形成第一半导体区;
第二工序,从所述半导体基板的一个主面以离子方式注入杂质而在比所述第一半导体区浅的区域形成杂质浓度比所述第一半导体区的杂质浓度高的第二半导体区;
第三工序,从所述半导体基板的一个主面照射第一激光而使所述第二半导体区活化,并且将所述半导体基板的一个主面的表面层熔融而使其再结晶化;以及
第四工序,在所述第三工序之后,从所述半导体基板的一个主面照射波长比所述第一激光的波长长的第二激光而使所述第一半导体区活化,
在所述第三工序中,将所述第一激光的能量设为1J/cm2以上且2J/cm2以下,并将所述第一激光的脉冲宽度设为50ns以上且300ns以下,
在所述第四工序中,将所述第二激光的能量设为4J/cm2以上且8J/cm2以下,并使所述第二激光的脉冲宽度比所述第一激光的脉冲宽度长,且设为10μs以上。
2.根据权利要求1所述的半导体装置的制造方法,其特征在于,在所述第三工序中,将通过所述第一激光使杂质活化时的活化深度设为小于1μm。
3.根据权利要求1所述的半导体装置的制造方法,其特征在于,在所述第四工序中,将通过所述第二激光使杂质活化时的活化深度设为1μm以上且4μm以下。
4.根据权利要求1所述的半导体装置的制造方法,其特征在于,所述第一激光的波长为500nm以上且550nm以下。
5.根据权利要求1所述的半导体装置的制造方法,其特征在于,所述第二激光的波长为800nm以上。
6.根据权利要求1所述的半导体装置的制造方法,其特征在于,所述半导体装置的制造方法还包括:
第五工序,在第一导电型的所述半导体基板的另一个主面侧形成预定的元件结构;以及
第六工序,在所述第三工序之前,从所述半导体基板的一个主面以离子方式注入第二导电型杂质,在比所述第一半导体区浅的区域形成第二导电型的第三半导体区,该第三半导体区在与所述半导体基板的一个主面平行的方向上与所述第二半导体区并列地配置,
在所述第一工序中,从所述半导体基板的一个主面以离子方式注入第一导电型杂质而形成第一导电型的所述第一半导体区,
在所述第二工序中,从所述半导体基板的一个主面以离子方式注入第一导电型杂质而形成第一导电型的所述第二半导体区,
在所述第三工序中,照射所述第一激光而使所述第二半导体区和所述第三半导体区活化。
7.根据权利要求1所述的半导体装置的制造方法,其特征在于,在所述第一工序中,将离子注入的剂量设为5×1011/cm2以上且1×1014/cm2以下。
8.根据权利要求1~7中任一项所述的半导体装置的制造方法,其特征在于,在所述第二工序中,将离子注入的剂量设为1×1014/cm2以上且1×1016/cm2以下。
9.根据权利要求6所述的半导体装置的制造方法,其特征在于,在所述第六工序中,将离子注入的剂量设为1×1012/cm2以上且1×1015/cm2以下。
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