CN109638633A - 具有高回波损耗的to-壳体 - Google Patents

具有高回波损耗的to-壳体 Download PDF

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CN109638633A
CN109638633A CN201811171987.8A CN201811171987A CN109638633A CN 109638633 A CN109638633 A CN 109638633A CN 201811171987 A CN201811171987 A CN 201811171987A CN 109638633 A CN109638633 A CN 109638633A
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groove
shell
feedthrough
support
connecting pin
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CN109638633B (zh
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A·奥尤都马萨克
K·德勒格米勒
R·琼沃思
M·Y·方
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Schott AG
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Abstract

本发明涉及一种TO‑壳体,其具有用于光电元件的支座。所述支座包括电穿通件,所述电穿通件被设计成嵌入填料中的连接销。所述支座包括凹槽,在所述凹槽中,所述连接销中的至少一个在所述穿通件中的一个中被从所述支座的底侧中引出。

Description

具有高回波损耗的TO-壳体
技术领域
本发明涉及一种用于光电元件的TO-壳体。更特别地,本发明涉及一种用于数据传输的接收器或发射器激光二极管的TO-壳体。此外,本发明涉及一种用于制造TO-壳体的方法。
背景技术
用于光电元件的TO(Transistor-Outline(晶体管外形))壳体是已知的。这种壳体被用于发射器或接收器的激光二极管、特别是在数据信号传输的领域中。
特别地,现有技术的壳体由金属支座(德语:Sockel)构成,该金属支座具有包含用于传输数据信号的连接销的玻璃穿通件。从印刷电路板的连接点延伸到光电元件的信号路径的阻抗已经适配于光电元件的阻抗和/或适配于驱动、操作光电子部件或供应光电子部件能量的电子电路。根据其是否是具有一条或两条信号线的光电元件,在实际中常用的是25Ω、50Ω或100Ω的阻抗。
在玻璃穿通件内的信号线的部分在高频范围内可以被看作是电容,其中用于将信号线的连接销与光电元件连接的接合线可以被看作是电感。
为了匹配信号路径的阻抗,公开专利申请DE 10 2013 114 547A1(Schott股份公司)提出了提供一种印刷电路板(PCB)以距离TO-壳体的支座的底侧的一间距的连接点。
通过该间距,由于该间距连接销或者被空气或者被具有比穿通件的灌注混合物更小的介电常数εr的灌注混合物包围,在连接侧建立额外的电感,该电感可以用于匹配信号路径的阻抗。
已经发现,至少在一些应用中,难以精确地满足在PCB与TO-壳体的底侧之间的期望的距离。
发明内容
发明目的
有鉴于此,本发明基于的目的是提供一种具有良好阻抗特性的TO-壳体,其中至少减少了现有技术的上述缺点。更特别地,旨在进一步改善阻抗特性并且简化TO-壳体在印刷电路板上的安装。
发明概述
本发明的目的已经通过一种根据权利要求1所述的TO-壳体以及通过用于制造所述壳体的方法实现。
本发明的优选实施方式和改进方案可以在从属权利要求的主题、说明书以及附图中获得。
本发明涉及一种TO-壳体,其包括用于光电元件的支座(德语:Sockel)。支座尤其由金属制成并提供用于光电元件的安装区域。
优选地,在支座上放置具有窗口的盖子、特别是具有透镜形式的窗口的盖子。窗口使得用于数据传输的电磁辐射可以进入壳体内部和/或从壳体中出来。
支座具有至少一个电穿通件(Durchführungen),其是以至少一个嵌入在灌注混合物(德文:Vergussmasse,英文:potting compound,灌注胶)中的连接销的形式。优选地,支座包括多个穿通件,以及至少一个穿通件用作信号传导路径。
优选使用无机灌注混合物,特别是玻璃。
填料的介电常数εr(=ε/ε0)为优选小于4.5,特别优选小于4.0。
填料不仅用于连接销与支座的机械连接和壳体的气密密封而且用于连接销相对于支座的电绝缘。
根据本发明,支座包括凹槽,其中连接销在凹槽的区域中被从TO-壳体中延伸出。
凹槽被理解为一个有限的区域,该区域不在支座的整个表面上延伸并且在该区域内优选为板形的支座的厚度减小。
凹槽优选地被布置在支座的底侧上。
根据另一个实施方式,在支座的顶侧上,即在TO-壳体内侧上,也可以存在凹槽。而且,不仅在顶侧上而且在底侧上可以存在相对置的凹槽。
在一个穿通件中的连接销中的至少一个在凹槽内从支座的底侧中延伸出。由灌注混合物和连接销的嵌入灌注混合物中的部分组成的穿通件优选终止于凹槽的底部处。
因此,由于凹槽,穿通件的出口点与相邻的支座的底侧间隔开。
现在印刷电路板可以相邻地直接安装和连接到支座的底侧上。由于在底侧上布置有凹槽,因此产生与穿通件间隔开的连接点,这导致在穿通件下方产生一个附加的电感并且因此导致改善的阻抗特性。
为此,凹槽形成空腔或者也可以用一种材料、特别是塑料材料填充,该材料具有比穿通件的灌注混合物更低的介电常数εr,特别是用一种具有如下介电常数εr的材料,该εr比灌注混合物的介电常数小至少1.0。
优选地,壳体的支座是单层地,特别是构造成单件式的(一体的)。特别地,凹槽被压入到支座中。因此,可以特别容易地提供凹槽。
根据另一个实施方式,支座是构造成多层的,其中下壳体层具有通孔。在该实施方式中,上壳体层的底侧形成凹槽的底部。
在本发明的一个改进方案中,两个、特别是正好两个接触销在正好一个凹槽中被从底侧中延伸出。本发明的该实施方式尤其可以用于光电元件的TO-壳体,该光电元件用于对称的,必要时对称差分的信号传输(差分信号)。
但是,不言而喻,也可以设想,TO-壳体具有三个或更多个用于信号线的穿通件和/或各用于一个信号线的至少两个连接销各自处于一个唯一的凹槽中、特别是圆柱形的凹槽中。
优选地,TO-壳体还包括另外的连接销,其不用于信号线的连接。用于这些连接销的穿通件优选地不布置在一个凹槽中。而是,用于光电元件的供电和/或控制的连接销被布置在一直延伸到支座的底侧的填料中。
对于一个单独的连接销的穿通件来说,凹槽优选在俯视图上基本上是圆形的,特别地,凹槽以圆柱的形状来构造。特别地,在与圆形稍微偏离的形状的情况下,最大直径与最小直径的比最大为1.2。
对于具有两个连接销的穿通件,凹槽优选基本上以长孔的形状来构造。但是穿通件也可以构造成椭圆形的。
从支座的至少一侧出发的至少一个凹槽的深度,或者在两个凹槽的情况下,两个凹槽的总深度,最好为支座的厚度的1%至80%、优选为4%至65%、特别优选为15%至30%。如上所述,凹槽可以从一侧或两侧发出,其中在双侧凹槽的情况下各个深度可以彼此不相同。
根据一个优选的实施方式,用于调节阻抗特性的凹槽至少在支座与凹槽相邻的区域中占支座的高度的20%至50%、优选35%至45%。因此,凹槽的深度为在凹槽区域中的支座的厚度的20%至50%。
优选地,布置在凹槽中的导体电路部分(Leiterbahnabschnitt),该导体电路部分即从穿通件的下端一直延伸到印刷电路板上的连接点,具有比布置在电穿通件中的导体电路部分高1.2至4倍、优选1.6至2.7倍的阻抗,布置在电穿通件中的该导体电路部分从支座的底侧一直延伸到支座的顶侧并且因此被灌注混合物包围。
在本发明的意义上的阻抗被理解为导线的特征阻抗(波阻抗)。
在行进波中的电压和电流的比是导线的特征阻抗。特征波阻抗是导线的特征。特征波阻抗由横截面尺寸和材料常数得出。因此,特征波阻抗是导线常数。特征波阻抗是与位置无关的(只要导线不变),并且对于高的频率、特别是对于在此相关的频率(5GHz以上),是与频率无关的。
通过本发明可以在20GHz下实现超过12dB、优选地超过15dB的回波损耗。
特别地,成功提供一种TO-壳体,其中回波损耗特别是在10至20GHz的范围内形成一个平台,在该平台内回波损耗位于10和35dB之间、优选地在15和20dB之间。通过合理设计壳体的几何形状和/或材料,可以至少在朝向更高的频率方向上实现间隔的移位和/或展宽。
优选地,在10至20GHz的范围内,壳体的信号路径的回波损耗位于正/负2.5dB之间的范围内,即在5dB的窗口内。
插入损耗在10至20GHz的范围内优选为小于0.5dB。
如果TO-壳体被装配有光电元件并且被连接到导体电路上,特别是被连接到柔性的导体电路,那么信号路径的阻抗特别地为10至150Ω、优选在40至60Ω之间或在20至30Ω之间或在90至110Ω之间。
如果TO-壳体被连接到具有电子电路的印刷电路板上,则在印刷电路板上的电子电路优选具有信号路径的阻抗正/负5Ω。
因此,电子电路的阻抗至少大致对应于信号路径的阻抗。电子电路的阻抗和光电元件的阻抗确定了TO-壳体关于信号导线路径的阻抗并且因此特别是关于凹槽的构造的设计。
信号路径在此情况下从导体电路上的连接点一直延伸到光电元件上的连接点。因此,信号路径由在凹槽区域中的电感、由在穿通件区域中的电容和通过接合线形成的电感组成。
凹槽的宽度或直径优选为由连接销和灌注混合物形成的电穿通件的直径或宽度的1.0至4.0倍、优选1.0至3.0倍和特别优选1.2至2.5倍。
凹槽的宽度或直径优选为连接销的布置在电穿通件中的部分的直径的1.5-5.0倍、优选2.0-3.0倍。
凹槽的深度优选为0.1至1.5mm、特别优选为0.4至0.8mm。在具有非平的底部的凹槽的情况下,该深度被理解为最大深度。但是,优选地,凹槽的底部是平的。
根据本发明的TO-壳体包括支座,该支座优选地被冲压成形,其中凹槽被压入,特别是在冲压期间。
TO-壳体的支座因此可以简单地制造。根据应用目的的情况,支座可以通过简单的方式制成具有不同深度的凹槽。通过凹槽的几何形状、特别是凹槽的深度,可以以简单的方式使信号路径的阻抗适配于相应的应用。
附图说明
下面将参考附图1至9通过示实施例阐述了本发明的主题。
图1是根据本发明的TO-壳体的实施例的支座的顶侧的俯视图,该壳体已经装配了光电元件。
图2是在图1中所示的TO-壳体的底侧上的透视图。
图3也以透视图示出了TO-壳体的一个替代实施方式的底侧,在该壳体中两个分开的连接销分别布置在一个穿通件中。
图4是一个凹槽连同具有至少一个连接销的穿通件一起的详细图示,借助于该详细图示,将更详细地解释穿通件以及凹槽的尺寸设计。
图5是根据本发明的TO-壳体的示意侧视图。
图6示出了在图5中所示的TO-壳体如何连接到印刷电路板上。
在根据图7的曲线图中绘制了回波损耗和在根据图8的曲线图中绘制了根据本发明的TO-壳体的插入损耗,其分别为频率的函数。
图9是TO-壳体的另一个实施方式的示意剖视图,在该壳体中在顶侧上也存在凹槽。
具体实施方式
图1是在俯视图中示出根据本发明的TO-壳体1的支座2的顶侧。完整的TO-壳体1可以包括安放到该支座2的带有窗口的盖子(未示出)。
支座2在该实施例中构造成圆柱形的并且尤其可以由冲压成形的金属部件制成。
特别地,支座2可以由钢制成。此外,支座可以具有涂层、特别是含金的涂层。
通过支座2形成用于光电元件6的安装区域。
在该实施例中,光电元件6包括光电二极管7,其安装在放大器8上。
在该实施例中,TO-壳体1包括连接销3a和3b,它们设计成用于输入和输出信号的信号导线连接销。
连接销3a和3b被嵌入灌注混合物5、特别是由玻璃制成的灌注混合物5中,由此形成电穿通件。
通过接合线9a,9b,连接销3a和3b在TO-壳体内与光电元件6相连接。
应当理解,这种TO-壳体1通常还包括另外的连接销4。这些连接销也可以嵌入到灌注混合物、特别是由玻璃制成的灌注混合物中。
但是,与连接销3a和3b相反,连接销4不是用于输入信号或输出信号的传输,而是用于电流供给或用作光电元件6的控制线。因此,对通过连接销4引导的信号路径的阻抗特性通常提出不太高的要求。
图2在从底侧11看的透视图中示出了在图1中所示的TO-壳体1。可以看出,具有连接销3a和3b的穿通件被布置在凹槽10中,该穿通件包括灌注混合物5以及连接销3a,3b。在该实施例中,两个连接销3a,3b被布置在一个唯一的穿通件中。
凹槽10是构造成长孔形的并且使得连接销3a,3b不在底侧11的高度上,而是与其间隔开地,并且是大致在凹槽10的底部的高度处从支座2中伸出。
为了更清楚起见,在该图示中未画出不用作信号线的其它的连接销(图1中的4)。
支座2优选单件式地(一体地)构造,特别地,凹槽10被压入。
图3示出了TO-壳体1的一个相对于图1/图2替代的实施方式。在该实施方式中,各将一个单独的连接销3a,3b布置在一个单独的穿通件中。该穿通件在此情况下分别由一个单独的连接销3a,3b和灌注混合物5组成,连接销3a,3b被嵌入到该灌注混合物中。
在该实施例中,设置两个分开的凹槽10,由此每个连接销3a,3b的穿通件被布置在自己的凹槽10中。
因此,在该实施例中,相应的凹槽10是构造成圆柱形的。
在这里示出的实施例中,支座2是两层地构造成的。但是应该理解,在图3中所示的具有两个分开的穿通件的实施方式也可以单层地设计。
否则,在图3中所示的实施例也可以对应于之前在图1/图2中所示的实施例。
参照图4,借助于实施例更详细地解释凹槽和穿通件的优选的尺寸设计,但是,这适用于本发明的所有实施方式,而不仅仅适用于在前述附图中示出的实施方式。
如在此处所示的那样,在两个连接销3a,3b布置在穿通件14中的情况下,凹槽10具有1至5mm、优选1.2至2.75mm的长度lc。此外,凹槽具有优选0.3至3mm、特别优选0.7至1.8mm的宽度dc
在用于具有一个单独的连接销(此处未示出)的穿通件的、圆柱形的凹槽10的情况下,其直径dc为0.3至3mm、优选为0.7至1.8mm。
凹槽10具有优选0.1至1.5mm、特别优选0.4至0.8mm的深度。
灌注混合物5可以具有0.7至1.4mm的宽度,或者在用于一个单独的连接销的、圆柱形的设计方案的情况下,的直径dg和/或1.45至2.35mm的长度lg
在具有两个彼此间隔开的连接销3a,3b的穿通件14的情况下,距离p可以为在0.5和0.95mm之间。
在穿通件14中的各个的连接销3a,3b的直径优选为0.2至0.5mm。
连接销3a,3b可以具有加厚的头部或者可以在壳体内侧成角度地构造,这尤其可以用于减小接合线(在图1中的9a,9b)的长度。
优选地,凹槽的宽度是穿通件14的尺寸的1.2至1.5倍、优选1.5至2倍,或者直径是穿通件14的尺寸的1.2至5倍、优选为1.5至2倍。
图5在示意剖视图中示出了在图1/图2中示出的TO-壳体1。
可以看出,通过灌注混合物5和布置在灌注混合物5中的连接销3a的部分形成的穿通件14延伸穿过支座2。
在该实施例中,连接销3a(优选地还有连接销3b)具有加厚的头部12。由此可以减小接合线9a的长度,连接销3a通过该接合线与光电元件6连接。
在穿通件下方布置凹槽10,该凹槽导致灌注混合物5并且因此导致穿通件终止在支座2的底侧11的上方,特别是大致在凹槽10的底部的高度上。
图6示出了现在如何将印刷电路板13、特别是柔性印刷电路板13连接到TO-壳体1上。印刷电路板13被施加到支座2的底侧(在图5中的11)上,即至少以其顶侧位于支座2的底侧的水平上。
由于凹槽10,印刷电路板13和连接销3a的接触区域15与穿通件14间隔开。
在接触区域15和穿通件14之间的距离在此情况下基本上对应于凹槽10的深度t。
由于凹槽10或者被构造成空腔或者被用具有比灌注混合物5更低的介电常数的材料填充,因此产生电感。
印刷电路板13的连接和接触区域15与穿通件14的限定距离的保持可以以简单的方式实现。
为了连接,印刷电路板13的接触线路可以被穿孔。然后,连接销3a,3b被引导穿过相应的孔,直到印刷电路板13搁置在支座2的底侧上,并且接触区域15可以以简单的方式通过焊接而被连接。
其他的连接销4可以以相同的方式进行接触,其中在连接销4的穿通件下方没有凹槽,从而印刷电路板13与这些连接销4中的一个的相应的穿通件直接相邻。
还可以看出,在穿通件14的出口区域16中,灌注混合物5可以在熔化期间在连接销3a上提升。连接销3a然后也在凹槽10的底部上方被由灌注混合物5构成的一个部分包裹。这可以必要时通过相应更深的凹槽10来补偿。
在根据图7的图示中的曲线图示出了在与没有凹槽(虚线)的TO-壳体相比较下,TO-壳体(实线)的根据本发明的实施例的以dB为单位的回波损耗(return loss(回波损耗))。
在x轴上给出以GHz为单位的频率和在y轴上给出以dB为单位的回波损耗。
回波损耗是在反射信号和输入信号之间的对数比。回波损耗越大,部件的阻抗上的匹配就越好。例如如果回波损耗为-3dB,则仅还有50%的信号被传输,而在-10dB下仍然有90%的信号被传输。
可以看出,在10至20GHz的频率范围内,形成一个平台并且回波损耗在10GHz处就已经大约高出5dB。
在没有凹槽的TO-壳体中,即使在针对优选规定的应用的10至20GHz中,回波损耗也连续地增加。
在20GHz处,通过TO-壳体的根据本发明的设计可以实现高出5dB以上的回波损耗。
特别地,可以提供一种TO-壳体,其中回波损耗在10和20GHz之间的整个范围内处在-15和-20dB之间。
在20GHz以上,在根据本发明的TO-壳体中,回波损耗也连续地减小并且在30GHz以上甚至比在没有凹槽的TO-壳体中更低。因此,根据本发明的TO-壳体特别适用于高于10GHz但低于20GHz的应用。
图8以相同的图示示出了在与没有凹槽的TO-壳体(虚线)相比较下,根据本发明的TO-壳体(实线)的插入损耗(insertion loss(插入损耗))。
可以看出,根据本发明的TO-壳体也具有改善的插入损耗。因此,插入损耗在10和20GHz之间的整个频率范围内较低。
不言而喻,在针对相应的应用所使用的频率范围内应该实现尽可能高的回波损耗和低的插入损耗。
特别有利的是,通过本发明可以实现在宽频率范围内几乎恒定的回波损耗。
图9是TO-壳体1的另一个实施反射的示意性剖视图,其中支座2不仅在顶侧上而且在底侧都分别具有凹槽10a,10b。
连接销3a在凹槽10a,10b内在穿通件14中被引导穿过支座2。
除此之外,该TO-壳体可以对应于前面描述的TO-壳体。
在另一个未示出的实施反射中,也可以仅在顶侧上存在凹槽。
附图标记清单
1 TO-壳体
2 支座
3a,3b 连接销
4 连接销
5 灌注混合物
6 光电元件
7 光电二极管
8 放大器
9a,9b 接合线
10,10a,10b 凹槽
11 底侧
12 头部
13 印刷电路板
14 穿通件
15 接触区域
16 出口区域

Claims (15)

1.一种TO-壳体,包括用于光电元件的支座,其中所述支座具有至少一个电穿通件,所述电穿通件被设计成嵌入特别是由玻璃制成的灌注混合物中的连接销的形式,其特征在于,所述支座优选在底侧上包括凹槽,在所述凹槽中,所述连接销中的至少一个在所述穿通件中的一个中从所述支座的所述底侧中延伸出。
2.根据前述权利要求所述的TO-壳体,其特征在于,两个连接销、特别是正好两个连接销在正好一个凹槽中从所述底侧中延伸出。
3.根据前述权利要求中任一项所述的TO-壳体,其特征在于,所述凹槽形成空腔或被用一种具有比所述灌注混合物更小的介电常数的材料填充。
4.根据前述权利要求中任一项所述的TO-壳体,其特征在于,所述凹槽在横截面上基本上是圆形地或以长孔的形式构造。
5.根据前述权利要求中任一项所述的TO-壳体,其特征在于,所述凹槽具有:
1-5mm、优选1.2-2.75mm的长度lc,0.3-3mm、优选0.7-1.8mm的宽度dc或0.3-3mm、优选0.7-1.8mm的直径,
和/或0.1-1.5mm、优选0.4-0.8mm的深度,
和/或所述穿通件具有0.7-1.4mm的宽度或直径dg和/或1.45-2.35mm的长度lg
和/或两个布置在穿通件中的连接销具有在0.5mm和0.95mm之间的距离p,
和/或在穿通件中的至少一个连接销的直径为0.2mm至0.5mm,
和/或所述凹槽具有所述穿通件的1.2-5倍、优选1.5-2倍的宽度/直径。
6.根据前述权利要求中任一项所述的TO-壳体,其特征在于,所述凹槽占所述支座至少在与所述凹槽相邻的区域中的高度的20%-50%、优选35%-45%。
7.根据前述权利要求中任一项所述的TO-壳体,其特征在于,布置在所述凹槽中的导体电路部分的阻抗是布置在电穿通件中的导体电路部分的阻抗的1.2至4倍、优选1.6至2.7倍。
8.根据前述权利要求中任一项所述的TO-壳体,其特征在于,所述TO-壳体装配有光电元件并被连接到导体电路上,其中在所述导体电路上的一个连接点和在所述光电元件上的一个连接点之间延伸的信号路径的阻抗为在10Ω和150Ω之间、优选在40Ω和60Ω之间或在20Ω和30Ω之间或在90Ω和110Ω之间。
9.根据前述权利要求中任一项所述的TO-壳体,其特征在于,所述连接销被连接到印刷电路板、特别是柔性印刷电路板上,其中所述印刷电路板和所述连接销的至少一个连接点位于大约支座的底侧的水平上。
10.根据前述权利要求中任一项所述的TO-壳体,其特征在于,所述凹槽的宽度或直径是所述电穿通件的直径的1.0至4.0倍、优选1.0至3.0倍、特别优选1.2至2.5倍。
11.根据前述权利要求中任一项所述的TO-壳体,其特征在于,所述凹槽的宽度或直径是所述连接销的布置在所述电穿通件中的部分的直径的1.5-5.0倍、优选2.0-3.0倍。
12.根据前述权利要求中任一项所述的壳体,其特征在于,所述支座是单层的,特别是构成为单件式的。
13.根据前述权利要求中任一项所述的壳体,其特征在于,所述壳体的信号路径的回波损耗在10至20GHz的范围中形成一个平台,在该平台内回波损耗处于10至35dB之间、优选处于15至20dB之间,
和/或在10至20GHz的范围中,所述壳体的信号路径的回波损耗处在正/负2.5dB之间的范围中。
14.一种用于制造根据前述权利要求中任一项所述的TO-壳体的方法,其中所述TO-壳体的支座被冲压成形并且所述凹槽通过压入而成形。
15.根据前述权利要求所述的方法,其特征在于,所述凹槽在冲压期间被压入。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110225673A (zh) * 2019-07-02 2019-09-10 深圳市友华通信技术有限公司 Pcba制作方法和pcba

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102018120893B4 (de) * 2018-08-27 2022-01-27 Schott Ag TO-Gehäuse mit einer Durchführung aus Glas
JP7398877B2 (ja) * 2019-04-18 2023-12-15 新光電気工業株式会社 半導体装置用ステム及び半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090003003A1 (en) * 2004-08-25 2009-01-01 Byoung Jae Park Light Emitting Device, Light Emitting Device Package Structure, and Method of Manufacturing the Light Emitting Device Package Structure
CN101668786A (zh) * 2007-04-24 2010-03-10 日立化成工业株式会社 固化性树脂组合物、led封装件及其制造方法、以及光半导体
US20100326723A1 (en) * 2007-07-17 2010-12-30 Cochlear Limited Electrically insulative structure having holes for feedthroughs
CN105977246A (zh) * 2015-03-11 2016-09-28 Lg伊诺特有限公司 发光器件

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4951011A (en) * 1986-07-24 1990-08-21 Harris Corporation Impedance matched plug-in package for high speed microwave integrated circuits
US4816791A (en) * 1987-11-27 1989-03-28 General Electric Company Stripline to stripline coaxial transition
JPH11186425A (ja) * 1997-12-24 1999-07-09 Sharp Corp 高周波モジュールデバイス
DE60333547D1 (de) * 2002-02-28 2010-09-09 Greatbatch Ltd Emi-durchgangsfilteranschlussbaugruppe für humanimplantationsanwendungen mit oxidresistenten biostabilen leitfähigen kontaktstellen für zuverlässige elektrische anbringungen
US6841815B2 (en) * 2002-03-19 2005-01-11 Finisar Corporation Transimpedance amplifier assembly with separate ground leads and separate power leads for included circuits
CN1253982C (zh) 2002-04-20 2006-04-26 富士康(昆山)电脑接插件有限公司 激光器引脚和底座的封装结构及其封装方法
JP3998526B2 (ja) * 2002-07-12 2007-10-31 三菱電機株式会社 光半導体用パッケージ
US7061949B1 (en) * 2002-08-16 2006-06-13 Jds Uniphase Corporation Methods, apparatus, and systems with semiconductor laser packaging for high modulation bandwidth
DE10247315B4 (de) * 2002-10-10 2005-12-15 Schott Ag TO-Gehäuse für Hochfrequenzanwendungen - Verdrahtungsträger aus Keramik
US7456945B2 (en) * 2002-10-28 2008-11-25 Finisar Corporation Photonic device package with aligned lens cap
KR100456308B1 (ko) * 2002-11-14 2004-11-10 주식회사 래피더스 10기가비피에스급 광모듈용 티오-캔 패키지
JP2004253419A (ja) 2003-02-18 2004-09-09 Sumitomo Electric Ind Ltd 光半導体パッケージ
US7221829B2 (en) * 2003-02-24 2007-05-22 Ngk Spark Plug Co., Ltd. Substrate assembly for supporting optical component and method of producing the same
JP4279134B2 (ja) * 2003-12-24 2009-06-17 三菱電機株式会社 半導体用パッケージ及び半導体デバイス
KR100635210B1 (ko) 2004-06-11 2006-10-16 주식회사 엘지화학 중공부를 포함하는 점착시트 및 이들의 제조 방법
JP4756840B2 (ja) * 2004-09-13 2011-08-24 三菱電機株式会社 キャンパッケージ型光半導体装置および光モジュール
WO2006073085A1 (ja) * 2005-01-04 2006-07-13 I Square Reserch Co., Ltd. 固体撮像装置及びその製造方法
JP2007088233A (ja) * 2005-09-22 2007-04-05 Nec Electronics Corp 光モジュール
JP5003110B2 (ja) * 2006-11-15 2012-08-15 住友電気工業株式会社 光電変換モジュール
JP2009105284A (ja) * 2007-10-24 2009-05-14 Sumitomo Electric Ind Ltd 回路素子パッケージ
JP2011100785A (ja) * 2009-11-04 2011-05-19 Nippon Telegr & Teleph Corp <Ntt> To−can形光モジュール用パッケージおよびto−can形光モジュール
JP5144628B2 (ja) * 2009-11-19 2013-02-13 日本電信電話株式会社 To−can型tosaモジュール
JP5473583B2 (ja) * 2009-12-22 2014-04-16 京セラ株式会社 電子部品搭載用パッケージおよびそれを用いた電子装置
JP5334887B2 (ja) * 2010-02-22 2013-11-06 京セラ株式会社 電子部品搭載用パッケージおよびそれを用いた電子装置
JP5409432B2 (ja) * 2010-02-23 2014-02-05 京セラ株式会社 電子部品搭載用パッケージおよびそれを用いた電子装置
JP5705491B2 (ja) * 2010-09-30 2015-04-22 京セラ株式会社 電子部品搭載用パッケージおよびそれを用いた電子装置
JP5553421B2 (ja) 2011-08-01 2014-07-16 株式会社ルネッサンス・エナジー・リサーチ Co2促進輸送膜及びその製造方法
DE102013114547B4 (de) * 2013-01-18 2020-01-16 Schott Ag TO-Gehäuse
JP6166101B2 (ja) * 2013-05-29 2017-07-19 京セラ株式会社 光半導体素子収納用パッケージおよびこれを備えた実装構造体
KR101542443B1 (ko) * 2013-06-19 2015-08-06 주식회사 포벨 고속 통신용 to형 광소자 패키지
JP6412274B2 (ja) * 2015-08-24 2018-10-24 京セラ株式会社 電子部品搭載用パッケージおよびそれを用いた電子装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090003003A1 (en) * 2004-08-25 2009-01-01 Byoung Jae Park Light Emitting Device, Light Emitting Device Package Structure, and Method of Manufacturing the Light Emitting Device Package Structure
CN101668786A (zh) * 2007-04-24 2010-03-10 日立化成工业株式会社 固化性树脂组合物、led封装件及其制造方法、以及光半导体
US20100326723A1 (en) * 2007-07-17 2010-12-30 Cochlear Limited Electrically insulative structure having holes for feedthroughs
CN105977246A (zh) * 2015-03-11 2016-09-28 Lg伊诺特有限公司 发光器件

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110225673A (zh) * 2019-07-02 2019-09-10 深圳市友华通信技术有限公司 Pcba制作方法和pcba
CN110225673B (zh) * 2019-07-02 2024-03-19 深圳市友华通信技术有限公司 Pcba制作方法和pcba

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