CN109560076A - 集成扇出型封装 - Google Patents

集成扇出型封装 Download PDF

Info

Publication number
CN109560076A
CN109560076A CN201711131655.2A CN201711131655A CN109560076A CN 109560076 A CN109560076 A CN 109560076A CN 201711131655 A CN201711131655 A CN 201711131655A CN 109560076 A CN109560076 A CN 109560076A
Authority
CN
China
Prior art keywords
tube core
height
conductive column
active surface
adhesion coating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201711131655.2A
Other languages
English (en)
Inventor
洪艾蒂
陈星兆
谢静华
林志伟
林敬尧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN109560076A publication Critical patent/CN109560076A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/11845—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191—Forming a passivation layer after forming the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24101—Connecting bonding areas at the same height
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2512—Layout
    • H01L2224/25171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种集成扇出型封装包括第一管芯及第二管芯、包封体、及重布线结构。第一管芯及第二管芯分别具有有源表面、与有源表面相对的后表面、及位于有源表面上的导电柱。第一与第二管芯是不同类型的管芯。第一管芯的有源表面及后表面分别与第二管芯的有源表面及后表面齐平。第一管芯的导电柱的顶表面与第二管芯的导电柱的顶表面齐平。第一管芯的导电柱与第二管芯的导电柱被相同的材料包绕。包封体包封第一管芯的侧壁及第二管芯的侧壁。包封体的第一表面与有源表面齐平且第二表面与后表面齐平。重布线结构设置在第一管芯、第二管芯、及包封体上。

Description

集成扇出型封装
技术领域
本发明实施例涉及一种集成扇出型封装。更具体来说，本发明实施例涉及一种具有不同类型管芯的集成扇出型封装。
背景技术
近来，由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续提高，半导体行业已经历快速增长。在很大程度上，集成密度的此种提高来自于最小特征大小(minimum feature size)的相继减小，此使得更多组件能够集成到给定区域中。当前，集成扇出型封装因其紧凑性而正变得日渐流行。在集成扇出型封装中，模塑化合物的平坦化及重布线路结构的形成在封装工艺期间至关重要。
发明内容
一种集成扇出型封装包括第一管芯及第二管芯、包封体、及重布线结构。第一管芯及第二管芯分别具有有源表面、与有源表面相对的后表面、及位于有源表面上的导电柱。第一管芯与第二管芯是不同类型的管芯。第一管芯的有源表面及后表面分别与第二管芯的有源表面及后表面齐平。第一管芯的导电柱的顶表面与第二管芯的导电柱的顶表面齐平。第一管芯的导电柱与第二管芯的导电柱被相同的材料包绕。包封体包封第一管芯的侧壁及第二管芯的侧壁。包封体的第一表面与有源表面齐平。包封体的第二表面与后表面齐平。重布线结构设置在第一管芯、第二管芯、及包封体上。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1A至图1N示出根据本发明一些实施例的制造集成扇出型封装的方法中的各个阶段的示意性剖视图。
图2A至图2M示出根据本发明一些替代实施例的制造集成扇出型封装的方法中的各个阶段的示意性剖视图。
附图标号说明
10、20：集成扇出型封装
100：第一载板
110、610：剥离层
200、200’、210：粘着层
200a：表面
210a、500a、510a、700a、710a：第一表面
210b、500b、510b、700b：第二表面
300：第一管芯
300a、400a：有源表面
300b、300b’、400b、400b’：后表面
310、310’、410、410’：导电柱
310a’：顶表面
400：第二管芯
500：包封材料
510：包封体
600：第二载板
620：管芯贴合膜
700：基底材料层
710：基底层
800：重布线结构
802：重布线导电图案
804：介电层
806：导通孔
900：导电端子
H200、H200’、H210、H300、H300’、H310、H310’、H400、H400’、H410、H410’、H500、H510、H700、H710：高度
SW300、SW400：侧壁
TP1：剥离载体
TP2：分割载体
X、Z：方向
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及配置形式的具体实例以简化本公开内容。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种例子中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或其他取向)，且本文中所用的空间相对性用语可同样相应地进行解释。
也可包括其他特征及工艺。举例来说，可包括测试结构，以帮助对三维(threedimensional，3D)封装或三维集成电路(three dimensional integrated circuit，3DIC)装置进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试接垫(test pad)，以允许对三维封装或三维集成电路进行测试、对探针及/或探针卡(probecard)进行使用等。可对中间结构以及最终结构执行验证测试。另外，可将本文中所公开的结构及方法与包括对已知良好管芯进行中间验证的测试方法结合使用，以提高良率并降低成本。
图1A至图1N示出根据本发明一些实施例的制造集成扇出型封装10的方法中的各个阶段的示意性剖视图。参照图1A，提供第一载板100。在第一载板100上依序形成剥离层110及粘着层200。在一些实施例中，第一载板100是玻璃衬底。然而，其他材料也可适于作为第一载板100的材料，只要所述材料能够在承载在其上面形成的封装结构的同时耐受后续工艺即可。在一些实施例中，剥离层110是形成在玻璃衬底上的光热转换(light-to-heatconversion，LTHC)释放层。光热转换释放层可通过利用例如紫外(ultra-violet，UV)光进行照射来实现剥离。在一些实施例中，粘着层200包含弹性聚合物材料(elastic polymericmaterial)或包括由弹性聚合物材料所形成的层。弹性聚合物材料例如是酚醛树脂(phenolresin)、环氧树脂(epoxy resin)、或丙烯酸聚合物(acrylic polymer)。在一些实施例中，可在弹性聚合物材料中添加无机填料，例如二氧化硅(SiO2)。在一些实施例中，粘着层200可用作热释放膜或紫外释放膜。热释放膜可在所述膜被加热到特定温度时剥除，且紫外释放膜可在被紫外光曝光之后被剥除。在一些实施例中，粘着层200包含粘着性质。在一些实施例中，粘着层200能够容纳接着在上面形成的管芯的导电柱，且能够良好地密封管芯的表面。
参照图1B，提供多个第一管芯300及多个第二管芯400。每一个第一管芯300具有有源表面300a、与有源表面300a相对的后表面300b、以及形成在有源表面300a上的多个导电柱310。每一个第二管芯400具有有源表面400a、与有源表面400a相对的后表面400b、以及形成在有源表面400a上的多个导电柱410。第一管芯300的导电柱310及第二管芯400的导电柱410可包括例如铜柱。在一些实施例中，第一管芯300可包括相同类型的芯片且可选自：应用专用集成电路(application-specific integrated circuit，“ASIC”)芯片、模拟芯片(analog chip)、传感器芯片、无线射频芯片(wireless and radio frequency chip)、电压调节器芯片或存储器芯片。在一些实施例中，第二管芯400可包括相同类型的芯片且可选自：应用专用集成电路(“ASIC”)芯片、模拟芯片、传感器芯片、无线射频芯片、电压调节器芯片或存储器芯片。在某些实施例中，第一管芯300与第二管芯400是不同类型的管芯。举例来说，第一管芯300与第二管芯400可囊括不同类型的芯片或不同的电子组件或元件。根据应用而定，第一管芯300与第二管芯400可执行不同的功能。在一些实施例中，第一管芯300可为系统芯片(system on chip，SoC)管芯且第二管芯400可为高带宽存储器(highbandwidth memory，HBM)管芯。然而，本发明实施例并非仅限于此，且第一管芯300与第二管芯400可基于产品需要而为其他类型的管芯。由于第一管芯300与第二管芯400是不同类型的管芯，因此第一管芯300的大小及高度与第二管芯400的大小及高度将不同。举例来说，如图1B所示，第一管芯300的高度(由高度H300与高度H310之和表示)不同于第二管芯400的高度(由高度H400与高度H410之和表示)。应注意，在本公开内容通篇中，元件的高度是指元件的有源表面与后表面之间在厚度方向Z上的距离。在一些实施例中，高度H400不同于高度H300。此外，第一管芯300的导电柱310的高度H310也可不同于第二管芯400的导电柱410的高度H410。应注意，由于导电柱310的高度H310及导电柱410的高度H410比高度H300及高度H400小很多而可忽略不计，因此在本发明中出于简明的目的，将高度H300称为第一管芯300的高度且将高度H400称为第二管芯400的高度。
在粘着层200上将第一管芯300及第二管芯400放置成使得有源表面300a、400a面对粘着层200。将第一管芯300及第二管芯400压抵在粘着层200上。应注意，在压抵之前，第一管芯300的有源表面300a及第二管芯400的有源表面400a被暴露出。换句话说，第一管芯300及第二管芯400是在其有源表面300a、400a上未形成有介电层(例如，聚苯并恶唑(polybenzooxazole，PBO)层)的裸露管芯(bare die)。由此，当第一管芯300及第二管芯400被压抵在粘着层200上时，第一管芯300的有源表面300a及第二管芯400的有源表面400a直接接触粘着层的表面200a。在一些实施例中，粘着层200的高度H200至少等于或大于第一管芯300的导电柱310的高度H310以及第二管芯400的导电柱410的高度H410。由此，当第一管芯300及第二管芯400被压抵在粘着层200上时，第一管芯300的导电柱310及第二管芯400的导电柱410可完全浸没(submerge)在粘着层200中。换句话说，导电柱310、410被粘着层200包封或良好地保护。
如图1B所示，由于第一管芯300与第二管芯400的高度差，因此在压抵工艺之后，第二管芯400的后表面400b位于比第一管芯300的后表面300b高的水平高度处。应注意，在图1B中分别示出两个第一管芯300及两个第二管芯400。然而，在一些替代实施例中，第一管芯300及第二管芯400的数目可基于需要而变化。
参照图1C，在粘着层200上形成包封材料500。包封材料500的第一表面500a接触粘着层200。在一些实施例中，包封材料500的高度H500大于第一管芯300的高度H300以及第二管芯400的高度H400。由此，包封材料500完全包封第一管芯300及第二管芯400。换句话说，包封材料500的第二表面500b位于比第一管芯300的后表面300b及第二管芯400的后表面400b两者高的水平高度处。第一管芯300及第二管芯400不被显露出且受到包封材料500的良好保护。在一些实施例中，包封材料500可为由模塑工艺(molding process)形成的模塑化合物(molding compound)。然而，在一些替代实施例中，包封材料500可由绝缘材料(例如，环氧树脂或其他合适的树脂)所形成。同时，包封材料500可通过与所选择的绝缘材料对应的其他工艺形成。
参照图1D，执行薄化工艺以减小包封材料500的高度H500、第一管芯300的高度H300以及第二管芯400的高度H400。在一些实施例中，移除包封材料500的一部分以形成包封体510且暴露出每一个第一管芯300及每一个第二管芯400。在一些实施例中，薄化工艺包括机械研磨工艺、化学机械抛光(chemical mechanical polishing，CMP)工艺、或其组合。在一些实施例中，通过研磨来减小包封材料500的高度H500、第一管芯300的高度H300、以及第二管芯的高度H400。在一些实施例中，如上所述，第一管芯300的高度H300不同于第二管芯400的高度H400。当局部地移除包封材料500以暴露出后表面300b、400b中的一者时，后表面300b、400b中的另一者仍被包封材料500覆盖。因此，进一步移除后表面300b、400b中的至少一者直到暴露出另一个后表面300b、400b为止。在一些替代实施例中，在后表面300b、400b两者均被暴露出之后，可对第一管芯300、第二管芯400、及包封材料500继续进行研磨工艺以进一步减小后续所形成的封装的总体厚度。
如图1D所示，包封体510的第一表面510a与第一管芯300的有源表面300a及第二管芯400的有源表面400a齐平。包封体510的第二表面510b与第一管芯300的后表面300b及第二管芯400的后表面400b齐平。第一管芯300的侧壁SW300及第二管芯400的侧壁SW400被包封体510包封。在一些实施例中，包封体510的高度H510实质上等于经薄化的第一管芯300的高度H300’以及经薄化的第二管芯400的高度H400’。
参照图1E，提供上面依序地形成有剥离层610及管芯贴合膜(die attach film，DAF)620的第二载板600。在一些实施例中，第二载板600可相似于第一载板100且剥离层610可相似于剥离层110，因此在本文中将不再对其予以赘述。第一管芯300的后表面300b’及第二管芯400的后表面400b’贴合到管芯贴合膜620。
参照图1E至图1G，将第一载板100及剥离层110从粘着层200分离且接着移除第一载板100及剥离层110。在一些实施例中，可通过紫外激光(UV laser)来照射剥离层110(例如，光热转换释放层)，以使得粘着层200从第一载板100剥除。在将粘着层200从第一载板100分离之后，将所述结构上下翻转以获得如图1F所示的结构。
参照图1G，从第一管芯300、第二管芯400、及包封体510移除粘着层200，以使得包封体510的第一表面510a、第一管芯300的有源表面300a、及第二管芯400的有源表面400a暴露出。在一些实施例中，可通过剥除工艺(peel off process)、溶剂洗脱工艺(solventwash off process)、或刻蚀工艺来移除粘着层200。
参照图1H，在包封体510的第一表面510a、第一管芯300的有源表面300a、及第二管芯400的有源表面400a上形成基底材料层700。基底材料层700具有第一表面700a及与第一表面700a相对的第二表面700b。在一些实施例中，基底材料层700直接形成在包封体510上以覆盖第一管芯300的导电柱310及第二管芯400的导电柱410，并使得基底材料层700的第二表面700b接触包封体510的第一表面510a。基底材料层700的高度H700大于第一管芯300的导电柱310的高度H310及第二管芯400的导电柱410的高度H410。换句话说，导电柱310、410两者均被基底材料层700包封。也就是说，导电柱310、410两者被相同的材料包绕。在一些实施例中，基底材料层700由介电材料所形成。介电材料包括例如聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(benzocyclobutene，BCB)、聚苯并恶唑(PBO)或任何其他适合的聚合物系介电材料。在一些实施例中，基底材料层700可包含粒径比传统的模塑化合物或包封体的填料小的填料。在一些替代实施例中，基底材料层700可不含有填料。基底材料层700可通过例如涂布工艺或叠层工艺形成。在一些实施例中，可在涂布之后将基底材料层700固化。
参照图1I，减小基底材料层700的高度H700、第一管芯300的导电柱310的高度H310、及第二管芯400的导电柱410的高度H410以形成基底层710及多个导电柱310’、410’。可通过飞切工艺(fly cutting process)或化学机械抛光工艺来移除基底材料层700的部分及导电柱310、410的部分。如图1I所示，基底层710暴露出导电柱310’的顶表面310a’及导电柱410’的顶表面410a’。在一些实施例中，基底层710的第一表面710a、导电柱310’的顶表面310a’、以及导电柱410’的顶表面410a’彼此齐平。由此，基底层710的高度H710、导电柱310的高度H310’、及导电柱410的高度H410’实质上相同。在一些实施例中，导电柱310的高度H310、导电柱410的高度H410可为约30μm。在研磨之后，减小的高度H310’、H410’可为约7μm。
如上所述，包封体510的第一表面510a与第一管芯300的有源表面300a及第二管芯400的有源表面400a齐平，因而基底材料层700可形成在平坦的表面上。此外，第一管芯300的导电柱310及第二管芯400的导电柱410形成在同一水平高度上。因此，当减小导电柱310的高度H310及导电柱410的高度H410时，可在降低由高度变化引起的研磨不足(under-grinding)或过度研磨(over-grinding)的风险的情况下容易地执行研磨工艺以在厚度方向Z上获得期望高度。另外，如上所述，基底材料层700包括粒径小的填料或不含有填料。由此，在研磨之后，基底层710的第一表面710a可为上面仅形成有很少的凹坑或不形成凹坑的平滑表面。
参照图1J，在基底层710、第一管芯300的导电柱310’、及第二管芯400的导电柱410’上形成重布线结构800。之后，在重布线结构800上形成多个导电端子900。在一些实施例中，重布线结构800包括交替堆叠的多个重布线导电图案802与多个介电层804。重布线导电图案802通过嵌置在介电层804中的导通孔806来彼此内连。重布线导电图案802电连接到第一管芯300的导电柱310’以及第二管芯400的导电柱410’以使得重布线结构800电连接到第一管芯300及第二管芯400。在一些实施例中，重布线导电图案802的材料包括铝、钛、铜、镍、钨、及/或其合金。重布线导电图案802可通过例如电镀、沉积、及/或光刻及刻蚀来形成。在一些实施例中，介电层804的材料包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或任何其他适合的聚合物系介电材料。介电层804例如可通过例如旋转涂布(spin-on coating)、化学气相沉积(chemical vapor deposition，CVD)、等离子体增强型化学气相沉积(plasma-enhanced chemical vapor deposition，PECVD)等适合的制作技术来形成。在一些实施例中，重布线结构800中的介电层804的材料不同于基底层710的材料。如上所述，基底层710的第一表面710a可为上面仅形成有很少的凹坑或不形成凹坑的平滑表面。因此，在一些实施例中，重布线结构800形成在平滑表面上，这有助于在确保重布线结构800的可靠性的同时方便降低工艺复杂性。
在一些实施例中，最顶部介电层804暴露出最顶部重布线导电图案802，且所暴露出的重布线导电图案802包括用于安装球的球下金属(under-ball metallurgy，UBM)图案。在球下金属图案上形成导电端子900。在一些实施例中，通过焊剂(图中未示出)将导电端子900贴合到球下金属图案。在一些实施例中，导电端子900是例如焊料球(solder ball)、球栅阵列(ball grid array，BGA)球、或受控塌陷晶粒连接(controlled collapse chipconnection，C4)凸块。在一些实施例中，可通过植球工艺及/或回焊工艺来将导电端子900设置在球下金属图案上。
参照图1K及图1L，将图1J所示的结构上下翻转并放置在剥离载体TP1上。剥离载体TP1可包括框架及由框架所固持的胶带。剥离载体TP1的胶带有助于提供支撑以使得第二载板600可从第一管芯300的后表面300b’、第二管芯400的后表面400b’、以及包封体510的第二表面510b移除。在一些实施例中，可通过紫外激光来照射剥离层610(例如，光热转换释放层)，以将管芯贴合膜620从第二载板600剥除。进一步移除管芯贴合膜620以暴露出第一管芯300的后表面300b’、第二管芯400的后表面400b’、以及包封体510的第二表面510b，如图1L所示。在一些实施例中，可通过剥除工艺、溶剂洗脱工艺、或刻蚀工艺来移除管芯贴合膜620。
参照图1M及图1N，在移除第二载板600之后，将图1L所示的结构从剥离载体TP1分离并再次上下翻转以将所述结构贴合到分割载体TP2。相似于剥离载体TP1，分割载体TP2也可包括框架及由框架固持的胶带。分割载体TP2的胶带有助于提供支撑以可将图1M所示的结构单体化以形成如图1N所示的集成扇出型封装10。在一些实施例中，用于单体化工艺(singulation process)的切割机制涉及利用旋转叶片(rotating blade)或激光束来进行分割。换句话说，分割或单体化工艺例如是激光切割工艺或机械切割工艺。
图2A至图2M示出根据本发明一些替代实施例的制造集成扇出型封装20的方法中的各个阶段的示意性剖视图。图2A至图2M所示各个步骤与图1A至图1N所示各个步骤相似，因此由相同的附图标号来表示相似的元件。参照图2A至图2B，所述工艺与图1A至图1B所示工艺相似，因此在本文中将不再对其予以赘述。应注意，在一些实施例中，粘着层200’是由热固化材料(thermosetting material)所形成。热固性材料是例如管芯贴合膜(DAF)、管芯上膜(film over die，FOD)、导线上膜(film over wire，FOW)、味之素构成膜(AjinomotoBuild-up Film)、聚酰亚胺系层、或环氧系层。换句话说，当施加能量(例如，热量或光)时，粘着层200’可被固化。在一些实施例中，粘着层200’包括粘着性质。在一些实施例中，粘着层200’能够容纳接着形成在上面的管芯的导电柱且能够良好地密封管芯的表面。在一些实施例中，粘着层200’包括与传统的包封材料相比粒径较小的填料或不具有填料。与图1B所示步骤相似，粘着层200’的高度H200’等于或大于第一管芯300的导电柱310的高度H310以及第二管芯400的导电柱410的高度H410。由此，当第一管芯300及第二管芯400被压抵在粘着层200’上时，第一管芯300的导电柱310及第二管芯400的导电柱410可完全浸没在粘着层200’中。
参照图2C，在第一管芯300及第二管芯400被压抵在粘着层200’上之后，将粘着层200’固化。如上所述，粘着层200’包含热固化材料。因此，在照射具有某些波长的光或施加热量时，粘着层200’可被固化/硬化以包封第一管芯300的导电柱310及第二管芯400的导电柱410。换句话说，导电柱310、410两者被相同的材料包绕。
参照图2D至图2G，所述工艺与图1C至图1F所示工艺相似，因此在本文中将不再对其予以赘述。参照图2G至图2H，减小粘着层200’的高度H200’、第一管芯300的导电柱310的高度H310、及第二管芯400的导电柱410的高度H410以形成粘着层210及多个导电柱310’、410’。可通过飞切工艺或化学机械抛光工艺来移除粘着层200’的部分及导电柱310、410的部分。如图2H所示，粘着层210暴露出导电柱310’的顶表面310a’及导电柱410’的顶表面410a’。在一些实施例中，粘着层210的第一表面210a贴合到包封体510的第一表面510a、第一管芯300的有源表面300a、及第二管芯400的有源表面400a。另一方面，粘着层210的第二表面210b、导电柱310’的顶表面310a’、以及导电柱410’的顶表面410a’彼此齐平。由此，粘着层210的高度H210、导电柱310的高度H310’、及导电柱410的高度H410’实质上相同。在一些实施例中，导电柱310的高度H310及导电柱410的高度H410可为约30μm。在研磨之后，减小的高度H310’、H410’可为约7μm。
如上所述，第一管芯300的导电柱310及第二管芯400的导电柱410形成在同一水平高度上。因此，当减小导电柱310的高度H310及导电柱410的高度H410时，可在降低由高度变化引起的研磨不足或过度研磨的风险的情况下容易地执行研磨工艺以在厚度方向Z上获得期望高度。如上所述，粘着层200’包括粒径小的填料或不含有填料。由此，在研磨之后，粘着层210的第二表面210b可为上面仅形成有很少的凹坑或不形成凹坑的平滑表面。
参照图2I，在粘着层210、第一管芯300的导电柱310’、及第二管芯400的导电柱410’上形成重布线结构800。之后，在重布线结构800上形成多个导电端子900。图2I所示的重布线结构800及导电端子900与图1J所示的重布线结构800及导电端子900相似，因此在本文中将不再对其予以赘述。在一些实施例中，重布线结构800中的介电层804的材料不同于粘着层210的材料。如上所述，粘着层210的第二表面210b可为上面仅形成有很少的凹坑或不形成凹坑的平滑表面。因此，在一些实施例中，重布线结构800形成在平滑表面上，这有助于在确保重布线结构800的可靠性的同时降低工艺复杂性。
参照图2J至图2M，所述工艺与图1K至图1N所示工艺相似以获得集成扇出型封装20，因此在本文中将不再对其予以赘述。
根据本发明的一些实施例，一种集成扇出型封装包括第一管芯、第二管芯、包封体、及重布线结构。第一管芯及第二管芯分别具有有源表面、与所述有源表面相对的后表面、及形成在所述有源表面上的多个导电柱。所述第一管芯与所述第二管芯是不同类型的管芯。所述第一管芯的所述有源表面与所述第二管芯的所述有源表面齐平。所述第一管芯的所述后表面与所述第二管芯的所述后表面齐平。所述第一管芯的所述导电柱的顶表面与所述第二管芯的所述导电柱的顶表面齐平。所述第一管芯的所述导电柱与所述第二管芯的所述导电柱被由相同材料所形成的层包绕。包封体包封所述第一管芯的侧壁及所述第二管芯的侧壁。所述包封体具有第一表面及与所述第一表面相对的第二表面。所述第一表面与所述第一管芯的所述有源表面及所述第二管芯的所述有源表面齐平。所述第二表面与所述第一管芯的所述后表面及所述第二管芯的所述后表面齐平。重布线结构位于所述第一管芯、所述第二管芯、及所述包封体上。所述重布线结构与所述第一管芯及所述第二管芯电连接。
在一些实施例中，所述集成扇出型封装进一步包括位于所述重布线结构上的多个导电端子。
在一些实施例中，所述相同材料包括弹性聚合物材料(elastic polymericmaterial)或热固性材料(thermosetting material)。
在一些实施例中，由所述相同材料所形成的所述层接触所述包封体的所述第一表面且接触所述第一管芯的所述有源表面及所述第二管芯的所述有源表面。
在一些实施例中，所述第一管芯的所述多个导电柱的高度与所述第二管芯的所述多个导电柱的高度相同。
根据本发明的一些实施例，一种集成扇出型封装的制造方法至少包括以下步骤。提供载板，所述载板上形成有粘着层。在所述粘着层上提供第一管芯及第二管芯。所述第一管芯的高度不同于所述第二管芯的高度。所述第一管芯具有第一导电柱且所述第二管芯具有第二导电柱。将所述第一管芯及所述第二管芯压抵(press against)在所述粘着层上，以使所述第一管芯的有源表面及所述第二管芯的有源表面直接接触所述粘着层且使所述第一导电柱及所述第二导电柱浸没(submerge)在所述粘着层中。将所述粘着层固化。形成包封体，以包封所述第一管芯及所述第二管芯。从所述粘着层移除所述载板。减小所述粘着层的高度以及所述第一导电柱的高度及所述第二导电柱的高度，使得所述第一导电柱及所述第二导电柱从所述粘着层暴露出。在所述粘着层以及所述第一导电柱及所述第二导电柱上形成重布线结构，使得所述重布线结构与所述第一导电柱及所述第二导电柱电连接。
在一些实施例中，所述集成扇出型封装的制造方法进一步包括执行单体化工艺(singulation process)以将所述集成扇出型封装单体化。
在一些实施例中，所述集成扇出型封装的制造方法进一步包括在所述重布线结构上形成多个导电端子。
在一些实施例中，所述粘着层是由热固性材料所形成，且所述粘着层是在形成所述包封体之前固化。
在一些实施例中，所述粘着层的高度大于或等于所述第一管芯的所述第一导电柱的高度及所述第二管芯的所述第二导电柱的高度。
在一些实施例中，减小所述粘着层的高度以及所述多个第一及第二导电柱的高度包括执行飞切工艺(fly cutting process)或化学机械抛光工艺(chemical mechanicalpolishing process)。
在一些实施例中，形成所述包封体至少包括以下步骤。在所述粘着层上形成包封材料，以包封所述第一管芯及所述第二管芯。所述包封材料的高度大于所述第一管芯的所述高度及所述第二管芯的所述高度。减小所述包封材料的所述高度、所述第一管芯的所述高度、及所述第二管芯的所述高度以形成所述包封体。所述包封体的表面与所述第一管芯的所述后表面及所述第二管芯的所述后表面齐平。
根据本发明的一些替代实施例，一种集成扇出型封装的制造方法至少包括以下步骤。提供第一载板，所述第一载板上形成有粘着层。将第一管芯及第二管芯压抵在所述粘着层上。第一管芯及第二管芯分别具有有源表面、与所述有源表面相对的后表面、及形成在所述有源表面上的多个导电柱。所述第一管芯的高度不同于所述第二管芯的高度。所述第一管芯的所述有源表面及所述第二管芯的所述有源表面被压至直接接触所述粘着层。所述导电柱被压至浸没在所述粘着层中。形成包封体，以包封所述第一管芯及所述第二管芯。将所述第一管芯的所述后表面及所述第二管芯的所述后表面贴合到第二载板。移除所述第一载板。从所述第一管芯、所述第二管芯及所述包封体移除所述粘着层。在所述第一管芯的所述有源表面及所述第二管芯的所述有源表面上形成基底材料层，以包封所述导电柱。减小所述基底材料层的高度及所述导电柱的高度。在所述导电柱上形成重布线结构，使得所述重布线结构与所述导电柱电连接。从所述第一管芯的所述后表面及所述第二管芯的所述后表面移除所述第二载板。
在一些实施例中，所述集成扇出型封装的制造方法进一步包括单体化工艺，以将所述集成扇出型封装单体化。
在一些实施例中，所述集成扇出型封装的制造方法进一步包括在所述重布线结构上形成多个导电端子。
在一些实施例中，所述粘着层是由弹性聚合物材料所形成。
在一些实施例中，所述粘着层的高度大于或等于所述第一管芯的所述多个导电柱的高度以及所述第二管芯的所述多个导电柱的高度。
在一些实施例中，移除所述粘着层包括应用剥除工艺(peel off process)、溶剂洗脱工艺(solvent wash off process)、或刻蚀工艺。
在一些实施例中，减小所述基底材料层的高度及所述多个导电柱的高度包括执行飞切工艺或化学机械抛光工艺。
在一些实施例中，形成所述包封体至少包括以下步骤。在所述粘着层上形成包封材料，以包封所述第一管芯及所述第二管芯。所述包封材料的高度大于所述第一管芯的所述高度及所述第二管芯的所述高度。减小所述包封材料的所述高度、所述第一管芯的所述高度、及所述第二管芯的所述高度以形成所述包封体。所述包封体的表面与所述第一管芯的所述后表面及所述第二管芯的所述后表面齐平。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知，他们可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (1)

1.一种集成扇出型封装，其特征在于，包括：
第一管芯及第二管芯，分别具有有源表面、与所述有源表面相对的后表面、及形成在所述有源表面上的多个导电柱，其中所述第一管芯与所述第二管芯是不同类型的管芯，所述第一管芯的所述有源表面与所述第二管芯的所述有源表面齐平，所述第一管芯的所述后表面与所述第二管芯的所述后表面齐平，所述第一管芯的所述多个导电柱的顶表面与所述第二管芯的所述多个导电柱的顶表面齐平，且所述第一管芯的所述多个导电柱与所述第二管芯的所述多个导电柱被由相同材料所形成的层包绕；
包封体，包封所述第一管芯的侧壁及所述第二管芯的侧壁，所述包封体具有第一表面及与所述第一表面相对的第二表面，所述第一表面与所述第一管芯的所述有源表面及所述第二管芯的所述有源表面齐平，且所述第二表面与所述第一管芯的所述后表面及所述第二管芯的所述后表面齐平；以及
重布线结构，位于所述第一管芯、所述第二管芯、及所述包封体上，其中所述重布线结构与所述第一管芯及所述第二管芯电连接。
CN201711131655.2A 2017-09-25 2017-11-15 集成扇出型封装 Pending CN109560076A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/715,132 US10276537B2 (en) 2017-09-25 2017-09-25 Integrated fan-out package and manufacturing method thereof
US15/715,132 2017-09-25

Publications (1)

Publication Number Publication Date
CN109560076A true CN109560076A (zh) 2019-04-02

Family

ID=65808400

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711131655.2A Pending CN109560076A (zh) 2017-09-25 2017-11-15 集成扇出型封装

Country Status (3)

Country Link
US (2) US10276537B2 (zh)
CN (1) CN109560076A (zh)
TW (1) TW201916266A (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101922884B1 (ko) * 2017-10-26 2018-11-28 삼성전기 주식회사 팬-아웃 반도체 패키지
US10770394B2 (en) * 2017-12-07 2020-09-08 Sj Semiconductor (Jiangyin) Corporation Fan-out semiconductor packaging structure with antenna module and method making the same
KR20200113069A (ko) * 2019-03-20 2020-10-06 삼성전자주식회사 반도체 소자 제조 방법
WO2021013097A1 (en) * 2019-07-25 2021-01-28 Nantong Tongfu Microelectronics Co., Ltd. Packaging structure and formation method thereof
US11239217B2 (en) * 2020-03-30 2022-02-01 Nanya Technology Corporation Semiconductor package including a first sub-package stacked atop a second sub-package
US11450615B2 (en) 2020-06-12 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
US20230057113A1 (en) * 2021-08-19 2023-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, package structure and method of fabricating the same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6172077A (ja) * 1984-09-14 1986-04-14 Shin Etsu Chem Co Ltd 接着促進剤
US5486265A (en) * 1995-02-06 1996-01-23 Advanced Micro Devices, Inc. Chemical-mechanical polishing of thin materials using a pulse polishing technique
US7921551B2 (en) * 2005-03-24 2011-04-12 Panasonic Corporation Electronic component mounting method
US8008125B2 (en) * 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) * 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US20130307153A1 (en) 2012-05-18 2013-11-21 International Business Machines Corporation Interconnect with titanium-oxide diffusion barrier
US8597979B1 (en) * 2013-01-23 2013-12-03 Lajos Burgyan Panel-level package fabrication of 3D active semiconductor and passive circuit components
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US10312220B2 (en) * 2016-01-27 2019-06-04 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
US20170243845A1 (en) * 2016-02-19 2017-08-24 Qualcomm Incorporated Fan-out wafer-level packages with improved topology
US10700011B2 (en) * 2016-12-07 2020-06-30 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an integrated SIP module with embedded inductor or package

Also Published As

Publication number Publication date
US20190252339A1 (en) 2019-08-15
TW201916266A (zh) 2019-04-16
US10867953B2 (en) 2020-12-15
US20190096840A1 (en) 2019-03-28
US10276537B2 (en) 2019-04-30

Similar Documents

Publication Publication Date Title
CN109560076A (zh) 集成扇出型封装
US10090284B2 (en) Semiconductor device and method of manufacture
TWI793960B (zh) 封裝結構及其製造方法
US20220320029A1 (en) Dummy Structure of Stacked and Bonded Semiconductor Device
CN107068669B (zh) 半导体装置封装以及半导体封装及其制造方法
CN106356340B (zh) 半导体器件及其制造方法
US9716080B1 (en) Thin fan-out multi-chip stacked package structure and manufacturing method thereof
KR101746269B1 (ko) 반도체 디바이스 및 그 제조방법
CN110299351A (zh) 半导体封装件及其形成方法
CN109585404A (zh) 半导体封装及其形成方法
CN109860136A (zh) 集成扇出封装件及其形成方法
US20150348920A1 (en) Microelectronic packages having radiofrequency stand-off layers and methods for the production thereof
CN110060935A (zh) 半导体器件及其制造方法
CN109216296A (zh) 半导体封装件和方法
CN109786268A (zh) 半导体封装件中的金属化图案及其形成方法
CN108630676A (zh) 半导体封装件及其形成方法
CN107818974A (zh) 具有伪连接件的半导体封装件及其形成方法
CN107689333A (zh) 半导体封装件及其形成方法
CN108987380A (zh) 半导体封装件中的导电通孔及其形成方法
TW201916297A (zh) 積體扇出型封裝
CN106057760A (zh) 半导体器件及其形成方法
KR20150104467A (ko) 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
CN109727951A (zh) 封装结构及其制造方法
KR101831036B1 (ko) 반도체 소자 및 그 제조 방법
CN104037098B (zh) 封装结构及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20190402

WD01 Invention patent application deemed withdrawn after publication