TW201916266A - 積體扇出型封裝 - Google Patents
積體扇出型封裝 Download PDFInfo
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- TW201916266A TW201916266A TW106139225A TW106139225A TW201916266A TW 201916266 A TW201916266 A TW 201916266A TW 106139225 A TW106139225 A TW 106139225A TW 106139225 A TW106139225 A TW 106139225A TW 201916266 A TW201916266 A TW 201916266A
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Abstract
一種積體扇出型封裝包括第一晶粒及第二晶粒、包封體、及重佈線結構。第一晶粒及第二晶粒分別具有主動表面、與主動表面相對的後表面、及位於主動表面上的導電柱。第一與第二晶粒是不同類型的晶粒。第一晶粒的主動表面及後表面分別與第二晶粒的主動表面及後表面齊平。第一晶粒的導電柱的頂表面與第二晶粒的導電柱的頂表面齊平。第一晶粒的導電柱與第二晶粒的導電柱被相同的材料包繞。包封體包封第一晶粒的側壁及第二晶粒的側壁。包封體的第一表面與主動表面齊平且第二表面與後表面齊平。重佈線結構設置在第一晶粒、第二晶粒、及包封體上。
Description
本發明是有關於一種積體扇出型封裝,且特別是有關於一種具有不同類型晶粒的積體扇出型封裝。
近來,由於各種電子元件(例如,電晶體、二極體、電阻器、電容器等)的集成密度的持續提高,半導體行業已經歷快速增長。在很大程度上,積體密度的此種提高來自於最小特徵大小(minimum feature size)的相繼減小,此使得更多元件能夠集成到給定區域中。當前,積體扇出型封裝因其緊湊性而正變得日漸流行。在積體扇出型封裝中,模塑化合物的平坦化及重佈線路結構的形成在封裝製程期間至關重要。
一種積體扇出型封裝包括第一晶粒及第二晶粒、包封體、及重佈線結構。第一晶粒及第二晶粒分別具有主動表面、與主動表面相對的後表面、及位於主動表面上的導電柱。第一晶粒與第二晶粒是不同類型的晶粒。第一晶粒的主動表面及後表面分別與第二晶粒的主動表面及後表面齊平。第一晶粒的導電柱的頂表面與第二晶粒的導電柱的頂表面齊平。第一晶粒的導電柱與第二晶粒的導電柱被相同的材料包繞。包封體包封第一晶粒的側壁及第二晶粒的側壁。包封體的第一表面與主動表面齊平。包封體的第二表面與後表面齊平。重佈線結構設置在第一晶粒、第二晶粒、及包封體上。
以下公開內容提供用於實作所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及配置形式的具體實例以簡化本公開內容。當然,這些僅為實例且不旨在進行限制。舉例來說,以下說明中將第一特徵形成在第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例,且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外,本公開內容可能在各種例子中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的,而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外,為易於說明,本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向(旋轉90度或其他取向),且本文中所用的空間相對性用語可同樣相應地進行解釋。
也可包括其他特徵及製程。舉例來說,可包括測試結構,以幫助對三維(three dimensional;3D)封裝或三維積體電路(three dimensional integrated circuit;3DIC)裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基板上形成的測試接墊(test pad),以允許對三維封裝或三維積體電路進行測試、對探針及/或探針卡(probe card)進行使用等。可對中間結構以及最終結構執行驗證測試。另外,可將本文中所公開的結構及方法與包括對已知良好晶粒進行中間驗證的測試方法結合使用,以提高良率並降低成本。
圖1A至圖1N繪示根據本發明一些實施例的製造積體扇出型封裝10的方法中的各個階段的示意性剖面圖。參照圖1A,提供第一載板100。在第一載板100上依序形成剝離層110及黏著層200。在一些實施例中,第一載板100是玻璃基板。然而,其他材料也可適於作為第一載板100的材料,只要所述材料能夠在承載在其上面形成的封裝結構的同時耐受後續製程即可。在一些實施例中,剝離層110是形成在玻璃基板上的光熱轉換(light-to-heat conversion;LTHC)釋放層。光熱轉換釋放層可通過利用例如紫外(ultra-violet;UV)光進行照射來實現剝離。在一些實施例中,黏著層200包含彈性聚合物材料(elastic polymeric material)或包括由彈性聚合物材料所形成的層。彈性聚合物材料例如是酚醛樹脂(phenol resin)、環氧樹脂(epoxy resin)、或丙烯酸聚合物(acrylic polymer)。在一些實施例中,可在彈性聚合物材料中添加無機填料,例如二氧化矽(SiO2
)。在一些實施例中,黏著層200可用作熱釋放膜或紫外釋放膜。熱釋放膜可在所述膜被加熱到特定溫度時剝除,且紫外釋放膜可在被紫外光曝光之後被剝除。在一些實施例中,黏著層200包含黏著性質。在一些實施例中,黏著層200能夠容納接著在上面形成的晶粒的導電柱,且能夠良好地密封晶粒的表面。
參照圖1B,提供多個第一晶粒300及多個第二晶粒400。每一個第一晶粒300具有主動表面300a、與主動表面300a相對的後表面300b、以及形成在主動表面300a上的多個導電柱310。每一個第二晶粒400具有主動表面400a、與主動表面400a相對的後表面400b、以及形成在主動表面400a上的多個導電柱410。第一晶粒300的導電柱310及第二晶粒400的導電柱410可包括例如銅柱。在一些實施例中,第一晶粒300可包括相同類型的晶片且可選自:特殊應用積體電路(application-specific integrated circuit;ASIC)晶片、類比晶片(analog chip)、感測器晶片、無線射頻晶片(wireless and radio frequency chip)、電壓調節器晶片或記憶體晶片。在一些實施例中,第二晶粒400可包括相同類型的晶片且可選自:特殊應用積體電路(ASIC)晶片、類比晶片、感測器晶片、無線射頻晶片、電壓調節器晶片或記憶體晶片。在某些實施例中,第一晶粒300與第二晶粒400是不同類型的晶粒。舉例來說,第一晶粒300與第二晶粒400可囊括不同類型的晶片或不同的電子構件或元件。根據應用而定,第一晶粒300與第二晶粒400可執行不同的功能。在一些實施例中,第一晶粒300可為系統晶片(system on chip;SoC)晶粒且第二晶粒400可為高頻寬記憶體(high bandwidth memory;HBM)晶粒。然而,本發明實施例並非僅限於此,且第一晶粒300與第二晶粒400可基於產品需要而為其他類型的晶粒。由於第一晶粒300與第二晶粒400是不同類型的晶粒,因此第一晶粒300的大小及高度與第二晶粒400的大小及高度將不同。舉例來說,如圖1B所示,第一晶粒300的高度(由高度H300
與高度H310
之和表示)不同於第二晶粒400的高度(由高度H400
與高度H410
之和表示)。應注意,在本公開內容通篇中,元件的高度是指元件的主動表面與後表面之間在厚度方向Z上的距離。在一些實施例中,高度H400
不同於高度H300
。此外,第一晶粒300的導電柱310的高度H310
也可不同於第二晶粒400的導電柱410的高度H410
。應注意,由於導電柱310的高度H310
及導電柱410的高度H410
比高度H300
及高度H400
小很多而可忽略不計,因此在本發明中出於簡明的目的,將高度H300
稱為第一晶粒300的高度且將高度H400
稱為第二晶粒400的高度。
在黏著層200上將第一晶粒300及第二晶粒400放置成使得主動表面300a、400a面對黏著層200。將第一晶粒300及第二晶粒400壓抵在黏著層200上。應注意,在壓抵之前,第一晶粒300的主動表面300a及第二晶粒400的主動表面400a被暴露出。換句話說,第一晶粒300及第二晶粒400是在其主動表面300a、400a上未形成有介電層(例如,聚苯并噁唑(polybenzooxazole;PBO)層)的裸露晶粒(bare die)。由此,當第一晶粒300及第二晶粒400被壓抵在黏著層200上時,第一晶粒300的主動表面300a及第二晶粒400的主動表面400a直接接觸黏著層的表面200a。在一些實施例中,黏著層200的高度H200
至少等於或大於第一晶粒300的導電柱310的高度H310
以及第二晶粒400的導電柱410的高度H410
。由此,當第一晶粒300及第二晶粒400被壓抵在黏著層200上時,第一晶粒300的導電柱310及第二晶粒400的導電柱410可完全浸沒(submerge)在黏著層200中。換句話說,導電柱310、410被黏著層200包封或良好地保護。
如圖1B所示,由於第一晶粒300與第二晶粒400的高度差,因此在壓抵製程之後,第二晶粒400的後表面400b位於比第一晶粒300的後表面300b高的水平高度處。應注意,在圖1B中分別繪示兩個第一晶粒300及兩個第二晶粒400。然而,在一些替代實施例中,第一晶粒300及第二晶粒400的數目可基於需要而變化。
參照圖1C,在黏著層200上形成包封材料500。包封材料500的第一表面500a接觸黏著層200。在一些實施例中,包封材料500的高度H500大於第一晶粒300的高度H300以及第二晶粒400的高度H400。由此,包封材料500完全包封第一晶粒300及第二晶粒400。換句話說,包封材料500的第二表面500b位於比第一晶粒300的後表面300b及第二晶粒400的後表面400b兩者高的水平高度處。第一晶粒300及第二晶粒400不被顯露出且受到包封材料500的良好保護。在一些實施例中,包封材料500可為由模塑製程(molding process)形成的模塑化合物(molding compound)。然而,在一些替代實施例中,包封材料500可由絕緣材料(例如,環氧樹脂或其他合適的樹脂)所形成。同時,包封材料500可通過與所選擇的絕緣材料對應的其他製程形成。
參照圖1D,執行薄化製程以減小包封材料500的高度H500
、第一晶粒300的高度H300
以及第二晶粒400的高度H400
。在一些實施例中,移除包封材料500的一部分以形成包封體510且暴露出每一個第一晶粒300及每一個第二晶粒400。在一些實施例中,薄化製程包括機械研磨製程、化學機械拋光(chemical mechanical polishing;CMP)製程、或其組合。在一些實施例中,通過研磨來減小包封材料500的高度H500
、第一晶粒300的高度H300
、以及第二晶粒的高度H400
。在一些實施例中,如上所述,第一晶粒300的高度H300
不同於第二晶粒400的高度H400
。當局部地移除包封材料500以暴露出後表面300b、400b中的一者時,後表面300b、400b中的另一者仍被包封材料500覆蓋。因此,進一步移除後表面300b、400b中的至少一者直到暴露出另一個後表面300b、400b為止。在一些替代實施例中,在後表面300b、400b兩者均被暴露出之後,可對第一晶粒300、第二晶粒400、及包封材料500繼續進行研磨製程以進一步減小後續所形成的封裝的總體厚度。
如圖1D所示,包封體510的第一表面510a與第一晶粒300的主動表面300a及第二晶粒400的主動表面400a齊平。包封體510的第二表面510b與第一晶粒300的後表面300b及第二晶粒400的後表面400b齊平。第一晶粒300的側壁SW300
及第二晶粒400的側壁SW400
被包封體510包封。在一些實施例中,包封體510的高度H510
實質上等於經薄化的第一晶粒300的高度H300’
以及經薄化的第二晶粒400的高度H400’
。
參照圖1E,提供上面依序地形成有剝離層610及晶粒貼合膜(die attach film;DAF)620的第二載板600。在一些實施例中,第二載板600可類似於第一載板100且剝離層610可類似於剝離層110,因此在本文中將不再對其予以贅述。第一晶粒300的後表面300b’及第二晶粒400的後表面400b’貼合到晶粒貼合膜620。
參照圖1E至圖1G,將第一載板100及剝離層110從黏著層200分離且接著移除第一載板100及剝離層110。在一些實施例中,可通過紫外雷射(UV laser)來照射剝離層110(例如,光熱轉換釋放層),以使得黏著層200從第一載板100剝除。在將黏著層200從第一載板100分離之後,將所述結構上下翻轉以獲得如圖1F所示的結構。
參照圖1G,從第一晶粒300、第二晶粒400、及包封體510移除黏著層200,以使得包封體510的第一表面510a、第一晶粒300的主動表面300a、及第二晶粒400的主動表面400a暴露出。在一些實施例中,可通過剝除製程(peel off process)、溶劑洗脫製程(solvent wash off process)、或蝕刻製程來移除黏著層200。
參照圖1H,在包封體510的第一表面510a、第一晶粒300的主動表面300a、及第二晶粒400的主動表面400a上形成基底材料層700。基底材料層700具有第一表面700a及與第一表面700a相對的第二表面700b。在一些實施例中,基底材料層700直接形成在包封體510上以覆蓋第一晶粒300的導電柱310及第二晶粒400的導電柱410,並使得基底材料層700的第二表面700b接觸包封體510的第一表面510a。基底材料層700的高度H700
大於第一晶粒300的導電柱310的高度H310
及第二晶粒400的導電柱410的高度H410
。換句話說,導電柱310、410兩者均被基底材料層700包封。也就是說,導電柱310、410兩者被相同的材料包繞。在一些實施例中,基底材料層700由介電材料所形成。介電材料包括例如聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、苯並環丁烯(benzocyclobutene;BCB)、聚苯并噁唑(PBO)或任何其他適合的聚合物系介電材料。在一些實施例中,基底材料層700可包含粒徑比傳統的模塑化合物或包封體的填料小的填料。在一些替代實施例中,基底材料層700可不含有填料。基底材料層700可通過例如塗布製程或疊層製程形成。在一些實施例中,可在塗布之後將基底材料層700固化。
參照圖1I,減小基底材料層700的高度H700
、第一晶粒300的導電柱310的高度H310
、及第二晶粒400的導電柱410的高度H410
以形成基底層710及多個導電柱310’、410’。可通過飛切製程(fly cutting process)或化學機械拋光製程來移除基底材料層700的部分及導電柱310、410的部分。如圖1I所示,基底層710暴露出導電柱310’的頂表面310a’及導電柱410’的頂表面410a’。在一些實施例中,基底層710的第一表面710a、導電柱310’的頂表面310a’、以及導電柱410’的頂表面410a’彼此齊平。由此,基底層710的高度H710
、導電柱310的高度H310’
、及導電柱410的高度H410’
實質上相同。在一些實施例中,導電柱310的高度H310
、導電柱410的高度H410
可為約30μm。在研磨之後,減小的高度H310’
、H410’
可為約7μm。
如上所述,包封體510的第一表面510a與第一晶粒300的主動表面300a及第二晶粒400的主動表面400a齊平,因而基底材料層700可形成在平坦的表面上。此外,第一晶粒300的導電柱310及第二晶粒400的導電柱410形成在同一水平高度上。因此,當減小導電柱310的高度H310
及導電柱410的高度H410
時,可在降低由高度變化引起的研磨不足(under-grinding)或過度研磨(over-grinding)的風險的情況下容易地執行研磨製程以在厚度方向Z上獲得期望高度。另外,如上所述,基底材料層700包括粒徑小的填料或不含有填料。由此,在研磨之後,基底層710的第一表面710a可為上面僅形成有很少的凹坑或不形成凹坑的平滑表面。
參照圖1J,在基底層710、第一晶粒300的導電柱310’、及第二晶粒400的導電柱410’上形成重佈線結構800。之後,在重佈線結構800上形成多個導電端子900。在一些實施例中,重佈線結構800包括交替堆疊的多個重佈線導電圖案802與多個介電層804。重佈線導電圖案802通過嵌置在介電層804中的導通孔806來彼此內連。重佈線導電圖案802電性連接到第一晶粒300的導電柱310’以及第二晶粒400的導電柱410’以使得重佈線結構800電性連接到第一晶粒300及第二晶粒400。在一些實施例中,重佈線導電圖案802的材料包括鋁、鈦、銅、鎳、鎢、及/或其合金。重佈線導電圖案802可通過例如電鍍、沉積、及/或微影及蝕刻來形成。在一些實施例中,介電層804的材料包括聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、苯並環丁烯(BCB)、聚苯并噁唑(PBO)或任何其他適合的聚合物系介電材料。介電層804例如可通過例如旋轉塗布(spin-on coating)、化學氣相沉積(chemical vapor deposition;CVD)、電漿增強型化學氣相沉積(plasma-enhanced chemical vapor deposition;PECVD)等適合的製作技術來形成。在一些實施例中,重佈線結構800中的介電層804的材料不同於基底層710的材料。如上所述,基底層710的第一表面710a可為上面僅形成有很少的凹坑或不形成凹坑的平滑表面。因此,在一些實施例中,重佈線結構800形成在平滑表面上,這有助於在確保重佈線結構800的可靠性的同時方便降低製程複雜性。
在一些實施例中,最頂部介電層804暴露出最頂部重佈線導電圖案802,且所暴露出的重佈線導電圖案802包括用於安裝球的球下金屬(under-ball metallurgy;UBM)圖案。在球下金屬圖案上形成導電端子900。在一些實施例中,通過焊劑(圖中未繪示)將導電端子900貼合到球下金屬圖案。在一些實施例中,導電端子900是例如焊料球(solder ball)、球柵陣列(ball grid array;BGA)球、或受控塌陷晶粒連接(controlled collapse chip connection;C4)凸塊。在一些實施例中,可通過植球製程及/或回焊製程來將導電端子900設置在球下金屬圖案上。
參照圖1K及圖1L,將圖1J所示的結構上下翻轉並放置在剝離載體TP1上。剝離載體TP1可包括框架及由框架所固持的膠帶。剝離載體TP1的膠帶有助於提供支撐以使得第二載板600可從第一晶粒300的後表面300b’、第二晶粒400的後表面400b’、以及包封體510的第二表面510b移除。在一些實施例中,可通過紫外雷射來照射剝離層610(例如,光熱轉換釋放層),以將晶粒貼合膜620從第二載板600剝除。進一步移除晶粒貼合膜620以暴露出第一晶粒300的後表面300b’、第二晶粒400的後表面400b’、以及包封體510的第二表面510b,如圖1L所示。在一些實施例中,可通過剝除製程、溶劑洗脫製程、或蝕刻製程來移除晶粒貼合膜620。
參照圖1M及圖1N,在移除第二載板600之後,將圖1L所示的結構從剝離載體TP1分離並再次上下翻轉以將所述結構貼合到分割載體TP2。類似於剝離載體TP1,分割載體TP2也可包括框架及由框架固持的膠帶。分割載體TP2的膠帶有助於提供支撐以可將圖1M所示的結構單體化以形成如圖1N所示的積體扇出型封裝10。在一些實施例中,用於單體化製程(singulation process)的切割機制涉及利用旋轉葉片(rotating blade)或雷射光束來進行分割。換句話說,分割或單體化製程例如是雷射切割製程或機械切割製程。
圖2A至圖2M繪示根據本發明一些替代實施例的製造積體扇出型封裝20的方法中的各個階段的示意性剖面圖。圖2A至圖2M所示各個步驟與圖1A至圖1N所示各個步驟相似,因此由相同的標號來表示相似的元件。參照圖2A至圖2B,所述製程與圖1A至圖1B所示製程相似,因此在本文中將不再對其予以贅述。應注意,在一些實施例中,黏著層200’是由熱固化材料(thermosetting material)所形成。熱固性材料是例如晶粒貼合膜(DAF)、晶粒上膜(film over die;FOD)、導線上膜(film over wire;FOW)、味之素構成膜(Ajinomoto Build-up Film)、聚醯亞胺系層、或環氧系層。換句話說,當施加能量(例如,熱量或光)時,黏著層200’可被固化。在一些實施例中,黏著層200’包括黏著性質。在一些實施例中,黏著層200’能夠容納接著形成在上面的晶粒的導電柱且能夠良好地密封晶粒的表面。在一些實施例中,黏著層200’包括與傳統的包封材料相比粒徑較小的填料或不具有填料。與圖1B所示步驟相似,黏著層200’的高度H200’
等於或大於第一晶粒300的導電柱310的高度H310
以及第二晶粒400的導電柱410的高度H410
。由此,當第一晶粒300及第二晶粒400被壓抵在黏著層200’上時,第一晶粒300的導電柱310及第二晶粒400的導電柱410可完全浸沒在黏著層200’中。
參照圖2C,在第一晶粒300及第二晶粒400被壓抵在黏著層200’上之後,將黏著層200’固化。如上所述,黏著層200’包含熱固化材料。因此,在照射具有某些波長的光或施加熱量時,黏著層200’可被固化/硬化以包封第一晶粒300的導電柱310及第二晶粒400的導電柱410。換句話說,導電柱310、410兩者被相同的材料包繞。
參照圖2D至圖2G,所述製程與圖1C至圖1F所示製程相似,因此在本文中將不再對其予以贅述。參照圖2G至圖2H,減小黏著層200’的高度H200’
、第一晶粒300的導電柱310的高度H310
、及第二晶粒400的導電柱410的高度H410
以形成黏著層210及多個導電柱310’、410’。可通過飛切製程或化學機械拋光製程來移除黏著層200’的部分及導電柱310、410的部分。如圖2H所示,黏著層210暴露出導電柱310’的頂表面310a’及導電柱410’的頂表面410a’。在一些實施例中,黏著層210的第一表面210a貼合到包封體510的第一表面510a、第一晶粒300的主動表面300a、及第二晶粒400的主動表面400a。另一方面,黏著層210的第二表面210b、導電柱310’的頂表面310a’、以及導電柱410’的頂表面410a’彼此齊平。由此,黏著層210的高度H210
、導電柱310的高度H310’
、及導電柱410的高度H410’
實質上相同。在一些實施例中,導電柱310的高度H310
及導電柱410的高度H410
可為約30μm。在研磨之後,減小的高度H310’
、H410’
可為約7μm。
如上所述,第一晶粒300的導電柱310及第二晶粒400的導電柱410形成在同一水平高度上。因此,當減小導電柱310的高度H310
及導電柱410的高度H410
時,可在降低由高度變化引起的研磨不足或過度研磨的風險的情況下容易地執行研磨製程以在厚度方向Z上獲得期望高度。如上所述,黏著層200’包括粒徑小的填料或不含有填料。由此,在研磨之後,黏著層210的第二表面210b可為上面僅形成有很少的凹坑或不形成凹坑的平滑表面。
參照圖2I,在黏著層210、第一晶粒300的導電柱310’、及第二晶粒400的導電柱410’上形成重佈線結構800。之後,在重佈線結構800上形成多個導電端子900。圖2I所示的重佈線結構800及導電端子900與圖1J所示的重佈線結構800及導電端子900相似,因此在本文中將不再對其予以贅述。在一些實施例中,重佈線結構800中的介電層804的材料不同於黏著層210的材料。如上所述,黏著層210的第二表面210b可為上面僅形成有很少的凹坑或不形成凹坑的平滑表面。因此,在一些實施例中,重佈線結構800形成在平滑表面上,這有助於在確保重佈線結構800的可靠性的同時降低製程複雜性。
參照圖2J至圖2M,所述製程與圖1K至圖1N所示製程相似以獲得積體扇出型封裝20,因此在本文中將不再對其予以贅述。
根據本發明的一些實施例,一種積體扇出型封裝包括第一晶粒、第二晶粒、包封體、及重佈線結構。第一晶粒及第二晶粒分別具有主動表面、與所述主動表面相對的後表面、及形成在所述主動表面上的多個導電柱。所述第一晶粒與所述第二晶粒是不同類型的晶粒。所述第一晶粒的所述主動表面與所述第二晶粒的所述主動表面齊平。所述第一晶粒的所述後表面與所述第二晶粒的所述後表面齊平。所述第一晶粒的所述導電柱的頂表面與所述第二晶粒的所述導電柱的頂表面齊平。所述第一晶粒的所述導電柱與所述第二晶粒的所述導電柱被由相同材料所形成的層包繞。包封體包封所述第一晶粒的側壁及所述第二晶粒的側壁。所述包封體具有第一表面及與所述第一表面相對的第二表面。所述第一表面與所述第一晶粒的所述主動表面及所述第二晶粒的所述主動表面齊平。所述第二表面與所述第一晶粒的所述後表面及所述第二晶粒的所述後表面齊平。重佈線結構位於所述第一晶粒、所述第二晶粒、及所述包封體上。所述重佈線結構與所述第一晶粒及所述第二晶粒電性連接。
在一些實施例中,所述積體扇出型封裝更包括位於所述重佈線結構上的多個導電端子。
在一些實施例中,所述相同材料包括彈性聚合物材料(elastic polymeric material)或熱固性材料(thermosetting material)。
在一些實施例中,由所述相同材料所形成的所述層接觸所述包封體的所述第一表面且接觸所述第一晶粒的所述主動表面及所述第二晶粒的所述主動表面。
在一些實施例中,所述第一晶粒的所述多個導電柱的高度與所述第二晶粒的所述多個導電柱的高度相同。
根據本發明的一些實施例,一種積體扇出型封裝的製造方法至少包括以下步驟。提供載板,所述載板上形成有黏著層。在所述黏著層上提供第一晶粒及第二晶粒。所述第一晶粒的高度不同於所述第二晶粒的高度。所述第一晶粒具有第一導電柱且所述第二晶粒具有第二導電柱。將所述第一晶粒及所述第二晶粒壓抵(press against)在所述黏著層上,以使所述第一晶粒的主動表面及所述第二晶粒的主動表面直接接觸所述黏著層且使所述第一導電柱及所述第二導電柱浸沒(submerge)在所述黏著層中。將所述黏著層固化。形成包封體,以包封所述第一晶粒及所述第二晶粒。從所述黏著層移除所述載板。減小所述黏著層的高度以及所述第一導電柱的高度及所述第二導電柱的高度,使得所述第一導電柱及所述第二導電柱從所述黏著層暴露出。在所述黏著層以及所述第一導電柱及所述第二導電柱上形成重佈線結構,使得所述重佈線結構與所述第一導電柱及所述第二導電柱電性連接。
在一些實施例中,所述積體扇出型封裝的製造方法更包括執行單體化製程(singulation process)以將所述積體扇出型封裝單體化。
在一些實施例中,所述積體扇出型封裝的製造方法更包括在所述重佈線結構上形成多個導電端子。
在一些實施例中,所述黏著層是由熱固性材料所形成,且所述黏著層是在形成所述包封體之前固化。
在一些實施例中,所述黏著層的高度大於或等於所述第一晶粒的所述第一導電柱的高度及所述第二晶粒的所述第二導電柱的高度。
在一些實施例中,減小所述黏著層的高度以及所述多個第一及第二導電柱的高度包括執行飛切製程(fly cutting process)或化學機械拋光製程(chemical mechanical polishing process)。
在一些實施例中,形成所述包封體至少包括以下步驟。在所述黏著層上形成包封材料,以包封所述第一晶粒及所述第二晶粒。所述包封材料的高度大於所述第一晶粒的所述高度及所述第二晶粒的所述高度。減小所述包封材料的所述高度、所述第一晶粒的所述高度、及所述第二晶粒的所述高度以形成所述包封體。所述包封體的表面與所述第一晶粒的所述後表面及所述第二晶粒的所述後表面齊平。
根據本發明的一些替代實施例,一種積體扇出型封裝的製造方法至少包括以下步驟。提供第一載板,所述第一載板上形成有黏著層。將第一晶粒及第二晶粒壓抵在所述黏著層上。第一晶粒及第二晶粒分別具有主動表面、與所述主動表面相對的後表面、及形成在所述主動表面上的多個導電柱。所述第一晶粒的高度不同於所述第二晶粒的高度。所述第一晶粒的所述主動表面及所述第二晶粒的所述主動表面被壓至直接接觸所述黏著層。所述導電柱被壓至浸沒在所述黏著層中。形成包封體,以包封所述第一晶粒及所述第二晶粒。將所述第一晶粒的所述後表面及所述第二晶粒的所述後表面貼合到第二載板。移除所述第一載板。從所述第一晶粒、所述第二晶粒及所述包封體移除所述黏著層。在所述第一晶粒的所述主動表面及所述第二晶粒的所述主動表面上形成基底材料層,以包封所述導電柱。減小所述基底材料層的高度及所述導電柱的高度。在所述導電柱上形成重佈線結構,使得所述重佈線結構與所述導電柱電性連接。從所述第一晶粒的所述後表面及所述第二晶粒的所述後表面移除所述第二載板。
在一些實施例中,所述積體扇出型封裝的製造方法更包括單體化製程,以將所述積體扇出型封裝單體化。
在一些實施例中,所述積體扇出型封裝的製造方法更包括在所述重佈線結構上形成多個導電端子。
在一些實施例中,所述黏著層是由彈性聚合物材料所形成。
在一些實施例中,所述黏著層的高度大於或等於所述第一晶粒的所述多個導電柱的高度以及所述第二晶粒的所述多個導電柱的高度。
在一些實施例中,移除所述黏著層包括應用剝除製程(peel off process)、溶劑洗脫製程(solvent wash off process)、或蝕刻製程。
在一些實施例中,減小所述基底材料層的高度及所述多個導電柱的高度包括執行飛切製程或化學機械拋光製程。
在一些實施例中,形成所述包封體至少包括以下步驟。在所述黏著層上形成包封材料,以包封所述第一晶粒及所述第二晶粒。所述包封材料的高度大於所述第一晶粒的所述高度及所述第二晶粒的所述高度。減小所述包封材料的所述高度、所述第一晶粒的所述高度、及所述第二晶粒的所述高度以形成所述包封體。所述包封體的表面與所述第一晶粒的所述後表面及所述第二晶粒的所述後表面齊平。
以上概述了若干實施例的特徵,以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應知,他們可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到,這些等效構造並不背離本發明的精神及範圍,而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。
10、20‧‧‧積體扇出型封裝
100‧‧‧第一載板
110、610‧‧‧剝離層
200、200’、210‧‧‧黏著層
200a‧‧‧表面
210a、500a、510a、700a、710a‧‧‧第一表面
210b、500b、510b、700b‧‧‧第二表面
300‧‧‧第一晶粒
300a、400a‧‧‧主動表面
300b、300b’、400b、400b’‧‧‧後表面
310、310’、410、410’‧‧‧導電柱
310a’、410a’‧‧‧頂表面
400‧‧‧第二晶粒
500‧‧‧包封材料
510‧‧‧包封體
600‧‧‧第二載板
620‧‧‧晶粒貼合膜
700‧‧‧基底材料層
710‧‧‧基底層
800‧‧‧重佈線結構
802‧‧‧重佈線導電圖案
804‧‧‧介電層
806‧‧‧導通孔
900‧‧‧導電端子
H200
、H200’、H210、H300、H300’、H310
、H310’、H400、H400’、H410、H410’、H500、H510、H700、H710‧‧‧高度
SW300、SW400‧‧‧側壁
TP1‧‧‧剝離載體
TP2‧‧‧分割載體
X、Z‧‧‧方向
圖1A至圖1N繪示根據本發明一些實施例的製造積體扇出型封裝的方法中的各個階段的示意性剖面圖。 圖2A至圖2M繪示根據本發明一些替代實施例的製造積體扇出型封裝的方法中的各個階段的示意性剖面圖。
Claims (1)
- 一種積體扇出型封裝,包括: 第一晶粒及第二晶粒,分別具有主動表面、與所述主動表面相對的後表面、及形成在所述主動表面上的多個導電柱,其中所述第一晶粒與所述第二晶粒是不同類型的晶粒,所述第一晶粒的所述主動表面與所述第二晶粒的所述主動表面齊平,所述第一晶粒的所述後表面與所述第二晶粒的所述後表面齊平,所述第一晶粒的所述多個導電柱的頂表面與所述第二晶粒的所述多個導電柱的頂表面齊平,且所述第一晶粒的所述多個導電柱與所述第二晶粒的所述多個導電柱被由相同材料所形成的層包繞; 包封體,包封所述第一晶粒的側壁及所述第二晶粒的側壁,所述包封體具有第一表面及與所述第一表面相對的第二表面,所述第一表面與所述第一晶粒的所述主動表面及所述第二晶粒的所述主動表面齊平,且所述第二表面與所述第一晶粒的所述後表面及所述第二晶粒的所述後表面齊平;以及 重佈線結構,位於所述第一晶粒、所述第二晶粒、及所述包封體上,其中所述重佈線結構與所述第一晶粒及所述第二晶粒電性連接。
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US15/715,132 | 2017-09-25 |
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US10770394B2 (en) * | 2017-12-07 | 2020-09-08 | Sj Semiconductor (Jiangyin) Corporation | Fan-out semiconductor packaging structure with antenna module and method making the same |
KR20200113069A (ko) * | 2019-03-20 | 2020-10-06 | 삼성전자주식회사 | 반도체 소자 제조 방법 |
WO2021013097A1 (en) * | 2019-07-25 | 2021-01-28 | Nantong Tongfu Microelectronics Co., Ltd. | Packaging structure and formation method thereof |
US11239217B2 (en) * | 2020-03-30 | 2022-02-01 | Nanya Technology Corporation | Semiconductor package including a first sub-package stacked atop a second sub-package |
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US5486265A (en) * | 1995-02-06 | 1996-01-23 | Advanced Micro Devices, Inc. | Chemical-mechanical polishing of thin materials using a pulse polishing technique |
CN101147249B (zh) * | 2005-03-24 | 2010-05-19 | 松下电器产业株式会社 | 电子部件安装方法和电子电路装置 |
US8008125B2 (en) * | 2009-03-06 | 2011-08-30 | General Electric Company | System and method for stacked die embedded chip build-up |
US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
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US20190252339A1 (en) | 2019-08-15 |
US10867953B2 (en) | 2020-12-15 |
US20190096840A1 (en) | 2019-03-28 |
CN109560076A (zh) | 2019-04-02 |
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