CN109560057A - 一种多芯片倒装贴片三维集成封装结构及其制造方法 - Google Patents

一种多芯片倒装贴片三维集成封装结构及其制造方法 Download PDF

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CN109560057A
CN109560057A CN201811366711.5A CN201811366711A CN109560057A CN 109560057 A CN109560057 A CN 109560057A CN 201811366711 A CN201811366711 A CN 201811366711A CN 109560057 A CN109560057 A CN 109560057A
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chip
package substrate
salient point
patch
encapsulating structure
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金国庆
孙鹏
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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Abstract

本发明公开了一种多芯片倒装贴片三维集成封装结构，包括：封装基板；第一芯片，所述第一芯片正装设置在所述封装基板的对应位置；第二芯片，所述第二芯片倒装焊接至所述封装基板并覆盖所述第一芯片；塑封层，所述塑封层包覆所述第一芯片、第二芯片，且填充所述封装基板、第一芯片、第二芯片之间的间隙；以及外接焊盘，所述外接焊盘设置在所述封装基板的外表面。

Description

一种多芯片倒装贴片三维集成封装结构及其制造方法
技术领域
本发明涉及半导体封装技术领域，尤其涉及一种多芯片倒装贴片三维集成封装结构及其制造方法。
背景技术
随着半导体封装技术的发展，多芯片集成封装成为芯片封装的趋势。常规的多芯片封装可采用金线焊线或者芯片焊锡倒装互连的方式，其中倒装贴片省去了金线焊线的工艺产能瓶颈，为当前主流的多芯片高密集成封装方式。
传统的多芯片倒装贴片封装产品堆叠方式为两种：一种为芯片多次倒装到基板；另一种为芯片先互相倒装堆叠后，再整体贴装到基板，无论哪种方式均需要对多芯片分别做凸点制作处理，并且需要多次回流作业。这样就直接导致封装的工艺制程步骤较多，封装结构可靠性降低，并相应的降低了良率。
针对传统的多芯片倒装贴片封装产品堆叠方式存在的需要对多芯片分别做凸点和多次回流焊导致的工艺步骤多、封装结构可靠性低以及产品良率低等问题，本发明提出了一种新型的多芯片一次倒装贴片结构和方法，至少部分的克服了上述问题。
发明内容
针对传统的多芯片倒装贴片封装产品堆叠方式存在的需要对多芯片分别做凸点和多次回流焊导致的工艺步骤多、封装结构可靠性低以及产品良率低等问题，根据本发明的一个实施例，提供一种多芯片倒装贴片三维集成封装结构，包括：
封装基板；
第一芯片，所述第一芯片正装设置在所述封装基板的对应位置；
第二芯片，所述第二芯片倒装焊接至所述封装基板并覆盖所述第一芯片；
塑封层，所述塑封层包覆所述第一芯片、第二芯片，且填充所述封装基板、第一芯片、第二芯片之间的间隙；以及
外接焊盘，所述外接焊盘设置在所述封装基板的外表面。
在本发明的一个实施例中，所述第二芯片通过设置在其上的第一凸点倒装焊至所述第一芯片正面的焊盘。
在本发明的一个实施例中，所述第二芯片通过设置在其上的第二凸点倒装焊至所述封装基板上的焊盘。
在本发明的一个实施例中，所述第一芯片通过贴片层设置到所述封装基板的对应位置。
在本发明的一个实施例中，所述第二凸点的高度等于第一凸点高度、第一芯片厚度以及贴片层厚度之和。
在本发明的一个实施例中，所述第一芯片具有N个相同或不同的芯片，其中N≥2。
在本发明的一个实施例中，所述封装基板内或表面具有重新布局布线。
在本发明的一个实施例中，所述外接焊球通过所述重新布局布线与所述第二凸点连接；所述第二凸点通过第二芯片内的互连与所述第一凸点连接；所述第一凸点与所述第一芯片的焊盘连接。
根据本发明的另一个实施例，提供一种多芯片倒装贴片三维集成封装结构的制造方法，包括：在第一芯片上形成第一凸点；在第一芯片上形成第二凸点；提供第二芯片、贴片材料和封装基板；将第二芯片正装贴片至封装基板；将第一芯片倒装焊接至第二芯片和封装基板；对封装结构进行塑封保护；以及在封装基板的外表面形成外接焊球。
在本发明的另一个实施例中，所述第二芯片凸点的高度大于第一凸点的高度。
本发明提供一种多芯片倒装贴片三维集成封装结构及其制造方法，通过在一种芯片上制作多种尺寸的凸点，一次性实现了芯片到芯片、芯片到基板的凸点倒装焊互连，省掉了多次倒装贴片和回流焊处理，减少了工艺步骤，节约了芯片的凸点制作成本；同时提高了封装结构的可靠性和良率。
附图说明
为了进一步阐明本发明的各实施例的以上和其它优点和特征，将参考附图来呈现本发明的各实施例的更具体的描述。可以理解，这些附图只描绘本发明的典型实施例，因此将不被认为是对其范围的限制。在附图中，为了清楚明了，相同或相应的部件将用相同或类似的标记表示。
图1示出根据本发明的一个实施例形成的一种多芯片倒装贴片三维集成封装结构100的剖面示意图。
图2A至图2G示出根据本发明的一个实施例形成该种多芯片倒装贴片三维集成封装结构100的过程剖面示意图。
图3示出的是根据本发明的一个实施例形成该种多芯片倒装贴片三维集成封装结构100的流程图300。
具体实施方式
在以下的描述中，参考各实施例对本发明进行描述。然而，本领域的技术人员将认识到可在没有一个或多个特定细节的情况下或者与其它替换和/或附加方法、材料或组件一起实施各实施例。在其它情形中，未示出或未详细描述公知的结构、材料或操作以免使本发明的各实施例的诸方面晦涩。类似地，为了解释的目的，阐述了特定数量、材料和配置，以便提供对本发明的实施例的全面理解。然而，本发明可在没有特定细节的情况下实施。此外，应理解附图中示出的各实施例是说明性表示且不一定按比例绘制。
在本说明书中，对“一个实施例”或“该实施例”的引用意味着结合该实施例描述的特定特征、结构或特性被包括在本发明的至少一个实施例中。在本说明书各处中出现的短语“在一个实施例中”并不一定全部指代同一实施例。
需要说明的是，本发明的实施例以特定顺序对工艺步骤进行描述，然而这只是为了方便区分各步骤，而并不是限定各步骤的先后顺序，在本发明的不同实施例中，可根据工艺的调节来调整各步骤的先后顺序。
本发明提供一种多芯片倒装贴片三维集成封装结构及其制造方法，通过在一种芯片上制作多种尺寸的凸点，一次性实现了芯片到芯片、芯片到基板的凸点倒装焊互连，省掉了多次倒装贴片和回流焊处理，减少了工艺步骤，节约了芯片的凸点制作成本；同时提高了封装结构的可靠性和良率。
下面结合图1来详细介绍根据本发明的一个实施例的一种多芯片倒装贴片三维集成封装结构。图1示出根据本发明的一个实施例形成的一种多芯片倒装贴片三维集成封装结构100的剖面示意图。如图1所示，该多芯片倒装贴片三维集成封装结构100进一步包括封装基板110、第一芯片120、贴片层130、第二芯片140、第一凸点141、第二凸点142塑封层150以及外接焊盘160。
封装基板110为普通封装基板，如亚克力、PCB、玻璃等封装基板。在本发明的一个实施例中封装基板为多层板，其内和或表面设置有重新布局布线线路，上下表面的对应位置分别设置有焊盘。
第一芯片120可以为处理器、存储器、SOC等各类功能芯片，通过贴皮层130正装贴片至封装基板110的对应位置，第一芯片120的正面具有焊盘(图中未示出)。
第二芯片140通过第一凸点141和第二凸点142倒装焊接在第一芯片120 和封装基板110的对应焊盘上，其中通过第一凸点141与第一芯片120形成电和或信号互连；通过第二凸点142与封装基板110第一面的焊盘形成电和或信号的互连。其中第一凸点141的高度低于第二凸点142的高度，在封装结构中，第二凸点142的高度H等于第一凸点141的高度h与第一芯片120的厚度T 以及贴片层130的厚度t之和。
塑封层150位于封装基板110的第一面上，包覆第一芯片120、第二芯片 140，并填充封装基板110、第一芯片120以及第二芯片140之间的间隙。
外接焊盘160位于封装基板110的第二面，通过基板通孔(图中未示出) 和或重新布局布线互连(图中未示出)与第二芯片140电连接。
下面结合图2A至图2G以及图3来详细描述形成该种多芯片倒装贴片三维集成封装结构100的过程。图2A至图2G示出根据本发明的一个实施例形成该种多芯片倒装贴片三维集成封装结构100的过程剖面示意图；图3示出的是根据本发明的一个实施例形成该种多芯片倒装贴片三维集成封装结构100 的流程图300。
首先，在步骤301，如图2A所示，在第一芯片210上形成第一凸点211。第一凸点211可以通过电镀、植球等工艺形成；第一凸点211用于第一芯片210和其他芯片形成芯片间电和或信号互连。
接下来，在步骤302，如图2B所示，在第一芯片210上形成第二凸点 212。第二凸点212形成的位置与第一凸点211分离开。第二凸点212与第一凸点211类似，可以通过电镀、植球等工艺形成；第二凸点212的高度要大于第一凸点211的高度，具体的高度关系可以根据封装结构的设计确定；第二凸点212用于第一芯片210和封装基板的电和或信号互连。
然后，在步骤303，如图2C所示，提供第二芯片220、贴片材料230 和封装基板240。其中第二芯片220的上表面具有与第一芯片210上的第一凸点211对应的焊盘，贴片材料可以是粘接层、粘接胶、导电胶水、非导电胶水、DAF等多种形式；封装基板240为普通封装基板，如亚克力、PCB、玻璃等封装基板。在本发明的一个实施例中封装基板为多层板，其内和或表面设置有重新布局布线线路，上下表面的对应位置分别设置有焊盘。
接下来，在步骤304，如图2D所示，将第二芯片220正装贴片至封装基板240。具体贴片工艺为常规的正装贴片，包括对准、压合等工艺。
然后，在步骤305，如图2E所示，将第一芯片210倒装焊接至第二芯片220和封装基板240。其中通过第一芯片210上的第一凸点211形成第一芯片210与第二芯片220之间的电和或信号互连；通过第一芯片210上的第二凸点212形成第一芯片210与封装基板间的电和或信号互连。
接下来，在步骤306，如图2F所示，对封装结构进行塑封保护。塑封后，塑封层包覆第一芯片210、第二芯片220，并填充封装基板240、第一芯片210以及第二芯片220之间的间隙。
最后，在步骤307，如图2G所示，在封装基板240的外表面形成外接焊球。具体形成外接焊球的方法可以通过电镀、植球等工艺实现。
下面介绍根据本发明的又一实施例的一种多芯片倒装贴片三维集成封装结构。该多芯片倒装贴片三维集成封装结构与多芯片倒装贴片三维集成封装结构100的区别仅在于其第一芯片具有多个。本领域的技术人员应该可以理解到，可以具有更多个的二组合。同时可以设置在第二芯片上设置3种、4种或更多种高度的凸点，以实现不同尺寸、数量的芯片间的一次倒装焊封装，再次不在赘述。
基于本发明提供的该种多芯片倒装贴片三维集成封装结构及其制造方法，通过在一种芯片上制作多种尺寸的凸点，一次性实现了芯片到芯片、芯片到基板的凸点倒装焊互连，省掉了多次倒装贴片和回流焊处理，减少了工艺步骤，节约了芯片的凸点制作成本；同时提高了封装结构的可靠性和良率。
尽管上文描述了本发明的各实施例，但是，应该理解，它们只是作为示例来呈现的，而不作为限制。对于相关领域的技术人员显而易见的是，可以对其做出各种组合、变型和改变而不背离本发明的精神和范围。因此，此处所公开的本发明的宽度和范围不应被上述所公开的示例性实施例所限制，而应当仅根据所附权利要求书及其等同替换来定义。

Claims (10)

1.一种多芯片倒装贴片三维集成封装结构，包括：
封装基板；
第一芯片，所述第一芯片正装设置在所述封装基板的对应位置；
第二芯片，所述第二芯片倒装焊接至所述封装基板并覆盖所述第一芯片；
塑封层，所述塑封层包覆所述第一芯片、第二芯片，且填充所述封装基板、第一芯片、第二芯片之间的间隙；以及
外接焊盘，所述外接焊盘设置在所述封装基板的外表面。
2.如权利要求1所述的多芯片倒装贴片三维集成封装结构，其特征在于，所述第二芯片通过设置在其上的第一凸点倒装焊至所述第一芯片正面的焊盘。
3.如权利要求1所述的多芯片倒装贴片三维集成封装结构，其特征在于，所述第二芯片通过设置在其上的第二凸点倒装焊至所述封装基板上的焊盘。
4.如权利要求1所述的多芯片倒装贴片三维集成封装结构，其特征在于，所述第一芯片通过贴片层设置到所述封装基板的对应位置。
5.如权利要求1或2或3或4所述的多芯片倒装贴片三维集成封装结构，其特征在于，所述第二凸点的高度等于第一凸点高度、第一芯片厚度以及贴片层厚度之和。
6.如权利要求1所述的多芯片倒装贴片三维集成封装结构，其特征在于，所述第一芯片具有N个相同或不同的芯片，其中N≥2。
7.如权利要求1所述的多芯片倒装贴片三维集成封装结构，其特征在于，所述封装基板内或表面具有重新布局布线。
8.如权利要求7所述的多芯片倒装贴片三维集成封装结构，其特征在于，所述外接焊球通过所述重新布局布线与所述第二凸点连接；所述第二凸点通过第二芯片内的互连与所述第一凸点连接；所述第一凸点与所述第一芯片的焊盘连接。
9.一种多芯片倒装贴片三维集成封装结构的制造方法，包括：
在第一芯片上形成第一凸点；
在第一芯片上形成第二凸点；
提供第二芯片、贴片材料和封装基板；
将第二芯片正装贴片至封装基板；
将第一芯片倒装焊接至第二芯片和封装基板；
对封装结构进行塑封保护；以及
在封装基板的外表面形成外接焊球。
10.如权利要求9所述的多芯片倒装贴片三维集成封装结构的制造方法，其特征在于，所述第二芯片凸点的高度大于第一凸点的高度。
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