CN103915423A - 一种芯片三维堆叠封装结构及封装方法 - Google Patents

一种芯片三维堆叠封装结构及封装方法 Download PDF

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CN103915423A
CN103915423A CN201410136630.1A CN201410136630A CN103915423A CN 103915423 A CN103915423 A CN 103915423A CN 201410136630 A CN201410136630 A CN 201410136630A CN 103915423 A CN103915423 A CN 103915423A
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pcb substrate
encapsulating structure
dimensional stacked
packing
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徐健
孙鹏
王宏杰
陆原
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National Center for Advanced Packaging Co Ltd
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Abstract

本发明提供了一种芯片三维堆叠封装结构，实现了芯片在基板上的多层堆叠，保证了完成整个封装后结构的平衡，有效避免了封装结构的翘曲和内部芯片的碎裂，其包括PCB基板，其特征在于：所述PCB基板上设置有窗口，所述PCB基板上堆叠有多层芯片，所述多层芯片中的部分芯片套装在所述窗口内，本发明同时还提供了一种芯片三维堆叠封装结构的封装方法。

Description

一种芯片三维堆叠封装结构及封装方法
技术领域
本发明涉及微电子行业基板封装技术领域，具体涉及一种芯片三维堆叠封装结构及封装方法。
背景技术
当前半导体封装发展的趋势是越来越多的向高频、多芯片模块(MCM)方向发展。集成不同芯片堆叠而成的3D IC将成为主流发展趋势，系统集成(SiP)封装，堆叠封装(PiP, PoP)所占的市场份额也逐年增加，2.5D/3D TSV技术也处于准备量产阶段。由于封装外形尺寸的限制，在一个封装体内放入不同功能模块的封装体（芯片或者塑封好的package），封装体外形尺寸不可能做的很大，因此，芯片在高度方向的堆叠是一个大的趋势。目前已经存在众多可供应用的堆叠芯片封装结构，在其中的一些结构中包含了不同尺寸的芯片，并以金字塔的形式逐层往上堆叠。另外一部分结构则使用相同尺寸的芯片逐层往上堆叠。此外，还有一种对不同尺寸的芯片进行堆叠的方法，它在上部芯片和底层芯片间插入了一个间隔层，以产生芯片的悬空（over-hang）结构。见图1，由于芯片2在高度方向上的堆叠和塑封只处于封装基板1的一面，在完成整个封装后结构不平衡，容易产生结构内部应力的集中，从而导致结构产生翘曲和内部芯片的碎裂。
发明内容
针对上述问题，本发明提供了一种芯片三维堆叠封装结构，实现了芯片在基板上的多面堆叠，保证了完成整个封装后结构的平衡，有效避免了封装结构的翘曲和内部芯片的碎裂，本发明同时还提供了一种芯片三维堆叠封装结构的封装方法。
其技术方案如下： 
一种芯片三维堆叠封装结构，其包括PCB基板，其特征在于：所述PCB基板上设置有窗口，所述PCB基板上封装堆叠有多层芯片，所述多层芯片中的部分芯片套装在所述窗口内。
其进一步特征在于：所述多层芯片中上层芯片的长度长于所述多层芯片中下层芯片长度，所述多层芯片中上层芯片与所述PCB基板间通过第一焊球连接；所述PCB基板上与所述第一焊球对应面设置有第二焊球；所述多层芯片间通过粘结连接；所述上层芯片连接所述PCB基板；所述芯片通过金属引线连接所述PCB基板；所述多层芯片通过塑封材料连接所述PCB基板，成型塑封结构，形成芯片的密封。
一种芯片三维堆叠封装结构的封装方法，其包括以下步骤：
（1）、在PCB基板设计过程中，预先留出开窗位置，在PCB基板制造过程中，将这些开窗位置进行开窗处理；
（2）、芯片贴装，完成层芯片与基板之间的电学连接；
（3）、芯片贴装，在PCB基板开窗位置，完成芯片之间的物理结构连接；
（4）、芯片金属引线连接，以实现芯片与PCB基板的信号互联；
（5）、整体塑封，形成环境保护； 
（6）、器件植球，形成信号回路； 
其进一步特征在于，步骤（2）中，芯片通过焊球与PCB基板上面的焊盘一一对位互联，以达到信号互联；
 步骤（3）中，芯片之间通过粘结连接；
步骤（4）中，金属引线通过芯片上的焊接pad焊接连接PCB基板；
步骤（5）中，采用上下模分离的模具结构，将整个结构一并塑封起来，实现一次塑封整体结构；
    步骤（6）中，在PCB基板的背面进行锡球焊接，完成整个封装工艺，焊球高度需要大于塑封高度。 
采用本发明是的上述结构中，由于PCB基板上设置有窗口， PCB基板上堆叠有多层芯片，多层芯片中的部分芯片套装在所述窗口内，使得整体封装结构相对对称，保证了完成整个封装后结构的平衡，有效避免了封装结构的翘曲和内部芯片的碎裂，提高产品可靠性。
附图说明
图1为现有的芯片三维堆叠封装结构示意图；
图2为本发明芯片三维堆叠封装结构结构示意图；
图3为基板结构加工示意图；
图4为芯片贴装示意图；
图5为多层芯片贴装工示意图；
图6为芯片金属引线焊接示意图；
图7为芯片整体塑封示意图；
图8为器件植球示意图。
具体实施方式
以下结合附图来对发明进行详细描述，但是本实施方式并不限于本发明，本领域的普通技术人员根据本实施方式所做出的结构、方法或者功能上的变换，均包含在本发明的保护范围内
见图2，一种三维堆叠封装结构，其包括PCB基板1， PCB基板1上设置有窗口2， PCB基板1上堆叠有多层芯片，多层芯片间相互粘结连接，多层芯片中上层芯片3的长度长于多层芯片中下层芯片5的长度，多层芯片中的下层芯片5套装在窗口2内，多层芯片中上层芯片3与PCB基板1间通过第一焊球4连接； PCB基板1上与第一焊球4对应面设置有第二焊球9，下层芯片5通过金属引线7连接PCB基板1，以实现下层芯片5与PCB基板1的信号互联，上层芯片3与下层芯片5通过塑封材料连接PCB基板1，成型塑封结构8，形成对芯片的密封。
      本发明同时还提供了一种三维堆叠封装结构的封装方法，其包括以下步骤：
见图3，（1）、基板结构加工，在PCB基板1设计过程中，预先留出开窗位置，成型窗口2，在PCB制造过程中，将这些开窗位置进行开窗处理；
见图4，（2）、芯片贴装，完成上层芯片3与PCB基板1之间的电学连接。将倒装的上层芯片3上的第一焊球4与PCB基板1上面的焊盘一一对位互联，以达到信号互联。 
       见图5，（3）、芯片贴装，完成上层芯片3与下层芯片5之间的物理结构连接。 在PCB基板开窗位置2，通过粘合剂，将上层芯片3与下层芯片5进行物理结构上的粘结。下层芯片5上面的焊接pad6向下，面向PCB基板1的背面；
见图6，（4）、芯片金属引线7焊接，以实现下层芯片5与PCB基板1的信号互联。在金属引线焊接时，下层芯片5的焊接pad6面向下，与PCB基板1的背面的焊接点相互连接，实现信号之间的互联。
见图7，（5）、整体塑封，形成环境保护。 在塑封的时候，选用上下模分离的模具结构，将整个结构一并塑封起来，实现一次塑封结构8；
见图8，（6）、器件植球，形成信号回路。在PCB基板1的背面进行第二焊球9焊接，完成整个封装工艺。 另外，在器件的塑封和进行第二焊球9焊接的时候，在基板的背面方向。最后的第二焊球9高度需要大于塑封结构8高度，以方便在后续的工艺中，器件整体焊接在PCB主板上面的实现。
本发明的优势如下：
（1）、本发明采用在上下两个方向各自贴装芯片，并进行一次性塑封，封装结构相对对称，有利于降低封装体的翘曲情况，提高产品可靠性。
（2）、本发明无需进行底填工艺，可直接保证小间隙封装体完全一次性塑封。
（3）、本发明只需在基板制造过程中加入开槽，工艺简单，操作方便。
（4）、本发明由于减少了塑封料的流动距离，提高了整个结构的可塑封性能 。
（5）、本发明由于采用双面贴装芯片的方案，封装结构在高度方向可适当减薄，整个封装厚度较小。

Claims (10)

1.一种芯片三维堆叠封装结构，其包括PCB基板，其特征在于：所述PCB基板上设置有窗口，所述PCB基板上堆叠有多层芯片，所述多层芯片中的部分芯片套装在所述窗口内。
2.根据权利要求1所述的芯片三维堆叠封装结构，其特征在于：所述多层芯片中上层芯片的长度长于所述多层芯片中下层芯片长度，所述多层芯片中上层芯片与所述PCB基板间通过第一焊球连接。
3.根据权利要求2所述的芯片三维堆叠封装结构，其特征在于：所述PCB基板上与所述第一焊球对应面设置有第二焊球，所述芯片通过金属引线连接所述PCB基板，所述多层芯片通过塑封材料连接所述PCB基板，形成芯片的密封。
4.根据权利要求1所述的芯片三维堆叠封装结构，其特征在于：所述多层芯片间通过粘结连接。
5.一种权利要求1所述的芯片三维堆叠封装结构的封装方法，其特征在于：其包括以下步骤：
（1）、在PCB基板设计过程中，预先留出开窗位置，在PCB基板制造过程中，将这些开窗位置进行开窗处理；
（2）、芯片贴装，完成层芯片与基板之间的电学连接；
（3）、芯片贴装，在PCB基板开窗位置，完成芯片之间的物理结构连接；
（4）、芯片金属引线连接，以实现芯片与PCB基板的信号互联；
（5）、整体塑封，形成环境保护； 
（6）、器件植球，形成信号回路。
6.根据权利要求5所述的芯片三维堆叠封装结构的封装方法，其特征在于：步骤（2）中，芯片通过焊球与PCB基板上面的焊盘一一对位互联，以达到信号互联。
7.根据权利要求5所述的芯片三维堆叠封装结构的封装方法，其特征在于：步骤（3）中，芯片之间通过粘结连接。
8.根据权利要求5所述的芯片三维堆叠封装结构的封装方法，其特征在于：步骤（4）中，金属引线通过芯片上的焊接pad焊接连接PCB基板。
9.根据权利要求5所述的芯片三维堆叠封装结构的封装方法，其特征在于：步骤（5）中，采用上下模分离的模具结构，将整个结构一并塑封起来，实现一次塑封整体结构。
10.根据权利要求5所述的芯片三维堆叠封装结构的封装方法，其特征在于：步骤（6）中，在PCB基板的背面进行锡球焊接，完成整个封装工艺，焊球高度需要大于塑封高度。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017117909A1 (zh) * 2016-01-07 2017-07-13 中兴通讯股份有限公司 一种移动终端及其封装芯片
WO2018205625A1 (zh) * 2017-05-10 2018-11-15 叶秀慧 薄型化双芯片的叠接封装结构
CN109887900A (zh) * 2019-03-08 2019-06-14 中国科学院微电子研究所 带有软硬结合板的大尺寸芯片系统封装结构及其制作方法
CN110759311A (zh) * 2019-10-29 2020-02-07 太极半导体（苏州）有限公司 一种基于窗口式基板的无引线mems芯片封装结构及其工艺

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020105789A1 (en) * 2001-02-02 2002-08-08 Siliconware Precision Industries Co., Ltd. Semiconductor package for multi-chip stacks
US20080111248A1 (en) * 2004-12-14 2008-05-15 Chee Seng Foong Flip Chip And Wire Bond Semiconductor Package
US20080237833A1 (en) * 2007-03-27 2008-10-02 Phoenix Precision Technology Corporation Multi-chip semiconductor package structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020105789A1 (en) * 2001-02-02 2002-08-08 Siliconware Precision Industries Co., Ltd. Semiconductor package for multi-chip stacks
US20080111248A1 (en) * 2004-12-14 2008-05-15 Chee Seng Foong Flip Chip And Wire Bond Semiconductor Package
US20080237833A1 (en) * 2007-03-27 2008-10-02 Phoenix Precision Technology Corporation Multi-chip semiconductor package structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017117909A1 (zh) * 2016-01-07 2017-07-13 中兴通讯股份有限公司 一种移动终端及其封装芯片
WO2018205625A1 (zh) * 2017-05-10 2018-11-15 叶秀慧 薄型化双芯片的叠接封装结构
CN109887900A (zh) * 2019-03-08 2019-06-14 中国科学院微电子研究所 带有软硬结合板的大尺寸芯片系统封装结构及其制作方法
CN110759311A (zh) * 2019-10-29 2020-02-07 太极半导体（苏州）有限公司 一种基于窗口式基板的无引线mems芯片封装结构及其工艺

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