CN109508306B - 高带宽存储系统 - Google Patents

高带宽存储系统 Download PDF

Info

Publication number
CN109508306B
CN109508306B CN201810908900.4A CN201810908900A CN109508306B CN 109508306 B CN109508306 B CN 109508306B CN 201810908900 A CN201810908900 A CN 201810908900A CN 109508306 B CN109508306 B CN 109508306B
Authority
CN
China
Prior art keywords
command
high bandwidth
host device
memory processing
bandwidth storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810908900.4A
Other languages
English (en)
Chinese (zh)
Other versions
CN109508306A (zh
Inventor
克里希纳·T·马拉迪
郑宏忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN109508306A publication Critical patent/CN109508306A/zh
Application granted granted Critical
Publication of CN109508306B publication Critical patent/CN109508306B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661—Format or protocol conversion arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/068—Hybrid storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System (AREA)
  • Dram (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
CN201810908900.4A 2017-09-14 2018-08-10 高带宽存储系统 Active CN109508306B (zh)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US201762558741P 2017-09-14 2017-09-14
US201762558732P 2017-09-14 2017-09-14
US201762558726P 2017-09-14 2017-09-14
US62/558,726 2017-09-14
US62/558,741 2017-09-14
US62/558,732 2017-09-14
US15/821,688 US10592121B2 (en) 2017-09-14 2017-11-22 Quasi-synchronous protocol for large bandwidth memory systems
US15/821,688 2017-11-22

Publications (2)

Publication Number Publication Date
CN109508306A CN109508306A (zh) 2019-03-22
CN109508306B true CN109508306B (zh) 2023-11-10

Family

ID=65631048

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201810908900.4A Active CN109508306B (zh) 2017-09-14 2018-08-10 高带宽存储系统
CN201810945829.7A Active CN109508307B (zh) 2017-09-14 2018-08-16 高带宽存储系统

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201810945829.7A Active CN109508307B (zh) 2017-09-14 2018-08-16 高带宽存储系统

Country Status (5)

Country Link
US (4) US10908820B2 (enExample)
JP (2) JP6941082B2 (enExample)
KR (2) KR102651892B1 (enExample)
CN (2) CN109508306B (enExample)
TW (2) TWI746852B (enExample)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9997232B2 (en) * 2016-03-10 2018-06-12 Micron Technology, Inc. Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations
FR3075444B1 (fr) * 2017-12-19 2020-07-24 Commissariat Energie Atomique Systeme comportant une memoire adaptee a mettre en oeuvre des operations de calcul
JP2022507516A (ja) 2018-11-15 2022-01-18 クアンタム－エスアイ インコーポレイテッド タンパク質シーケンシングのための方法及び組成物
DE102020105628A1 (de) 2019-03-11 2020-09-17 Samsung Electronics Co., Ltd. Verfahren zur Durchführung interner Verarbeitungsvorgänge mit vordefinierter Protokollschnittstelle einer Speichervorrichtung
KR102707631B1 (ko) * 2019-05-10 2024-09-13 에스케이하이닉스 주식회사 연산 회로를 포함하는 메모리 장치, 이를 제어하는 메모리 컨트롤러 및 이를 포함하는 메모리 시스템
US11086804B2 (en) * 2019-12-09 2021-08-10 Western Digital Technologies, Inc. Storage system and method for reducing read-retry duration
US10841645B1 (en) 2019-12-09 2020-11-17 Western Digital Technologies, Inc. Storage system and method for video frame segregation to optimize storage
EP4081890B1 (en) 2019-12-26 2025-04-02 Micron Technology, Inc. Truth table extension for stacked memory systems
CN114846545A (zh) 2019-12-26 2022-08-02 美光科技公司 用于堆叠式存储器系统的非确定性操作的技术
CN115427925A (zh) 2019-12-26 2022-12-02 美光科技公司 用于堆叠存储器系统的主机技术
US11526435B2 (en) 2020-02-04 2022-12-13 Western Digital Technologies, Inc. Storage system and method for automatic data phasing
US11562018B2 (en) 2020-02-04 2023-01-24 Western Digital Technologies, Inc. Storage system and method for optimized surveillance search
US11328511B2 (en) 2020-03-13 2022-05-10 Western Digital Technologies, Inc. Storage system and method for improved playback analysis
CA3177375A1 (en) 2020-05-20 2021-11-25 Quantum-Si Incorporated Methods and compositions for protein sequencing
EP4165637A4 (en) * 2020-06-16 2024-07-10 Groq, Inc. DETERMINISTIC MEMORY CLOSE TO COMPUTATION FOR DETERMINISTIC PROCESSOR AND ENHANCED DATA MOVEMENT BETWEEN MEMORY UNITS AND PROCESSING UNITS
KR20220053249A (ko) * 2020-10-22 2022-04-29 에스케이하이닉스 주식회사 데이터 처리 장치, 이를 포함하는 데이터 처리 시스템 및 그 동작 방법
KR20220067961A (ko) * 2020-11-18 2022-05-25 삼성전자주식회사 프로세싱-인-메모리 및 프로세싱-인-메모리를 이용한 인스트럭션 출력 방법
US11625249B2 (en) * 2020-12-29 2023-04-11 Advanced Micro Devices, Inc. Preserving memory ordering between offloaded instructions and non-offloaded instructions
US11893278B2 (en) 2021-02-08 2024-02-06 Samsung Electronics Co., Ltd. Memory controller and memory control method for generating commands based on a memory request
CN113643739B (zh) * 2021-09-02 2025-02-07 西安紫光国芯半导体股份有限公司 一种llc芯片及缓存系统
EP4174672A1 (en) 2021-10-27 2023-05-03 Samsung Electronics Co., Ltd. Backward compatible processing-in-memory (pim) protocol
US12112828B2 (en) * 2021-11-24 2024-10-08 Micron Technology, Inc. Modification of a command timing pattern
US12019560B2 (en) 2021-12-20 2024-06-25 Advanced Micro Devices, Inc. Virtual partitioning a processor-in-memory (“PIM”)
US11934827B2 (en) 2021-12-20 2024-03-19 Advanced Micro Devices, Inc. Partition and isolation of a processing-in-memory (PIM) device
US11934698B2 (en) * 2021-12-20 2024-03-19 Advanced Micro Devices, Inc. Process isolation for a processor-in-memory (“PIM”) device
US12072761B2 (en) * 2022-06-02 2024-08-27 Micron Technology, Inc. Memory sub-system addressing for data and additional data portions
US20240088098A1 (en) * 2022-09-09 2024-03-14 Advanced Micro Devices, Inc. Hybrid memory architecture for advanced 3d systems
US12236134B2 (en) 2022-09-27 2025-02-25 Advanced Micro Devices, Inc. Bank-level parallelism for processing in memory
US20240103745A1 (en) * 2022-09-28 2024-03-28 Advanced Micro Devices, Inc. Scheduling Processing-in-Memory Requests and Memory Requests
US12131026B2 (en) 2022-12-29 2024-10-29 Advanced Micro Devices, Inc. Adaptive scheduling of memory and processing-in-memory requests

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396641A (en) * 1991-01-18 1995-03-07 Iobst; Kenneth W. Reconfigurable memory processor
CN102084428A (zh) * 2008-07-02 2011-06-01 美光科技公司 多模式存储器装置和方法
CN106471474A (zh) * 2014-06-02 2017-03-01 美光科技公司 用于在可扩展存储器系统协议中传输包的系统及方法

Family Cites Families (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5901304A (en) 1997-03-13 1999-05-04 International Business Machines Corporation Emulating quasi-synchronous DRAM with asynchronous DRAM
US6336159B1 (en) 1997-06-25 2002-01-01 Intel Corporation Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system
US6510503B2 (en) 1998-07-27 2003-01-21 Mosaid Technologies Incorporated High bandwidth memory interface
US6622235B1 (en) 2000-01-03 2003-09-16 Advanced Micro Devices, Inc. Scheduler which retries load/store hit situations
CA2316590A1 (en) 2000-08-23 2002-02-23 Celestica International Inc. System and method for using a synchronous device with an asynchronous memory controller
US7412553B2 (en) 2002-01-10 2008-08-12 O2Micro International Limited Enhanced protocol conversion system capable of providing offloaded protocol instruction processing
US7296112B1 (en) 2002-12-10 2007-11-13 Greenfield Networks, Inc. High bandwidth memory management using multi-bank DRAM devices
JP4383148B2 (ja) 2003-11-25 2009-12-16 株式会社日立製作所 処理オフロード機能モジュールを備えた磁気ディスクアレイ装置
US7363406B2 (en) 2004-12-08 2008-04-22 Motorola, Inc. Dynamic access scheduling memory controller
US8386722B1 (en) * 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
DE112007000101C9 (de) 2006-05-29 2017-08-10 Certgate Gmbh Verfahren zur Kommunikation mit einer Multifunktionsspeicherkarte
US20080001271A1 (en) 2006-06-30 2008-01-03 Sony Ericsson Mobile Communications Ab Flipped, stacked-chip IC packaging for high bandwidth data transfer buses
US8117415B2 (en) * 2006-09-18 2012-02-14 Sandisk Il Ltd. Storage device estimating a completion time for a storage operation
US20080162855A1 (en) 2006-12-29 2008-07-03 Tessil Thomas Memory Command Issue Rate Controller
US7865660B2 (en) 2007-04-16 2011-01-04 Montage Technology Group Ltd. Calibration of read/write memory access via advanced memory buffer
US8024511B2 (en) 2007-08-31 2011-09-20 Siemens Industry, Inc. Systems, devices, and/or methods to access synchronous RAM in an asynchronous manner
US8042082B2 (en) 2007-09-12 2011-10-18 Neal Solomon Three dimensional memory in a system on a chip
US7921272B2 (en) 2007-10-05 2011-04-05 International Business Machines Corporation Monitoring patterns of processes accessing addresses in a storage device to determine access parameters to apply
US7747803B2 (en) * 2007-11-28 2010-06-29 International Business Machines Corporation Device, system, and method of handling delayed transactions
US7855931B2 (en) 2008-07-21 2010-12-21 Micron Technology, Inc. Memory system and method using stacked memory device dice, and system using the memory system
JP5331427B2 (ja) * 2008-09-29 2013-10-30 株式会社日立製作所 半導体装置
JP2010146252A (ja) * 2008-12-18 2010-07-01 Nec Engineering Ltd Ｄｄｒメモリコントローラ
US8576714B2 (en) * 2009-05-29 2013-11-05 Futurewei Technologies, Inc. System and method for relay node flow control in a wireless communications system
JP2011081732A (ja) * 2009-10-09 2011-04-21 Elpida Memory Inc 半導体装置及びその調整方法並びにデータ処理システム
US8473695B2 (en) 2011-03-31 2013-06-25 Mosys, Inc. Memory system including variable write command scheduling
US8819687B2 (en) 2010-05-07 2014-08-26 Advanced Micro Devices, Inc. Scheduling for multiple memory controllers
US9251873B1 (en) 2010-05-20 2016-02-02 Kandou Labs, S.A. Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications
US8683148B2 (en) * 2010-06-30 2014-03-25 Sandisk Il Ltd. Status indication when a maintenance operation is to be performed at a memory device
US8314807B2 (en) 2010-09-16 2012-11-20 Apple Inc. Memory controller with QoS-aware scheduling
US8321627B1 (en) 2011-10-06 2012-11-27 Google Inc. Memory operation command latency management
WO2013153577A1 (en) 2012-04-12 2013-10-17 Hitachi, Ltd. Data transfer method and storage system adopting data transfer method
KR101975534B1 (ko) * 2012-09-11 2019-05-07 삼성전자주식회사 연산기능을 갖는 반도체 메모리 장치
US9201777B2 (en) 2012-12-23 2015-12-01 Advanced Micro Devices, Inc. Quality of service support using stacked memory device with logic die
BR122016006765B1 (pt) * 2013-03-15 2022-02-01 Intel Corporation Aparelho acoplado ao módulo de memória, sistema de memória e método
US9734097B2 (en) 2013-03-15 2017-08-15 Micron Technology, Inc. Apparatuses and methods for variable latency memory operations
WO2014193376A1 (en) * 2013-05-30 2014-12-04 Hewlett-Packard Development Company, L.P. Separate memory controllers to access data in memory
KR102094902B1 (ko) * 2013-07-08 2020-03-30 삼성전자주식회사 액티브 상태에서 인터페이스 모드를 전환하는 스토리지 시스템 및 ufs 시스템
US9535831B2 (en) 2014-01-10 2017-01-03 Advanced Micro Devices, Inc. Page migration in a 3D stacked hybrid memory
US20150270015A1 (en) 2014-03-19 2015-09-24 Micron Technology, Inc. Memory mapping
US9436397B2 (en) * 2014-09-23 2016-09-06 Sandisk Technologies Llc. Validating the status of memory operations
US9836277B2 (en) * 2014-10-01 2017-12-05 Samsung Electronics Co., Ltd. In-memory popcount support for real time analytics
KR20160063726A (ko) 2014-11-27 2016-06-07 에스케이하이닉스 주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
KR101782501B1 (ko) * 2014-12-10 2017-09-27 주식회사 엘지화학 고흡수성 수지의 제조 방법
US20160210174A1 (en) 2015-01-15 2016-07-21 Microsoft Corporation Hybrid Scheduler and Power Manager
WO2016118615A1 (en) 2015-01-20 2016-07-28 Ultrata Llc Object memory data flow instruction execution
JP2018517201A (ja) 2015-04-08 2018-06-28 ティントリ・インコーポレーテッドＴｉｎｔｒｉ Ｉｎｃｏｒｐｏｒａｔｅｄ 仮想マシンのためのネイティブなストレージサービス品質
US9443561B1 (en) 2015-05-21 2016-09-13 Advanced Micro Devices, Inc. Ring networks for intra- and inter-memory I/O including 3D-stacked memories
US20160379686A1 (en) 2015-06-29 2016-12-29 Microsoft Technology Licensing, Llc Server systems with hardware accelerators including stacked memory
US10540588B2 (en) 2015-06-29 2020-01-21 Microsoft Technology Licensing, Llc Deep neural network processing on hardware accelerators with stacked memory
US9633748B2 (en) 2015-08-17 2017-04-25 Micron Technology, Inc. Multi-channel testing
US9818458B1 (en) * 2015-09-23 2017-11-14 Intel Corporation Techniques for entry to a lower power state for a memory device
FR3042049A1 (enExample) 2015-10-01 2017-04-07 Upmem
KR101814577B1 (ko) * 2015-10-16 2018-01-03 삼성전자주식회사 프로세싱-인-메모리를 이용한 명령어 처리 방법 및 그 장치
US10528613B2 (en) 2015-11-23 2020-01-07 Advanced Micro Devices, Inc. Method and apparatus for performing a parallel search operation
WO2017120270A1 (en) 2016-01-04 2017-07-13 Gray Research LLC Massively parallel computer, accelerated computing clusters, and two dimensional router and interconnection network for field programmable gate arrays, and applications
US20170206033A1 (en) * 2016-01-19 2017-07-20 SK Hynix Inc. Mechanism enabling the use of slow memory to achieve byte addressability and near-dram performance with page remapping scheme
KR101735590B1 (ko) * 2016-01-22 2017-05-15 한양대학교 산학협력단 트랜잭션 추출 장치 및 방법
US11079936B2 (en) * 2016-03-01 2021-08-03 Samsung Electronics Co., Ltd. 3-D stacked memory with reconfigurable compute logic
US10430244B2 (en) 2016-03-28 2019-10-01 Micron Technology, Inc. Apparatuses and methods to determine timing of operations
US20170289850A1 (en) 2016-04-01 2017-10-05 Intel Corporation Write delivery for memory subsystem with narrow bandwidth repeater channel
US10453502B2 (en) 2016-04-04 2019-10-22 Micron Technology, Inc. Memory bank power coordination including concurrently performing a memory operation in a selected number of memory regions
US10083722B2 (en) 2016-06-08 2018-09-25 Samsung Electronics Co., Ltd. Memory device for performing internal process and operating method thereof
US10416896B2 (en) * 2016-10-14 2019-09-17 Samsung Electronics Co., Ltd. Memory module, memory device, and processing device having a processor mode, and memory system
US10268389B2 (en) * 2017-02-22 2019-04-23 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US10169261B1 (en) 2017-08-29 2019-01-01 International Business Machines Corporation Address layout over physical memory
US10741239B2 (en) 2017-08-31 2020-08-11 Micron Technology, Inc. Processing in memory device including a row address strobe manager
US10346092B2 (en) * 2017-08-31 2019-07-09 Micron Technology, Inc. Apparatuses and methods for in-memory operations using timing circuitry
US10416927B2 (en) * 2017-08-31 2019-09-17 Micron Technology, Inc. Processing in memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396641A (en) * 1991-01-18 1995-03-07 Iobst; Kenneth W. Reconfigurable memory processor
CN102084428A (zh) * 2008-07-02 2011-06-01 美光科技公司 多模式存储器装置和方法
CN106471474A (zh) * 2014-06-02 2017-03-01 美光科技公司 用于在可扩展存储器系统协议中传输包的系统及方法

Also Published As

Publication number Publication date
CN109508307A (zh) 2019-03-22
JP6941082B2 (ja) 2021-09-29
CN109508306A (zh) 2019-03-22
KR20190030586A (ko) 2019-03-22
JP6955478B2 (ja) 2021-10-27
KR102651892B1 (ko) 2024-03-28
TW201915732A (zh) 2019-04-16
US20190079678A1 (en) 2019-03-14
US10592121B2 (en) 2020-03-17
JP2019053726A (ja) 2019-04-04
TWI746852B (zh) 2021-11-21
US11893239B2 (en) 2024-02-06
CN109508307B (zh) 2024-01-05
US10908820B2 (en) 2021-02-02
KR20190030578A (ko) 2019-03-22
US20190079677A1 (en) 2019-03-14
US20210117103A1 (en) 2021-04-22
TWI761520B (zh) 2022-04-21
JP2019053725A (ja) 2019-04-04
US20200174676A1 (en) 2020-06-04
KR102412987B1 (ko) 2022-06-24
TW201915759A (zh) 2019-04-16

Similar Documents

Publication Publication Date Title
CN109508306B (zh) 高带宽存储系统
US9411538B2 (en) Memory systems and methods for controlling the timing of receiving read data
CN101583934B (zh) 包含高速串联缓冲器的存储器系统
EP3049946B1 (en) Read training a memory controller
EP2036095B1 (en) Memory device with speculative commands to memory core
US6728150B2 (en) Method and apparatus for supplementary command bus
CN105159853A (zh) 基于fpga的dfi标准ddr3控制器
US20120191943A1 (en) Dynamic protocol for communicating command and address information
CN109964209A (zh) 使用可变长度列命令的低功率存储器子系统
US8959271B2 (en) System and method for accessing memory
US12100468B2 (en) Standalone mode
CN110727401A (zh) 一种访存系统
US20250258782A1 (en) Asymmetric Read-Write Sequence for Interconnected Dies
CN118899021A (zh) 选择性动态随机存取存储器（dram）设备内元数据的存储和存取
CN120316058A (zh) 存储命令合并、分解方法和系统
CN109634880A (zh) 一种数据采集设备、数据交互设备及数据采集系统

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant