CN109427871A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN109427871A CN109427871A CN201810596906.2A CN201810596906A CN109427871A CN 109427871 A CN109427871 A CN 109427871A CN 201810596906 A CN201810596906 A CN 201810596906A CN 109427871 A CN109427871 A CN 109427871A
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- semiconductor device
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Classifications
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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Abstract
本发明提供一种半导体装置,包含衬底;堆叠在衬底上的多个沟道层;围绕多个沟道层的栅极电极;以及在栅极电极的相对侧上的嵌入式源极/漏极层。嵌入式源极/漏极层各自具有第一区域及在第一区域上的第二区域。第二区域具有具备不同成分的多个层。
Description
相关申请案的交叉参考
本专利申请案要求对在2017年8月29日于韩国知识产权局提交的韩国专利申请案第10-2017-0109428号的优先权,所述专利申请案的全部内容以引用的方式并入本文中。
技术领域
本发明概念涉及半导体装置及其制造方法。
背景技术
为了增加半导体装置的密度,已提出具有全环绕栅极(gate-all-around,GAA)结构的晶体管。这种GAA结构可以包含在衬底上形成具有纳米线形状的硅主体且形成栅极以包住所述硅主体。
由于具有这种GAA结构的晶体管使用三维沟道,所述晶体管可具有缩小的尺寸。此外,晶体管可实现改良的电流控制能力而无需增加栅极长度。此外,晶体管可抑制短沟道效应,所述短沟道效应可通过漏极电压影响沟道区的电势。
发明内容
本发明概念的方面可通过显著地减少半导体装置的栅极长度的增加来提供具有改良的交流电(alternating current,AC)特性的半导体装置。
本发明概念的方面可提供制造半导体装置的方法,所述方法可有助于其制造工艺。
根据本发明概念的一方面,一种半导体装置可以包含:衬底;堆叠在衬底上的多个沟道层;围绕所述多个沟道层的栅极电极;以及在栅极电极的相对侧上的嵌入式源极/漏极层,所述嵌入式源极/漏极层各自具有第一区域及在第一区域上的第二区域,所述第二区域具有具备不同成分的多个层。
根据本发明概念的一方面,一种半导体装置可以包含:衬底;堆叠在衬底上的多个沟道层,所述多个沟道层在第一方向上延伸;围绕所述多个沟道层的栅极电极,所述栅极电极在与第一方向相交的第二方向上延伸;以及在栅极电极的相对侧上的嵌入式源极/漏极层,其中所述多个沟道层中的至少一个第一沟道层可具有拥有与所述多个沟道层中的第二沟道层的第二长度相比在第一方向上更远地延伸的第一长度的区域,所述第二沟道层邻近于所述第一沟道层。所述多个沟道层中最远离衬底的顶部沟道层可具有在第一方向上延伸的朝向衬底减小的长度。
根据本发明概念的一方面,一种制造半导体装置的方法可以包含:在衬底上形成鳍结构,所述鳍结构具有交替堆叠的多个牺牲层及多个半导体层;形成与鳍结构相交的虚设栅极;通过各向异性地干式蚀刻鳍结构在虚设栅极的相对侧上形成凹口;使用各向同性干式蚀刻工艺扩展所述凹口以形成经扩展的凹口;以及在经扩展的凹口内形成嵌入式源极/漏极层。
根据本发明概念的一方面,半导体装置可以包含:衬底;在衬底上的嵌入式源极/漏极层;堆叠在衬底上的至少两个沟道层,所述至少两个沟道层邻近嵌入式源极/漏极层;栅极电极,在所述衬底上且包含栅极电极在所述至少两个沟道层之间的部分;栅极绝缘层,包含在嵌入式源极/漏极层与栅极电极的所述部分之间的第一材料,所述栅极电极的所述部分在所述至少两个沟道层之间;以及界面层,包括第二材料,所述界面层在所述嵌入式源极/漏极层与所述至少两个沟道层之间。
附图说明
当结合附图时本公开的上述以及其它方面、特征和优点将从以下详细描述更清晰地理解,在附图中:
图1为根据本发明概念的实例实施例的半导体装置的平面视图;
图2为图1中所示出的半导体装置沿着线I-I'截取的横截面图;
图3为图2中所示出的半导体装置的区域A的放大视图;
图4为图1中所示出的半导体装置沿着线II-II'截取的横截面图;
图5为根据本发明概念的实例实施例的半导体装置的部分放大视图,且为图3中所示出的半导体装置的经修改实例;
图6为根据本发明概念的实例实施例的半导体装置的横截面图,且为图4中所示出的半导体装置的经修改实例;
图7到图15为根据本发明概念的实施例的示出制造图1中所示出的半导体装置的方法的视图。
具体实施方式
在下文中,本发明概念的实例实施例将参考附图在下文描述。
图1为根据本发明概念的实例实施例的半导体装置的布局。
参考图1,根据本发明概念的实例实施例,半导体装置100可以包含设置在衬底上的突出部分104及与突出部分104相交的多个栅极电极130。突出部分104可在第一方向(例如,X轴方向)上延伸。栅极电极130可在与第一方向相交的第二方向(例如,Y轴方向)上延伸。嵌入式源极/漏极层107可以设置在栅极电极130中的每个的两个(例如,相对)侧面上。在第一方向上与栅极电极130相交的多个沟道层120可以设置在嵌入式源极/漏极层107之间。栅极电极130可围绕沟道层120。
图2为图1中所示出的半导体装置沿着线I-I'截取的横截面图。图3为图2中所示出的半导体装置的区域A的放大视图。图4为图1中所示出的半导体装置沿着线II-II'截取的横截面图。
参考图2到图4,根据本发明概念的实例实施例,半导体装置100可以包含衬底101、隔离绝缘层103、嵌入式源极/漏极层107、栅极绝缘层110、栅极电极130、间隔件140、保护层150以及层间绝缘层170。
衬底101可为半导体衬底。半导体衬底可以包含IV族半导体材料、III-V族化合物半导体材料及/或II-VI族化合物半导体材料。衬底101可以是绝缘体上硅(silicon oninsulator,SOI)衬底。
衬底101可以包含在第一方向(例如,X轴方向)上延伸的突出部分104。在一些实施例中,突出部分104可以包含鳍型有源区。隔离绝缘层103可以设置在衬底101上及设置在衬底101的突出部分104的侧表面上。隔离绝缘层103的上表面可低于突出部分104的上表面。突出部分104的上部部分可比隔离绝缘层103的上表面更远离衬底101的上表面(例如,可从衬底101突出得更多)。突出部分104可被称为有源区。
在第一方向(例如,X轴方向)上在突出部分104上延伸的沟道层120可以在垂直于衬底101的上表面的第三方向(例如,Z轴方向)上彼此间隔开。栅极电极130可在与突出部分104相交的第二方向上延伸。连接到沟道层120的嵌入式源极/漏极层107可以设置在栅极电极130中的每个的两侧上。沟道层120可以设置在嵌入式源极/漏极层107之间。在一些实施例中,多个沟道层120可布置(例如,堆叠)在第三方向上。
沟道层120中的至少一个可以包含其中所述至少一个沟道层120的长度可大于在第三方向(例如,Z轴方向)上邻近于所述至少一个沟道层120的另一沟道层120的长度的区域。沟道层120中的顶部沟道层120可以包含其中顶部沟道层120的长度可大于在第三方向(例如,Z轴方向)上邻近于所述顶部沟道层120的另一沟道层120的长度的区域。如本文中所使用,顶部沟道层120可以是在第三方向上堆叠的所述多个沟道层120中最远离衬底101的沟道层120。在一些实施例中,顶部沟道层120的长度可大于所述顶部沟道层120与衬底101之间的另一沟道层120的长度。顶部沟道层120的上部部分的长度可大于顶部沟道层120的下部部分的长度。顶部沟道层120具有在第一方向(例如,X轴方向)上延伸的长度,且顶部沟道层120的长度可朝向衬底101减小。顶部沟道层120的至少一个区域在第一方向上的长度可大于栅极电极130在第一方向上的长度。顶部沟道层120可具有倾斜侧表面。在本发明概念的一些实施例中,顶部沟道层120邻近于嵌入式源极/漏极层107的侧表面可以是关于衬底101的上表面倾斜的平坦表面。
在本发明概念的一些实施例中,顶部沟道层120邻近于嵌入式源极/漏极层107的侧表面可以是关于衬底101的上表面倾斜的弯曲表面(参考图5)。
在本发明概念的一实例实施例中,除了顶部沟道层120之外,沟道层120中的底部沟道层120还可包含其中底部沟道层120的长度可大于在第三方向(例如,Z轴方向)上邻近于所述底部沟道层120的另一沟道层120的长度的区域。如本文中所使用,底部沟道层120可以是在第三方向上堆叠的所述多个沟道层120中最接近于衬底101的沟道层120。与顶部沟道层120对比,底部沟道层120的下部部分的长度可大于底部沟道层120的上部部分的长度。底部沟道层120的下部部分可比底部沟道层120的上部部分更接近于衬底101。底部沟道层120具有在第一方向(例如,X轴方向)上延伸的长度,且底部沟道层120的长度可朝向衬底101增加。底部沟道层120的至少一个区域在第一方向上的长度可大于栅极电极130在第一方向上的长度。底部沟道层120邻近于嵌入式源极/漏极层107的侧表面可以是倾斜的平坦表面或倾斜的弯曲表面。
界面层106可设置在嵌入式源极/漏极层107与沟道层120之间。界面层106可设置在嵌入式源极/漏极层107与衬底101之间及/或嵌入式源极/漏极层107与突出部分104之间。
嵌入式源极/漏极层107中的每个可以包含衬层107a及依序堆叠在所述衬层107a上的第一外延层107b、第二外延层107c以及第三外延层107d(在本文中被称作第一外延层107b到第三外延层107d)。在一些实施例中,第一外延层107b到第三外延层107d可具有不同成分。界面层106可设置在衬层107a与沟道层120之间及/或衬层107a与衬底101之间。嵌入式源极/漏极层107可以包含第一区域及第二区域。衬层107a可形成嵌入式源极/漏极层107的第一区域,且第一外延层107b、第二外延层107c以及第三外延层107d可形成嵌入式源极/漏极层107的第二区域。
衬层107a可以包含与沟道层120的半导体材料实质上相同的半导体材料,且界面层106可以包含与第一外延层107b到第三外延层107d的半导体材料实质上相同的半导体材料。举例来说,界面层106可以包含锗化硅(SiGe),且衬层107a可以包含硅(Si),但本发明概念并不限于此。举例来说,第一外延层107b到第三外延层107d可以包含SiGe,但本发明概念并不限于此。第三外延层107d的锗含量可高于第二外延层107c的锗含量,且第二外延层107c的锗含量可高于第一外延层107b的锗含量。举例来说,锗含量可在从第一外延层107b朝向第三外延层107d的方向上增加。界面层106的锗含量可低于第一外延层107b的锗含量。
举例来说,界面层106可以包含5原子%到15原子%的锗(Ge),第一外延层107b可以包含17原子%到27原子%的Ge,第二外延层107c可以包含37原子%到47原子%的Ge,且第三外延层107d可以包含50原子%到60原子%的Ge。
衬层107a、第一外延层107b、第二外延层107c以及第三外延层107d可以掺杂有例如P型杂质。P型杂质可在选择性外延生长(selective epitaxial growth,SEG)工艺期间原位注入或通过后续的离子注入工艺注入。
界面层106中的各个界面层106的厚度可低于衬层107a的厚度。在一些实施例中,第一外延层107b到第三外延层107d的厚度可彼此不同。
在本发明概念的一实例实施例中,嵌入式源极/漏极层107中的每个可以包含衬层107a及具有不同成分的两个外延层。在一实例实施例中,嵌入式源极/漏极层107中的每个可以包含衬层107a及具有连续变化的成分的外延层。
嵌入式源极/漏极层107的上表面可高于顶部沟道层120的上表面。然而,本发明概念并不限于此。在一些实施例中,嵌入式源极/漏极层107的上表面可设置在与顶部沟道层120相同的水平面上。嵌入式源极/漏极层107的上表面可以是凸形弯曲表面。然而,本发明概念并不限于此。
栅极电极130的部分可在第一方向(例如,X轴方向)上设置在嵌入式源极/漏极层107之间,且可在与第一方向相交的第二方向(例如,Y轴方向)上在衬底101上延伸。栅极电极130及嵌入式源极/漏极层107可通过栅极绝缘层110隔绝。栅极电极130可围绕沟道层120。栅极绝缘层110可以设置在栅极电极130与沟道层120之间及栅极电极130与间隔件140之间。栅极电极130还可以形成于隔离绝缘层103上。栅极绝缘层110还可以设置在栅极电极130与隔离绝缘层103之间。
间隔件140可以设置在栅极电极130的两个侧壁上以在与栅极电极130的方向相同的方向上延伸。间隔件140可以由例如氮氧化硅(例如SiON)、氮化硅(例如SiN)、SiOC、SiOCN、SiBCN或其任何组合形成。
保护层150可以设置在栅极电极130上以保护栅极电极130。保护层150可包含例如氮化硅。层间绝缘层170可覆盖嵌入式源极/漏极层107。层间绝缘层170的上表面可以与保护层150的上表面共面。
参考图3,栅极绝缘层110可以包含多个层。在一实例实施例中,栅极绝缘层110可以包含第一绝缘层111及第二绝缘层112。第一绝缘层111及第二绝缘层112可具有不同电容率。第二绝缘层112的电容率可大于第一绝缘层111的电容率。在一些实施例中,第二绝缘层112可经设置比第一绝缘层111更接近于栅极电极130。举例来说,第一绝缘层111可经设置比第二绝缘层112更接近于沟道层120。具有比第一绝缘层111高的电容率水平的第二绝缘层112可具有比第一绝缘层111的厚度大的厚度。
具有比第一绝缘层111高的电容率水平的第二绝缘层112可以包含高介电常数(k)介电材料。高k介电材料可以例如是以下中的任何一个:氧化铝(Al2O3)、氧化钽(Ta2O3)、氧化钛(TiO2)、氧化钇(Y2O3)、氧化锆(ZrO2)、氧化锆硅(ZrSixOy)、氧化铪(HfO2)、氧化铪硅(HfSixOy)、氧化镧(La2O3)、氧化镧铝(LaAlxOy)、氧化镧铪(LaHfxOy)、氧化铪铝(HfAlxOy)、氧化镨(Pr2O3)或其任何组合。
在一些实施例中,栅极电极130可以包含多个金属层。在一些实施例中,包含于栅极电极130中的所述多个金属层可以设置在沟道层120之间。势垒金属层131可以设置为邻近于栅极绝缘层110,功函数金属层132可以设置在势垒金属层131上,且栅极金属层133可以设置在功函数金属层132上。在一些实施例中,沟道层120之间的空间可仅以栅极绝缘层110、势垒金属层131以及功函数金属层132填充。
势垒金属层131可例如包含金属氮化物,例如TiN、TaN、TaSiN、TiSiN等。功函数金属层132可决定半导体装置100的阈值电压。在一实例实施例中,功函数金属层132可以包含彼此堆叠的多个金属层。举例来说,功函数金属层132可以包含钌(Ru)、钯(Pd)、铂(Pt)、钴(Co)、镍(Ni)或其任何组合。栅极金属层133可例如由金属材料形成,例如钨(W)等。
参考图4,设置在衬底101上的沟道层120可以在第三方向(例如,Z轴方向)上彼此间隔开。栅极绝缘层110及栅极电极130可以设置在沟道层120之间以使沟道层120彼此分离。沟道层120可由栅极绝缘层110及栅极电极130包围。沟道层120可具有片状,所述片状在第二方向上(例如,在Y轴方向上)的宽度比在第三方向上的其厚度大。图4示出如具有角形的沟道层120的边缘。然而,本发明概念并不限于此。沟道层120的边缘可具有曲率。
在一些实施例中,沟道层120可具有带圆弧形横截面或椭圆形横截面的线形(参考图6)。
图7到图15为根据本发明概念的实施例的示出制造图1中所示出的半导体装置100的方法的视图。图7、图9、图11、图12、图13、图14以及图15为沿着图1的线I-I'截取的横截面视图,且图8及图10为沿着图1的线II-II'截取的横截面视图。
参考图7,多个牺牲层160a及多个半导体层120a可以交替堆叠在衬底101上。
牺牲层160a可首先形成于衬底101上,且半导体层120a可形成于牺牲层160a上。另一牺牲层160a可以重复形成于半导体层120a上。通过重复这种工艺,可以形成具有设置在其顶部上的半导体层120a的堆叠结构。图7示出如具有三个牺牲层160a及三个半导体层120a的堆叠结构。然而,本发明概念并不限于此。堆叠在衬底101上的牺牲层160a及半导体层120a的数目可以不同地改变。在一实例实施例中,一个牺牲层160a及一个半导体层120a可以堆叠在衬底101上。
半导体层120a可以包含第一半导体材料,且牺牲层160a可以包含第二半导体材料,所述第二半导体材料关于半导体层120a具有蚀刻选择性。举例来说,半导体层120a可以包含Si,且牺牲层160a可以包含SiGe。在一些实施例中,牺牲层160a可以包含SiGe,所述SiGe具有30原子%的锗含量。
在一些实施例中,半导体层120a及牺牲层160a的各自的厚度可以不同地改变。半导体层120a及牺牲层160a的各自的厚度可以是几纳米到几十纳米。举例来说,牺牲层160a的厚度可大于半导体层120a的厚度。
参考图8,鳍结构FS可通过选择性地去除半导体层120a及牺牲层160a的部分形成。鳍结构FS可在第一方向(例如,X轴方向)上在衬底101上延伸。
鳍结构FS可通过在衬底101上形成掩模图案及通过执行各向异性蚀刻工艺而形成,所述衬底具有堆叠在其上的半导体层120a及牺牲层160a。鳍结构FS可以包含彼此交替堆叠的半导体层120a及牺牲层160a。在形成鳍结构FS的过程中,突出部分104可以通过去除衬底101的一部分形成于衬底101上。衬底101的突出部分104可形成鳍结构FS以及半导体层120a及牺牲层160a。隔离绝缘层103可以形成于已去除衬底101的部分的区域上。隔离绝缘层103可覆盖突出部分104的侧表面的一部分。隔离绝缘层103的上表面可低于突出部分104的上表面。举例来说,衬底101的突出部分104可在隔离绝缘层103上方突出。
在形成鳍结构FS及隔离绝缘层103之后,可以去除掩模图案。
参考图9及图10,虚设栅极130a可以形成为与鳍结构FS相交。间隔件140及牺牲间隔件142可以形成于虚设栅极130a中的每个的侧壁上。虚设绝缘层128可以设置在虚设栅极130a与鳍结构FS之间。罩盖层135可进一步形成于虚设栅极130a上。
虚设栅极130a可在第二方向(例如,Y轴方向)上延伸。虚设绝缘层128、间隔件140以及牺牲间隔件142可在与虚设栅极130a的方向相同的方向上延伸。虚设栅极130a及虚设绝缘层128可在于隔离绝缘层103上方突出的鳍结构FS上。
虚设栅极130a可以由半导体材料,例如多晶硅等形成。间隔件140可以由例如氮氧化硅(例如SiON)、氮化硅(例如SiN)、SiOC、SiOCN、SiBCN或其任何组合形成。虚设绝缘层128可例如由氧化硅形成。
参考图11,凹口可以通过选择性地去除鳍结构FS的部分使用虚设栅极130a及间隔件140作为蚀刻掩模且使用各向异性干式蚀刻工艺而形成于虚设栅极130a中的每个的两个(例如,相对)侧面上。
作为在虚设栅极130a的两侧上产生凹口的结果,多个沟道层120可以形成于虚设栅极130a下方。此外,多个牺牲图案160可以形成于沟道层120之间。
衬底101的上表面的部分可通过凹口暴露。衬底101的上表面的部分可通过各向异性干式蚀刻工艺蚀刻。
参考图12,凹口可以使用各向同性干式蚀刻工艺扩展。
形成于虚设栅极130a中的每个的相对侧上的凹口可以在间隔件140及牺牲间隔件142的下方扩展。此外,可以蚀刻衬底101的上表面通过凹口暴露的部分。
斜面可以通过各向同性干式蚀刻工艺形成于沟道层120中的顶部沟道层120的侧表面上。顶部沟道层120的长度(例如,在X轴方向上的长度)可朝向衬底101减小。在一实例实施例中,斜面还可以通过各向同性干式蚀刻工艺形成于沟道层120中的底部沟道层120的侧表面上。底部沟道层120的长度(例如,在X轴方向上的长度)可朝向衬底101增加。
参考图13,嵌入式源极/漏极层107可以使用SEG工艺从扩展的凹口内的衬底101的上表面形成。
牺牲间隔件142可以通过预清洁工艺去除。在形成嵌入式源极/漏极层107之前,界面层106可以形成于凹口内。界面层106可以在氢气(H2)氛围下通过烘烤工艺形成。
嵌入式源极/漏极层107可以形成于界面层106上。衬层107a可首先形成于界面层106上。具有不同成分的第一外延层107b到第三外延层107d可以依序形成于衬层107a上。
衬层107a、第一外延层107b、第二外延层107c以及第三外延层107d可以掺杂有例如P型杂质。P型杂质可以在SEG工艺期间原位注入或通过后续的离子注入工艺注入。
界面层106的厚度可低于衬层107a的厚度。第一外延层107b到第三外延层107d的厚度可以不同地改变。
参考图14,第一开口部分OPa可以通过去除虚设栅极130a及虚设绝缘层128而形成。
层间绝缘层170可首先形成以覆盖虚设栅极130a。层间绝缘层170可以形成于间隔件140外部以覆盖嵌入式源极/漏极层107。
层间绝缘层170可以通过绝缘材料涂布工艺及平坦化工艺形成。罩盖层135可以去除,且虚设栅极130a可以通过平坦化工艺暴露。虚设栅极130a及虚设绝缘层128可以依序去除。
参考图15,第二开口部分OPb可以通过选择性地去除牺牲图案160形成。第一开口部分OPa及第二开口部分OPb可形成开口部分OP。
举例来说,沟道层120可以包含Si,且牺牲图案160可以包含SiGe。具有比Si的蚀刻速率高的SiGe的蚀刻速率的蚀刻剂可用于选择性地消除牺牲图案160。举例来说,可使用包含过氧化氢(H2O2)、氢氟酸(HF)以及乙酸(CH3COOH)的蚀刻剂;包含氢氧化铵(NH4OH)、过氧化氢(H2O2)以及去离子水(H2O)的蚀刻剂;以及包含过氧乙酸的蚀刻剂;或其任何组合。
当去除牺牲图案160时,可以去除界面层106的接触牺牲图案160的部分。衬层107a的一部分可通过第二开口部分OPb暴露。当衬层107a由Si形成时,可以防止衬层107a在牺牲图案160的去除中被蚀刻。因此,可以防止将在后续工艺中形成的栅极电极的长度在第一方向(例如,X轴方向)上增加。
再次参考图2到图4,栅极绝缘层110及栅极电极130可以依序形成于开口部分OP内。
栅极绝缘层110可以形成于通过开口部分OP暴露的间隔件140的内部侧表面上。栅极绝缘层110可以形成于通过开口部分OP暴露的沟道层120的表面上及嵌入式源极/漏极层107的部分的表面上。栅极绝缘层110可围绕沟道层120。栅极绝缘层110可以包含依序堆叠且具有不同电容率的第一绝缘层111及第二绝缘层112。第二绝缘层112的电容率可大于第一绝缘层111的电容率。
栅极电极130可以形成于栅极绝缘层110上。栅极电极130可以包含依序堆叠的势垒金属层131、功函数金属层132以及栅极金属层133。
保护层150可以形成于栅极金属层133上。保护层150可由例如氮化硅形成。保护层150可防止因氧气等渗透到栅极电极130中而导致的阈值电压的电平的改变。栅极电极130的一部分可以去除,且保护层150可以形成于已去除栅极电极130的部分的区域内。
如上文所述,根据本发明概念的实例实施例,具有改良的交流电(alternatingcurrent,AC)特性的半导体装置可以通过减少其栅极长度的增大而提供。
此外,本发明概念的实例实施例可提供制造这些改良的半导体装置的方法。
应理解,尽管术语“第一”、“第二”等在本文中用于描述本发明概念的实例实施例中的部件、区域、层、部分、区段、组件及/或元件,但所述部件、区域、层、部分、区段、组件及/或元件应不受这些术语限制。这些术语仅用于将一个部件、区域、部分、区段、组件或元件与另一部件、区域、部分、区段、组件或元件区分开。因此,在不脱离本发明概念的范围的情况下,下文所描述的第一部件、区域、部分、区段、组件或元件还可被称作第二部件、区域、部分、区段、组件或元件。举例来说,在不脱离本发明概念的范围的情况下,第一元件还可被称作第二元件,且类似地,第二元件还可被称作第一元件。
空间相对术语,例如“在…下方”、“下方”、“下部”、“上方”、“上部”等等,在本文中为易于描述可用于描述一个元件或特征与如图中所示出的另外的元件或特征的关系。应理解,空间相对术语既定涵盖装置在使用或操作中除图中描绘的定向外的不同定向。举例来说,如果图中的装置翻转,描述为在其它元件或特征“下方”或“之下”的元件则将定向在其它元件或特征“上方”。因此,示范性术语“下方”可涵盖上方和下方定向两者。装置可以其它方式定向(旋转90度或处于其它定向),且本文中所用的空间相对描述符可相应地进行解释。
本文中使用的术语仅出于描述特定实施例的目的,且并不意图限制实例实施例。如本文中所使用,除非上下文另外明确指示,否则单数形式“一”和“所述”既定还包含多数形式。应进一步理解,术语“包括”、“包含”在本文中使用时,指定存在所陈述的特征、整体、步骤、操作、元件及/或组件,但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件及/或其群组。
除非另外定义,否则本文中所使用的所有术语(包含技术和科学术语)具有与本发明概念本领域的普通技术人员通常所理解的相同的含义。还将理解,术语,例如常用词典中所定义的那些术语,应被解释为具有与其在说明书的上下文以及相关技术中的含义一致的含义,并且不应在理想化或过分形式化的意义上进行解释,除非在本文中这样明确定义。
当某一实例实施例可以不同方式实施时,特定工艺次序可以与所描述次序不同地执行。举例来说,两个连续描述的程序可实质上同时执行或以与所描述次序相反的次序执行。
在附图中,应预期作为例如制造技术和/或公差的结果而从所示出的形状的变化。因此,本发明概念的实例实施例不应被理解为限于本文中所说明的区域的特定形状,而是可解释为包含例如由制造工艺引起的形状的偏差。举例来说,示出为矩形形状的经蚀刻区域可以是圆弧形或一定曲率形状。因此,图中所示出的区域实际上是示意性的,且图中所示出的区域的形状既定示出装置的区域的特定形状且并不希望限制本发明概念的范围。如本文中所使用,术语“和/或”包含相关联的所列项目中的一或多个的任何和所有组合。例如“中的至少一个”等表述当在元件列表之前时修饰元件的整个列表而不是修饰列表中的个别元件。
将理解,当元件被称为“连接”或“耦合”到另一元件时,其可直接连接或耦合到另一元件或可存在介入元件。相比之下,当元件被称作“直接连接”或“直接耦合”到另一元件时,不存在插入元件。用于描述元件或层之间的关系的其它词应以相似的方式解释(例如,“在…之间”与“直接在…之间”、“邻近”与“直接邻近”、“在…上”与“直接在…上”)。
相同数字始终指代相同元件。因此,可参看其它附图来描述相同或类似数字,即使其既未提到,也未在对应的附图中描述。同样,可参看其它附图来描述未由参考数字表示的元件。
虽然上文已示出并描述了实例实施例,但对于本领域的技术人员将显而易见的是,可在不脱离如由所附权利要求书所定义的本发明概念的范围的情况下作出修改及变化。
Claims (20)
1.一种半导体装置,包括:
衬底;
多个沟道层,堆叠在所述衬底上;
栅极电极,围绕所述多个沟道层;以及
嵌入式源极/漏极层,在所述栅极电极的相对侧上,所述嵌入式源极/漏极层各自具有第一区域以及在所述第一区域上的第二区域,所述第二区域包括具有不同成分的多个层。
2.根据权利要求1所述的半导体装置,进一步包括:
界面层,在所述嵌入式源极/漏极层与所述多个沟道层之间以及所述嵌入式源极/漏极层与所述衬底之间。
3.根据权利要求2所述的半导体装置,其中所述第一区域以及所述多个沟道层都包括第一半导体材料,以及
其中所述界面层以及所述第二区域都包括第二半导体材料。
4.根据权利要求1所述的半导体装置,其中所述第一区域进一步包括P型杂质。
5.根据权利要求1所述的半导体装置,其中所述第二区域包括依序堆叠在所述第一区域上的第一外延层、第二外延层以及第三外延层。
6.根据权利要求5所述的半导体装置,其中所述第一外延层、所述第二外延层以及所述第三外延层包括锗化硅化合物,
其中所述第三外延层的第三锗含量高于所述第二外延层的第二锗含量,以及
其中所述第二外延层的所述第二锗含量高于所述第一外延层的第一锗含量。
7.根据权利要求1所述的半导体装置,其中所述多个沟道层包括第一沟道层以及第二沟道层,以及
其中所述第二沟道层的至少一个区域的长度大于所述第一沟道层的长度。
8.根据权利要求7所述的半导体装置,其中邻近于所述嵌入式源极/漏极层的所述第二沟道层的侧表面为关于所述衬底的上表面倾斜的平坦表面。
9.根据权利要求7所述的半导体装置,其中邻近于所述嵌入式源极/漏极层的所述第二沟道层的侧表面为关于所述衬底的上表面倾斜的弯曲表面。
10.根据权利要求7所述的半导体装置,其中所述第二沟道层的上部部分的长度大于所述第二沟道层的下部部分的长度。
11.根据权利要求1所述的半导体装置,其中所述多个沟道层包括第一沟道层、第二沟道层以及第三沟道层,
其中所述第三沟道层具有朝向所述衬底减小的长度,以及
其中所述第一沟道层具有朝向所述衬底增加的长度。
12.根据权利要求1所述的半导体装置,其中所述多个沟道层中的各个沟道层在垂直于所述衬底的第一方向上具有厚度,所述厚度低于在与所述第一方向交叉的第二方向上的宽度。
13.一种半导体装置,包括:
衬底;
多个沟道层,堆叠在所述衬底上,所述多个沟道层在第一方向上延伸;
栅极电极,围绕所述多个沟道层,所述栅极电极在与所述第一方向相交的第二方向上延伸;以及
嵌入式源极/漏极层,在所述栅极电极的相对侧上,
其中所述多个沟道层中的至少一个第一沟道层具有区域,所述区域具有与所述多个沟道层中的邻近于所述第一沟道层的第二沟道层的第二长度相比在所述第一方向上更远地延伸的第一长度。
14.根据权利要求13所述的半导体装置,其中所述多个沟道层中最远离所述衬底的顶部沟道层具有倾斜侧表面。
15.根据权利要求13所述的半导体装置,其中所述多个沟道层中最远离所述衬底的顶部沟道层具有在所述第一方向上延伸的朝向所述衬底减小的长度。
16.根据权利要求13所述的半导体装置,其中所述嵌入式源极/漏极层各自具有第一区域以及在所述第一区域上的第二区域,以及
其中所述第二区域包括具有不同成分的多个层。
17.根据权利要求13所述的半导体装置,进一步包括:
界面层,在所述嵌入式源极/漏极层与所述多个沟道层之间以及所述嵌入式源极/漏极层与所述衬底之间。
18.一种半导体装置,包括:
衬底;
嵌入式源极/漏极层,在所述衬底上;
至少两个沟道层,堆叠在所述衬底上,所述至少两个沟道层邻近所述嵌入式源极/漏极层;
栅极电极,在所述衬底上以及包括在所述至少两个沟道层之间的所述栅极电极的一部分;
栅极绝缘层,包括在所述嵌入式源极/漏极层与所述栅极电极的在所述至少两个沟道层之间的所述部分之间的第一材料;以及
界面层,包括第二材料,所述界面层在所述嵌入式源极/漏极层与所述至少两个沟道层之间。
19.根据权利要求18所述的半导体装置,其中所述嵌入式源极/漏极层包括衬层以及在所述衬层上的至少一个外延层,
其中所述衬层在所述至少一个外延层与所述栅极绝缘层之间以及所述至少一个外延层与所述界面层之间。
20.根据权利要求18所述的半导体装置,其中所述第一材料不同于所述第二材料,以及
其中所述至少两个沟道层中的第一沟道层的第一长度大于所述至少两个沟道层中的第二沟道层的第二长度。
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US20210091232A1 (en) | 2021-03-25 |
TW201914018A (zh) | 2019-04-01 |
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US10872983B2 (en) | 2020-12-22 |
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US11908952B2 (en) | 2024-02-20 |
US20220310852A1 (en) | 2022-09-29 |
US11393929B2 (en) | 2022-07-19 |
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