CN109301031B - Manufacturing method of N-type double-sided battery - Google Patents
Manufacturing method of N-type double-sided battery Download PDFInfo
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- CN109301031B CN109301031B CN201811062226.9A CN201811062226A CN109301031B CN 109301031 B CN109301031 B CN 109301031B CN 201811062226 A CN201811062226 A CN 201811062226A CN 109301031 B CN109301031 B CN 109301031B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 24
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 18
- 239000011574 phosphorus Substances 0.000 claims abstract description 18
- 230000008569 process Effects 0.000 claims abstract description 13
- 238000005245 sintering Methods 0.000 claims abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052796 boron Inorganic materials 0.000 claims abstract description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000002002 slurry Substances 0.000 claims abstract description 5
- 238000007639 printing Methods 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 230000009467 reduction Effects 0.000 claims description 3
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 229910004205 SiNX Inorganic materials 0.000 claims 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 238000007747 plating Methods 0.000 abstract description 5
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004298 light response Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a manufacturing method of an N-type double-sided battery, which comprises the following steps: s1, removing a damage layer SDE of the silicon wafer; s2, diffusing phosphorus with low surface concentration on the back of the silicon wafer; s3, plating an SINx film outside the PSG layer; s4, texturing the front side of the silicon wafer; s5, carrying out high-temperature long-time propulsion by using a boron expanding pipe; s6, removing the BSG on the front side; s7, generating aluminum oxide ALD and silicon nitride SINx on the front surface; s8, printing and sintering: and selecting the slurry with better contact performance and matching the sintering temperature. The invention reduces the steps of removing PSG and thermal oxidation of the cell, reduces the process flow of the cell, and reduces the required PSG removing machine and thermal oxidation machine, thereby greatly reducing the production cost.
Description
Technical Field
The invention relates to a manufacturing process of an N-type solar cell, in particular to a manufacturing method of an N-type double-sided cell.
Background
P-type crystalline silicon cells currently occupy an absolute share of the market. However, the constant pursuit of increased efficiency and reduced cost is a constant theme of the photovoltaic industry. Compared with the conventional single crystal, the N-type monocrystalline silicon has the advantages of long minority carrier lifetime, small light-induced attenuation and the like, has larger efficiency improvement space, and simultaneously has the advantages of good weak light response, low temperature coefficient and the like. Therefore, the N-type single crystal system has the dual advantages of high power generation amount and high reliability. The manufacturing process of the N-type battery has more procedures than the P-type process, the time is long, the cost is higher, and how to reduce the cost is the key of the production of the N-type battery.
Disclosure of Invention
The invention provides a manufacturing method of an N-type double-sided battery, which has the advantages of less working procedures, short process time and low cost and aims at solving the problems in the background technology.
Technical scheme
The method comprises the following steps:
s1, removing a damage layer of the silicon wafer;
s2, diffusing low-surface-concentration phosphorus on the back of the silicon wafer to generate a PSG layer;
s3, plating an SINx film outside the PSG layer, wherein the thickness of the SINx film is controlled to be 80-90 nm;
s4, texturing the front side of the silicon wafer;
s5, carrying out high-temperature long-time propulsion by using boron pipe expansion, continuously reducing the P content in the PSG layer, and changing the PSG layer into an SIO2 layer;
s6, removing the BSG on the front side;
s7, generating aluminum oxide ALD and silicon nitride SINx on the front surface;
s8, printing and sintering: and selecting the slurry with better contact performance and matching the sintering temperature.
Specifically, in step S1, the thickness is reduced to 8-9um, and the amount of reduction is controlled to 0.45-0.5 g.
In step S2, the silicon wafer back side is subjected to a low surface concentration by reducing the amount of phosphorus source and two-step low temperature deposition, specifically:
the phosphorus source amount was reduced from 188sccm to 100 sccm;
depositing at-750 deg.c for 10 min;
depositing at-780 ℃ for 8 min;
through the operation, the sheet resistance of the generated PSG layer is increased from 80ohm to 95 ohm; and simultaneously the phosphorus content in the PSG is reduced.
Specifically, in step S3, the SINx film is 85nm thick.
Specifically, in step S4, the texturing thinning amount during the texturing process of the front surface of the silicon wafer is controlled to be within 0.3 g.
Specifically, an HF cleaning process is also carried out before the texturing process of the front surface of the silicon wafer, so as to remove the front surface wraparound plating generated during back surface coating and reduce edge electric leakage.
Specifically, in step S5, the high temperature is 1000 ℃ and the long time is 2 hours; through the operation, the phosphorus concentration in the phosphorus-silicon glass PSG is further reduced, the surface concentration of the front surface of the silicon wafer is reduced, the junction depth is increased, and the surface concentration is reduced to 1E19cm-3The junction depth increases to 1.2 um.
Specifically, in step S7, the aluminum oxide ALD has a thickness of 6nm, the front-side silicon nitride SINx has a thickness of 78nm, and the refractive index is 2.07.
The invention has the advantages of
The invention adopts a phosphorus diffusion process with low surface concentration to ensure that the P content on the surface of the silicon wafer and in the PSG is very low, then a layer of SINx film is plated on the PSG, and a boron expansion pipe is used for carrying out high-temperature long-time propulsion to ensure that the P in the PSG is continuously reduced, finally the PSG is changed into an SIO2 layer with extremely low P content, the steps of removing the PSG from the cell and carrying out thermal oxidation are reduced, the process flow of the cell and required PSG removing machines and thermal oxidation machines are reduced, and the production cost is greatly reduced.
Drawings
FIG. 1 is a flow chart of the present invention.
FIG. 2 is a schematic diagram showing the morphology change of a silicon wafer after the steps S2 and S5 according to the present invention.
Detailed Description
The invention is further illustrated by the following examples, without limiting the scope of the invention:
with reference to fig. 1, a method for manufacturing an N-type double-sided battery includes the following steps:
s1, removing a damage layer SDE of the silicon wafer; in the embodiment, the thinning thickness is 8-9um, and the thinning amount is controlled to be 0.45-0.5 g.
S2, diffusing low-surface-concentration phosphorus on the back of the silicon wafer to generate a PSG layer; the silicon wafer back surface adopts the method of reducing the phosphorus source amount and obtaining lower surface concentration through two-step low-temperature deposition, as shown in figure 2, specifically:
the phosphorus source amount was reduced from 188sccm to 100 sccm;
depositing at-750 deg.c for 10 min;
depositing at-780 ℃ for 8 min;
through the operation, the sheet resistance of the generated PSG layer is increased from 80ohm to 95 ohm; and simultaneously the phosphorus content in the PSG is reduced.
S3, plating an SINx film outside the PSG layer, wherein the thickness of the SINx film is controlled to be 80-90 nm; in this example, the thickness of the SINx film was 85 nm.
S4, texturing the front side of the silicon wafer; in the embodiment, the texturing and thinning amount in the texturing process of the front surface of the silicon wafer is controlled within 0.3 g. In other embodiments, an HF cleaning process is also performed before the texturing process of the front surface of the silicon wafer to remove the front surface wraparound plating generated during back surface coating so as to reduce edge leakage.
S5, carrying out high-temperature long-time propulsion by using boron pipe expansion, continuously reducing the P content in the PSG layer, and changing the PSG layer into an SIO2 layer; in the embodiment, the high temperature is 1000 ℃ and the long time is 2 hours; as shown in FIG. 2, by this operation, the phosphorus concentration in the PSG was further reduced, the surface concentration of the front surface of the silicon wafer was increased, and the surface concentration was reduced to 1E19cm-3The junction depth increases to 1.2 um.
S6, removing the BSG on the front side;
s7, generating aluminum oxide ALD and silicon nitride SINx on the front surface; in this example, the thickness of the aluminum oxide ALD is 6nm, the thickness of the front silicon nitride SINx is 78nm, and the refractive index is 2.07.
S8, printing and sintering: selecting slurry with better contact performance and matching the sintering temperature; adopting Helishi 9642 slurry on the front surface, wherein the peak temperature is 780 ℃; the backside was DuPont C7980 with a peak temperature of 780 ℃.
The invention adopts a phosphorus diffusion process with low surface concentration to ensure that the P content on the surface of the silicon wafer and in the PSG is very low, then a layer of SINx film is plated on the PSG, and a boron expansion pipe is used for carrying out high-temperature long-time propulsion to ensure that the P in the PSG is continuously reduced, finally the PSG is changed into an SIO2 layer with extremely low P content, the steps of removing the PSG from the cell and carrying out thermal oxidation are reduced, the process flow of the cell and required PSG removing machines and thermal oxidation machines are reduced, and the production cost is greatly reduced.
The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.
Claims (7)
1. A manufacturing method of an N-type double-sided battery is characterized by comprising the following steps:
s1, removing a damage layer of the silicon wafer;
s2, diffusing low-surface-concentration phosphorus on the back of the silicon wafer to generate a PSG layer; in step S2, the silicon wafer back side is subjected to a low surface concentration by reducing the amount of phosphorus source and two-step low temperature deposition, specifically:
the phosphorus source amount was reduced from 188sccm to 100 sccm;
depositing at-750 deg.c for 10 min;
depositing at-780 ℃ for 8 min;
through the operation, the sheet resistance of the generated PSG layer is increased from 80ohm to 95 ohm; meanwhile, the phosphorus content in the PSG is reduced;
s3, coating a SiNx film outside the PSG layer, wherein the thickness of the SiNx film is controlled to be 80-90 nm;
s4, texturing the front side of the silicon wafer;
s5, carrying out high-temperature long-time propulsion by using boron pipe expansion, continuously reducing the P content in the PSG layer, and changing the PSG layer into an SIO2 layer;
s6, removing the BSG on the front side;
s7, generating aluminum oxide and silicon nitride SiNx by front ALD;
s8, printing and sintering: and selecting the slurry with better contact performance and matching the sintering temperature.
2. The method of claim 1, wherein in step S1, the thickness is reduced to 8-9um, and the amount of reduction is controlled to 0.45-0.5 g.
3. The method as claimed in claim 1, wherein the SiNx film is 85nm thick in step S3.
4. The method of claim 1, wherein in step S4, the texturing reduction during the texturing of the front surface of the silicon wafer is controlled to be within 0.3 g.
5. The method of claim 4, wherein an HF cleaning process is further performed before the texturing process for the front surface of the silicon wafer to remove the front surface wraparound generated during the back surface coating process and reduce edge leakage.
6. The method according to claim 1, wherein in step S5, the elevated temperature is 1000 ℃ and the extended time is 2 hours; through the operation, the phosphorus concentration in the phosphorus-silicon glass PSG is further reduced, the surface concentration of the front surface of the silicon wafer is reduced, the junction depth is increased, and the surface concentration is reduced to 1E19cm-3The junction depth increases to 1.2 um.
7. The method as claimed in claim 1, wherein the alumina thickness is 6nm, the front side silicon nitride SiNx thickness is 78nm, and the refractive index is 2.07 in step S7.
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Effective date of registration: 20230901 Address after: 226000 No. 222 Linyang Road, Nantong Economic and Technological Development Zone, Jiangsu Province Patentee after: Jiangsu Linyang Solar Energy Co.,Ltd. Address before: No. 612, Huashi Road, Huilong Town, Qidong City, Nantong City, Jiangsu Province 226200 Patentee before: JIANGSU LINYANG PHOTOVOLTAIC TECHNOLOGY CO.,LTD. |