CN109219876A - 多列型半导体装置用布线构件及其制造方法 - Google Patents
多列型半导体装置用布线构件及其制造方法 Download PDFInfo
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- CN109219876A CN109219876A CN201780031061.6A CN201780031061A CN109219876A CN 109219876 A CN109219876 A CN 109219876A CN 201780031061 A CN201780031061 A CN 201780031061A CN 109219876 A CN109219876 A CN 109219876A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 308
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 83
- 239000011248 coating agent Substances 0.000 claims abstract description 251
- 238000000576 coating method Methods 0.000 claims abstract description 251
- 239000011347 resin Substances 0.000 claims abstract description 170
- 229920005989 resin Polymers 0.000 claims abstract description 170
- 239000002184 metal Substances 0.000 claims description 89
- 229910052751 metal Inorganic materials 0.000 claims description 89
- 238000005530 etching Methods 0.000 claims description 76
- 238000000034 method Methods 0.000 claims description 39
- 238000007788 roughening Methods 0.000 claims description 16
- 239000003795 chemical substances by application Substances 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 8
- 239000004744 fabric Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 238000007747 plating Methods 0.000 abstract description 50
- 230000006978 adaptation Effects 0.000 abstract description 18
- 239000000758 substrate Substances 0.000 description 76
- 239000010410 layer Substances 0.000 description 69
- 238000007789 sealing Methods 0.000 description 46
- 239000010931 gold Substances 0.000 description 27
- 239000011521 glass Substances 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 12
- 238000009434 installation Methods 0.000 description 11
- 239000010949 copper Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 229910052737 gold Inorganic materials 0.000 description 9
- 238000011161 development Methods 0.000 description 8
- 230000018109 developmental process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 7
- 238000007711 solidification Methods 0.000 description 6
- 230000008023 solidification Effects 0.000 description 6
- 238000010276 construction Methods 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 5
- 238000004090 dissolution Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052763 palladium Inorganic materials 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 239000012530 fluid Substances 0.000 description 4
- 238000010030 laminating Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 230000017260 vegetative to reproductive phase transition of meristem Effects 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000012805 post-processing Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 229940079593 drug Drugs 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- -1 it Afterwards Substances 0.000 description 1
- 210000001503 joint Anatomy 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 229910000029 sodium carbonate Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/561—Batch processing
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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Abstract
本发明提供一种多列型半导体装置用布线构件。利用该多列型半导体装置用布线构件,能够实现半导体装置的薄型化、小型化,使端子部的镀覆膜与树脂之间的密合性提高,使内部端子侧镀层的面和内部端子部的高度均等,减轻树脂的翘曲,削减半导体装置制造时的工序数量,以高可靠性实现成品率良好的量产化。该多列型半导体装置用布线构件是半导体装置用布线构件呈矩阵状排列而成的,该半导体装置用布线构件在树脂层(15)的一个面(15a)上的规定部位以使下表面暴露于面(15a)的状态形成有成为内部端子的镀层(11),并形成有与镀层(11)相连接的成为布线部的镀层(12),以使上表面自树脂层的另一个面(15b)暴露的状态在镀层(12)的区域内局部地形成有成为外部端子的镀层(13),构成内部端子、布线部以及外部端子的镀层的层叠体的侧面形成为大致L字形状,在树脂层的一个面上的、半导体装置用布线构件的集合体的外周区域与树脂层一体地形成有树脂框部(16’)。
Description
技术领域
本发明涉及用于倒装法安装半导体元件的多列型半导体装置用布线构件及其制造方法。
背景技术
以往,在半导体装置用基板之中,例如如下面的专利文献1所记载那样,存在以下类型的半导体装置用基板:在半导体装置用基板上安装半导体元件,利用树脂进行密封,之后,剥下基材,由此完成半导体装置。
对于专利文献1所记载的半导体装置用基板,例如,如图5的(a)所示,在例如由不锈钢材料构成基材51之上具有分别由金属镀层形成的半导体元件搭载部52a和端子部52b。端子部52b形成为内部端子面52b1和外部端子面52b2成为表背一体(日文:表裏一体)那样的形状。
在半导体元件搭载部52a和端子部52b的靠半导体元件搭载侧的部位,在上端周缘形成有大致屋檐形状的突出部52a1、52b3。另外,在半导体元件搭载部52a或端子部52b的靠基材侧的部位,为了能够适当地进行半导体装置安装时的软钎焊,镀敷形成有例如Au等的薄膜作为外部端子面。
并且,在使用图5的(a)的半导体装置用基板来制造半导体装置的过程中,在半导体元件搭载部52a上搭载半导体元件53,利用引线54使半导体元件53的电极和端子部52b相接合,利用树脂来密封搭载有半导体元件53的一侧而形成密封树脂部55,之后,剥下基材51,从而完成半导体装置(参照图5的(b)~图5的(d))。
另外,以往,在半导体装置用基板之中,例如如下面的专利文献2所记载那样,存在以下类型的半导体装置用基板:其是使用于BGA(Ball Grid Array:球栅阵列)构造的半导体装置的半导体装置用基板,在金属板上利用金属镀敷形成有内部端子、外部端子以及布线部。
对于专利文献2所记载的半导体装置用基板,公开了如下的半导体装置用基板:例如,如图6的(a)所示,在构成基材的金属板61上,自金属板侧起形成有具有外部端子部62的外部端子侧镀层,在外部端子侧镀层之上以相同的形状形成有中间层63,并且在中间层63之上以相同的形状形成有具有内部端子部64的内部端子侧镀层。该半导体装置用基板成为如下结构,具有与半导体元件电连接内部端子部64的内部端子侧镀层的面形成为最上表面,自金属板起到最上表面为止的高度在整体上形成为大致相同高度。
专利文献2所记载的半导体装置用基板在制造半导体装置时,以外部端子面与金属板侧的面接触、内部端子面使与金属板相反侧的面暴露的状态进行使用。详细而言,在半导体装置用基板的内部端子面侧,搭载半导体元件65并利用粘接剂层66将半导体元件65固定,利用引线67将半导体元件65的电极和内部端子部64连接起来,之后,利用树脂进行密封而形成密封树脂部68,在利用密封树脂部68进行密封后,利用蚀刻所实现的溶解等方式去除金属板,由此将密封了的树脂的背面设为具有外部端子部62的外部端子侧镀层的面暴露的状态。之后,形成将暴露的外部端子侧镀层的整面覆盖的阻焊层69,形成仅使外部端子部62暴露的开口部70(参照图6的(b)~图6的(e))。然后,将焊球71埋入在开口部70暴露的外部端子部62,使其与外部设备相接合(参照图6的(f))。
现有技术文献
专利文献
专利文献1:日本特开2015-185619号公报
专利文献2:日本特开2009-164594号公报
发明内容
发明要解决的问题
但是,在如专利文献1和专利文献2所记载的半导体装置用基板那样构成的以往的半导体装置用基板中存在如下那样的问题。
即,对于专利文献1所记载的半导体装置用基板,在比半导体元件53的上表面更高的高度方向上需要用于进行将半导体元件53的电极和端子部52b电连接的引线键合的空间,这相应地成为小型化/薄型化的障碍。
另外,专利文献1所记载的半导体装置用基板成为如下结构,即使为了半导体装置的薄型化而倒装法安装半导体元件,端子部52b也形成为内部端子面52b1和外部端子面52b2成为表背一体那样的形状,使内部端子和外部端子在表面和背面的相同位置处发挥功能。因此,内部端子的连接节距由外部端子的连接节距确定,从而与内部端子相连接的半导体元件的小型化受到限制。
另外,对于专利文献1所记载的半导体装置用基板,在该半导体装置用基板上搭载半导体元件53,利用树脂进行密封,之后,剥下基材51,使镀敷形成的半导体元件搭载部52a和端子部52b的面暴露之际,镀覆膜与密封树脂部55之间的密合性和镀覆膜与基材51之间的密合性的相互的平衡存在如下那样的问题。即,专利文献1所记载的半导体装置用基板在镀敷形成的半导体元件搭载部52a和端子部52b的上端周缘形成有大致屋檐形状的突出部52a1、52b1,但由于突出部52a1、52b1的壁厚较薄,因此,突出部52a1、52b1与密封树脂部55之间的密合性较弱,并且容易变形。另一方面,在专利文献1所记载的半导体装置用基板的构成基材51的不锈钢材料的表面上,为了能够适当地进行半导体装置安装时的软钎焊,镀敷形成有例如Au等的薄膜作为半导体元件搭载部52a的外部连接端子面或端子部52b的外部连接端子面,但难以自Au覆膜剥下不锈钢材料。
对于专利文献1所记载的半导体装置用基板,为了使镀覆膜密合于密封树脂部55,镀覆膜需要规定以上的厚度。但是,当使形成半导体元件搭载部52a和端子部52b的镀覆膜较厚时,镀层厚度的偏差也会变大。当镀层厚度的偏差较大时,有可能因倒装法安装时的接合部位的高度的偏差而产生接合不良。
另外,专利文献1所记载的半导体装置用基板以在一侧形成密封树脂部55的方式构成,因此,存在在密封树脂固化后在密封树脂部55产生翘曲的担忧。详细而言,在密封树脂部55与基材51密合的状态下,通过基材51作用有对固化后的密封树脂部55的翘曲进行矫正的力,但在剥离去除基材51后,基材51的矫正力消失,其结果,密封树脂部55容易向规定方向翘曲。
另外,对于专利文献2所记载的半导体装置用基板,也在比半导体元件65的上表面更高的高度方向上需要用于进行将半导体元件65的电极和内部端子部64连接起来的引线键合的空间,这相应地成为小型化/薄型化的障碍。
此外,专利文献2所记载的半导体装置用基板成为如下结构,具有外部端子部62的外部端子侧镀层、中间层63、具有内部端子部64的内部端子侧镀层以相同的形状层叠,在内部端子部64与外部端子部62之间具有布线部,因此,内部端子和外部端子能够根据布线部的设计来调整节距。
但是,对于专利文献2所记载的半导体装置用基板,在半导体装置的制造过程中,形成密封树脂部68,在去除基材之后,内部端子部64和布线部的靠外部端子侧的面暴露,从而容易因氧化而劣化。为了防止布线部的暴露导致的劣化,在溶解去除基材之后,需要为了覆盖暴露的内部端子部64和布线部而涂敷阻焊剂形成覆盖所暴露的靠外部端子侧的整面的阻焊层69,并进行曝光、显影,形成仅使外部端子部62暴露的开口部70。但是,在阻焊剂的显影时,存在水分、药品自外部端子部62与密封树脂部68之间的界面渗入而使半导体装置劣化的担忧。
另外,对于专利文献2所记载的半导体装置用基板,由于具有外部端子部62的外部端子侧镀层、中间层63、具有内部端子部64的内部端子侧镀层以相同的形状层叠,因此与树脂之间的密合性较弱。
另外,当如专利文献2所记载的半导体装置用基板那样从金属板侧形成外部端子侧镀层并在最上层形成内部端子侧镀层时,在实际的生产过程中,镀层厚度会产生偏差,例如在镀层的厚度为约30μm的情况下会产生3μm~7μm这样的高低差,因此,在搭载半导体元件65并进行半导体元件65与内部端子部64之间的电连接时,存在半导体元件65以倾斜的状态进行搭载、在电连接的过程中产生导通不良的担忧。
另外,专利文献2所记载的半导体装置用基板成为设想到在搭载半导体元件65并利用树脂进行密封之后蚀刻去除基材61的结构,但当在组装半导体元件之后蚀刻去除基材61时,存在蚀刻液自端子与树脂之间的界面渗入而使半导体装置65劣化的担忧。
另外,专利文献2所记载的半导体装置用基板也以在一侧形成密封树脂部68的方式构成,因此,存在在密封树脂固化后在密封树脂部68产生翘曲的担忧。详细而言,在密封树脂部68与基材61密合的状态下,通过基材61作用有对固化后的密封树脂部68的翘曲进行矫正的力,但在溶解去除基材61后,基材61的矫正力消失,其结果,密封树脂部68容易向规定方向翘曲。
因此,本申请发明人进行反复试验,结果在导出本发明的前一阶段中想到了如下的半导体装置用布线构件及其制造方法的发明,利用该半导体装置用布线构件,能够使半导体装置薄型化、小型化,使构成端子部的镀覆膜与树脂之间的密合性提高,能够使搭载半导体元件的内部端子侧镀层的面和与半导体元件进行电连接的内部端子部的高度均等,并且在半导体装置的制造工序中能够省略蚀刻去除金属板的工序、形成仅使外部端子部暴露的开口部的工序,能够减轻密封树脂固化后的树脂的翘曲,削减制造半导体装置时的工序数量,能够制造可靠性较高的树脂密封型半导体装置。
并且,本申请发明人进一步进行了探讨、研究,在所想到的前一阶段的半导体装置用布线构件及其制造方法中,发现存在在半导体装置的量产化之际应当改进的课题。
本发明是鉴于这样的问题而做出的,其目的在于提供多列型半导体装置用布线构件及其制造方法,利用该多列型半导体装置用布线构件,能够使半导体装置薄型化、小型化,使构成端子部的镀覆膜与树脂之间的密合性提高,能够使搭载半导体元件的内部端子侧镀层的面和与半导体元件进行电连接的内部端子部的高度均等,并且在半导体装置的制造工序中能够省略蚀刻去除金属板的工序、形成仅使外部端子部暴露的开口部的工序,能够减轻密封树脂固化后的树脂的翘曲,削减半导体装置制造时的工序数量,能够成品率良好地量产可靠性较高的树脂密封型半导体装置。
用于解决问题的方案
为了实现上述目的,本发明提供一种多列型半导体装置用布线构件,其特征在于,该多列型半导体装置用布线构件是半导体装置用布线构件呈矩阵状排列而成的,该半导体装置用布线构件在树脂层的一侧的面上的规定部位以使下表面暴露于该树脂层的一侧的面的状态形成有成为内部端子的第1镀层,并形成有与所述第1镀层相连接的成为布线部的镀层,并且在所述成为布线部的镀层之上以使上表面自所述树脂层的另一侧的面暴露的状态在该成为布线部的镀层的区域内局部地形成有成为外部端子的第2镀层,构成所述内部端子、所述布线部以及所述外部端子的镀层的层叠体的侧面形状形成为大致L字形状或大致T字形状,在所述树脂层的一侧的面上的、各个所述半导体装置用布线构件呈矩阵状排列而成的半导体装置用布线构件的集合体的外周区域与该树脂层一体地形成有树脂框部。
另外,在本发明的多列型半导体装置用布线构件中,优选的是,所述成为布线部的镀层以与所述第1镀层相同的形状形成在该第1镀层之上。
另外,在本发明的多列型半导体装置用布线构件中,优选的是,在所述第1镀层之上形成的所述成为布线部的镀层的上表面是粗化面(日文:粗化面)。若如此设置,则即使第1镀层和成为布线部的镀层是厚度为例如5μm以下较薄的镀层,也能够防止它们从树脂层剥落。
另外,在本发明的多列型半导体装置用布线构件中,优选的是,所述第1镀层所暴露的所述树脂层的一侧的面是粗糙面。
另外,本发明提供一种多列型半导体装置用布线构件的制造方法,该多列型半导体装置用布线构件是半导体装置用布线构件呈矩阵状排列而成的,该多列型半导体装置用布线构件的制造方法的特征在于,包括以下工序:在金属板的另一侧的面上形成在半导体装置用布线构件的集合体的外周区域具有开口部的第1抗蚀剂掩模;自所述金属板的另一侧实施半蚀刻,在自开口部暴露的金属面形成凹部;剥离形成于所述金属板的另一侧的面的第1抗蚀剂掩模;在所述金属板的另一侧的面形成覆盖所述凹部且具有以图案A形成的开口部的第2抗蚀剂掩模;在以所述图案A形成的开口部形成成为内部端子的第1镀层和与所述第1镀层相连接的成为布线部的镀层;剥离形成于所述金属板的另一侧的面的第2抗蚀剂掩模;在所述金属板的另一侧的面形成覆盖所述凹部且具有以图案B形成的开口部的第3抗蚀剂掩模,该具有以图案B形成的开口部的第3抗蚀剂掩模在所述成为布线部的镀层的区域内使所述成为布线部的镀层的一部分暴露;在以所述图案B形成的开口部形成成为外部端子的第2镀层;剥离形成于所述金属板的所述第3抗蚀剂掩模;在所述金属板和所述成为布线部的镀层的未形成有所述第2镀层的部位之上以使该第2镀层的上表面暴露且填埋所述凹部的方式形成树脂层;以及利用蚀刻或剥离来去除所述金属板。
另外,在本发明的多列型半导体装置用布线构件的制造方法中,优选的是,所述成为布线部的镀层以与所述第1镀层相同的形状形成在该第1镀层之上。
另外,在本发明的多列型半导体装置用布线构件的制造方法中,优选的是,在形成所述成为布线部的镀层之后且在形成所述第2抗蚀剂掩模之前,对所述成为布线部的镀层的上表面实施粗化处理或使所述成为布线部的镀层形成为粗化镀层(日文:粗化めっき層)。
另外,在本发明的多列型半导体装置用布线构件的制造方法中,优选的是,该多列型半导体装置用布线构件的制造方法包含以下工序:在剥离形成于所述金属板的另一个面的所述第2抗蚀剂掩模之后,将形成于所述金属板的所述成为布线部的镀层作为掩模对所述金属板表面进行粗化处理。
发明的效果
采用本发明,能够得到多列型半导体装置用布线构件及其制造方法,利用该多列型半导体装置用布线构件,能够使半导体装置薄型化、小型化,使构成端子部的镀覆膜与树脂之间的密合性提高,能够使搭载半导体元件的内部端子侧镀层的面和与半导体元件进行电连接的内部端子部的高度均等,并且在半导体装置的制造工序中能够省略蚀刻去除金属板的工序、形成仅使外部端子部暴露的开口部的工序,能够减轻密封树脂固化后的树脂的翘曲,削减半导体装置制造时的工序数量,能够成品率良好地量产可靠性较高的树脂密封型半导体装置。
附图说明
图1是表示本发明的第1实施方式的多列型半导体装置用布线构件的结构的图,图1的(a)是从外部端子侧看的俯视图,图1的(b)是图1的(a)的局部放大图,图1的(c)是图1的(b)的A-A剖视图,图1的(d)是表示构成图1的(a)的多列型半导体装置用布线构件所具备的各个半导体装置用布线构件中的内部端子、布线部以及外部端子的镀层的层叠体的结构的一个例子的俯视图,图1的(e)是图1的(d)的剖视图。
图2是表示图1所示的多列型半导体装置用布线构件的制造工序的说明图。
图3是表示使用经过图2所示的制造工序制造而得到的第1实施方式的多列型半导体装置用布线构件来制造树脂密封型半导体装置的制造工序的一个例子的说明图。
图4是表示相对于图3所示的制造工序中的各个半导体装置用布线构件倒装法安装半导体元件的形态的图,图4的(a)是从半导体元件搭载侧看的俯视图,图4的(b)是图4的(a)的剖视图。
图5是表示使用以往的半导体装置用基板来制造半导体装置的制造工序的一个例子的说明图。
图6是表示使用以往的半导体装置用基板来制造半导体装置的制造工序的另一个例子的说明图。
图7是表示在导出本发明的前一阶段中想到的与发明有关的半导体装置用布线构件的结构的图,图7的(a)是俯视图,图7的(b)是剖视图。
具体实施方式
在说明实施方式之前,先说明导出本发明的经过和本发明的作用效果。
如上述那样,本申请发明人经过了反复试验,结果在导出本发明的前一阶段中想到了如下的半导体装置用布线构件及其制造方法的发明,利用该半导体装置用布线构件,能够使搭载半导体元件的内部端子面和与半导体元件进行电连接的内部端子部的高度均等,并且在半导体装置的制造工序中能够省略蚀刻去除金属板的工序、形成仅使外部端子部暴露的开口部的工序,从而削减半导体装置制造时的工序数量,能够制造可靠性较高的树脂密封型半导体装置。
在导出本发明的前一阶段中想到的发明
对于与在导出本发明以前想到的发明有关的半导体装置用布线构件,如图7的(b)所示,该半导体装置用布线构件在树脂层15的一侧的面15a上的规定部位以使下表面与树脂层15的一侧的面15a齐平地暴露的状态形成成为内部端子的第1镀层11,在第1镀层11之上以与第1镀层11相同的形状形成成为布线部的镀层12,并且在成为布线部的镀层12之上以使上表面自树脂层15的另一侧的面15b暴露的状态在成为布线部的镀层12的区域内局部地形成成为外部端子的第2镀层13,形成为构成内部端子、布线部以及外部端子的镀层的层叠体的侧面形状呈大致L字形状(或大致T字形状)。
若像图7所示的发明的半导体装置用布线构件那样形成利用布线部将内部端子和外部端子连接起来的镀层的层叠体,则能够根据设计来调整内部端子和外部端子各自的安装节距。
另外,若构成为利用布线部将内部端子和外部端子连接起来的镀层的层叠体的侧面形状呈大致L字形状或大致T字形状,则与树脂之间的密合性得到提高,能够防止形成端子的镀覆膜自树脂脱离。
另外,若设成在成为布线部的镀层12之上使成为外部端子的第2镀层13局部地形成在成为布线部的镀层12的区域内的结构,则能够使成为外部端子的第2镀层13形成得较小,从而能够防止在半导体装置的背面作为外部端子暴露的第2镀层13的脱落、脱离。
另外,若在以往的半导体装置用基板中的与在半导体装置的制造过程中设置的树脂层的开口部相当的部位预先设置与内部端子和布线部厚度不同的外部端子,利用树脂密封内部端子和布线部,仅使外部端子自树脂层的另一侧的面暴露,则与以往的半导体装置用基板不同,不必在半导体装置的制造过程中在与外部构件连接的连接面设置具有开口部的绝缘层,与其相应地,半导体装置的制造时的工序数量减少,生产率得到提高。
详细叙述该点。
本申请发明人进行反复试验,结果想到了使制造半导体装置时所使用的半导体装置用基板中的内部端子和外部端子电连接的连接面与以往的半导体装置用基板相反。
即,对于以往的半导体装置用基板,构成为在制造半导体装置时以外部端子面使金属板侧的面暴露、内部端子面使与金属板相反那一侧的面暴露的状态进行使用。
与此相对,对于图7所示的发明的半导体装置用布线构件,基于在制造半导体装置时以外部端子面使与制造半导体装置用基板时所使用的金属板相反那一侧的面暴露、内部端子面使制造半导体装置用基板时所使用的金属板侧的面暴露的状态进行使用的构思,构成为与构成内部端子和布线部的镀层相比使构成外部端子的镀层自制造半导体装置用基板时所使用的金属板的高度较高。
例如,当利用蚀刻所实现的溶解等方式去除在制造图7所示的发明的半导体装置用布线构件时使用的金属板时,在去除金属板之后,成为内部端子的第1镀层11的在去除了金属板的一侧的面以与金属板的表面平齐没有高度差(高低差为1μm以下)的状态暴露。该金属板是引线框等所使用的通常的轧制材料。
在此,与采用以往的半导体装置用基板的半导体装置同样地,在第1镀层11上搭载半导体元件,但由于第1镀层11的面以没有高度差的状态暴露,因此,连接面整体平坦,因此连接稳定。
在这种情况下,外部端子需要使与金属板侧相反那一侧的面暴露。因此,本申请发明人想到了通过以下方式得到的图7所示的发明的半导体装置用布线构件:在对金属板上的成为内部端子、外部端子以及布线部的部位实施了镀敷之后,与以往的半导体装置用基板不同,还仅在成为外部端子的部位进一步追加实施镀敷,从而形成有与内部端子、布线部存在高低差的外部端子,并且在未形成有第2镀层的部位之上以使第2镀层的上表面暴露的状态形成树脂层,并蚀刻去除了金属板。
若像图7所示的发明的半导体装置用布线构件那样,在外部端子与内部端子、布线部之间设置高低差,利用树脂仅密封内部端子和布线部,将仅使外部端子暴露的面设于树脂层的另一侧的面,则与以往的半导体装置用基板不同,在半导体装置的制造工序中不需要蚀刻去除金属板、在与外部构件连接的连接面形成开口部的加工,与其相应地,工序数量减少,生产率得到提高。
另外,若像图7所示的发明的半导体装置用布线构件那样构成,则成为仅由层叠镀覆膜和树脂构成的构造,在倒装法安装后进行树脂密封之际,利用密封树脂仅密封半导体装置用布线构件的树脂层和暴露的镀覆膜,而未对膨胀系数大不相同的基材(金属板)的表面进行树脂密封,因此,能够减轻密封树脂的固化后的翘曲。详细而言,与向构成基材的金属板进行的树脂密封相比,对于向树脂层进行的树脂密封,由于树脂层和密封树脂这两者是物理特性为同系统的材料,因此密封树脂固化后的热收缩、热膨胀变小。并且,未如专利文献1、2所记载的半导体装置用基板那样在形成密封树脂部之后去除基材。其结果,密封树脂的固化后的翘曲变小。
另外,采用图7所示的发明的半导体装置用布线构件,在半导体装置的制造工序中不需要蚀刻去除构成基材的金属板、用于在与外部设备连接的连接面形成开口部的加工(阻焊剂的涂敷、曝光、显影),因此,不存在水分、药液渗入而使半导体装置劣化的担忧。
在导出本发明以前想到的发明中的课题
本申请发明人进一步进行了探讨、研究,对于图7所示的发明的半导体装置用布线构件,发现为了应对量产化的要求而存在如下那样的课题。
即,对于这种在半导体装置的制造过程中使用的半导体装置用布线构件,为了一次获得许多半导体装置,形成将具有内部端子部、外部端子部以及布线部的各个半导体装置用布线构件呈矩阵状排列而成的多列型半导体装置用布线构件。
然而,图7所示的半导体装置用布线构件成为如下结构,内部端子、布线部以及外部端子由镀层11、12、13形成,内部端子、布线部以及外部端子被树脂层15固定,整体上形成为薄板状。在使这样的薄板状的半导体装置用布线构件进一步形成为呈矩阵状进行多列化而成的形态的情况下,相对于树脂层的厚度,半导体装置用布线构件的集合体的面积非常大,因此,半导体装置用布线构件的集合体的面整体容易产生挠曲,有可能对半导体装置的制造造成不良影响。例如,在为了在层叠镀覆膜埋设于树脂层的状态下进行倒装法安装工序而对构成多列型半导体装置用基板的集合体的片材进行输送的情况下,作为半导体元件搭载用片材,由于其强度较弱,因此有可能因输送而变形。
本发明的作用效果
因此,本申请发明人鉴于图7所示的发明中的上述课题而进行了进一步的探讨、研究、反复试验,其结果,想到了能维持图7所示的发明的上述效果且能解决上述课题的本发明。
本发明的多列型半导体装置用布线构件是图7所示的发明的半导体装置用布线构件呈矩阵状排列而成的多列型半导体装置用布线构件,在树脂层的一侧的面上的由各个半导体装置用布线构件呈矩阵状排列而成的半导体装置用布线构件的集合体的外周区域与树脂层一体地形成有树脂框部。
若像本发明的多列型半导体装置用布线构件那样在树脂层的一侧的面上的半导体装置用布线构件的集合体的外周区域与树脂层一体地形成树脂框部,则多列型半导体装置用布线构件被树脂框部加强,能够确保即使进行输送也不易变形的强度。
此外,半导体装置用布线构件的集合体的成为树脂框部的形成对象的部位既可以是多列型半导体装置用布线构件的全部区域(1张片材),也可以是在将多列型半导体装置用布线构件的全部区域分成多个区块时的各个区块。
此外,在本发明的多列型半导体装置用布线构件中,优选的是,在第1镀层之上形成的成为布线部的镀层的上表面是粗化面。
若如此设置,则成为布线部的镀层中的未被第2镀层覆盖的部位的与树脂层之间的密合性得到提高。于是,即使第1镀层和成为布线部的镀层是厚度为例如5μm以下较薄的镀层,也能够防止它们从树脂层剥落。
另外,在本发明的多列型半导体装置用布线构件中,优选的是,第1镀层所暴露的树脂层的一侧的面是粗糙面。
若如此设置,则与在搭载半导体元件时使用的粘接剂层之间的密合性、与在搭载半导体元件搭载之后进行密封的密封树脂之间的密合性得到提高。
其他结构和作用效果与图7所示的发明的半导体装置用布线构件大致相同。
此外,本发明的多列型半导体装置用布线构件能够通过具有以下工序来制造:在金属板的另一侧的面上形成在半导体装置用布线构件的集合体的外周区域具有开口部的第1抗蚀剂掩模,且形成覆盖金属板的一侧的整面的第1抗蚀剂掩模;自金属板的另一侧实施半蚀刻,在自开口部暴露的金属面形成凹部;剥离形成于金属板的另一侧的面的第1抗蚀剂掩模;在金属板的另一侧的面形成覆盖凹部且具有以图案A形成的开口部的第2抗蚀剂掩模;在以图案A形成的开口部形成成为内部端子的第1镀层和与第1镀层相连接的成为布线部的镀层;剥离形成于金属板的另一侧的面的第2抗蚀剂掩模;在金属板的另一侧的面形成覆盖凹部且具有以图案B形成的开口部的第3抗蚀剂掩模,该具有以图案B形成的开口部的第3抗蚀剂掩模在成为布线部的镀层的区域内使成为布线部的镀层的一部分暴露;在以图案B形成的开口部形成成为外部端子的第2镀层;剥离在金属板的两面形成的第3抗蚀剂掩模和第1抗蚀剂掩模;在金属板和成为布线部的镀层的未形成有第2镀层的部位之上以使第2镀层的上表面暴露且填埋凹部的方式形成树脂层;以及利用蚀刻或剥离来去除金属板。
此外,优选的是,成为布线部的镀层以与第1镀层相同的形状形成在第1镀层之上。
若如此设置,则能够使成为内部端子的面较大,因此能够适应搭载电极的节距不同的、更多的半导体元件。
另外,优选的是,在形成成为布线部的镀层之后且在形成第2抗蚀剂掩模之前,对成为布线部的镀层的上表面实施粗化处理或使成为布线部的镀层形成为粗化镀层。
若如此设置,则成为布线部的镀层中的未被第2镀层覆盖的部位的与树脂层之间的密合性得到提高。于是,即使第1镀层和成为布线部的镀层是厚度为例如5μm以下较薄的镀层,也能够防止它们从树脂层剥落。
另外,优选的是,包含以下工序:在剥离形成于金属板的另一个面的第2抗蚀剂掩模之后,将形成于金属板的成为布线部的镀层作为掩模对金属板表面进行粗化处理。
若如此设置,则在去除了金属板时,树脂层的一侧的面成为粗糙面并暴露,因此,与在搭载半导体元件时使用的粘接剂层之间的密合性、与在搭载半导体元件搭载之后进行密封的密封树脂之间的密合性得到提高。
因而,采用本发明,能够得到如下的多列型半导体装置用布线构件及其制造方法,利用该多列型半导体装置用布线构件,能够使半导体装置薄型化、小型化,使构成端子部的镀覆膜与树脂之间的密合性提高,能够使搭载半导体元件的内部端子面和与半导体元件进行电连接的内部端子部的高度均等,并且在半导体装置的制造工序中能够省略蚀刻去除金属板的工序、形成仅使外部端子部暴露的开口部的工序,能够减轻密封树脂固化后的树脂的翘曲,削减半导体装置制造时的工序数量,能够成品率良好地量产可靠性较高的树脂密封型半导体装置。
以下,使用附图来说明本发明的实施方式。
第1实施方式
图1是表示本发明的第1实施方式的多列型半导体装置用布线构件的结构的图,图1的(a)是从外部端子侧看的俯视图,图1的(b)是图1的(a)的局部放大图,图1的(c)是图1的(b)的A-A剖视图,图1的(d)是表示构成图1的(a)的多列型半导体装置用布线构件所具备的各个半导体装置用布线构件中的内部端子、布线部以及外部端子的镀层的层叠体的结构的一个例子的俯视图,图1的(e)是图1的(d)的剖视图。图2是表示图1所示的多列型半导体装置用布线构件的制造工序的说明图。图3是表示使用经过图2所示的制造工序制造而得到的第1实施方式的多列型半导体装置用布线构件来制造树脂密封型半导体装置的制造工序的一个例子的说明图。图4是表示相对于图3所示的制造工序中的各个半导体装置用布线构件倒装法安装半导体元件的形态的图,图4的(a)是从半导体元件搭载侧看的俯视图,图4的(b)是图4的(a)的剖视图。
如图1的(a)所示,第1实施方式的多列型半导体装置用布线构件具有呈矩阵状排列的半导体装置用布线构件10的集合体和树脂框部16’。
如图1的(c)所示,各个半导体装置用布线构件10构成为具有树脂层15、成为内部端子的第1镀层11、成为布线构件的镀层12以及成为外部端子的镀层13。
成为内部端子的第1镀层11以使下表面与树脂层15的一侧的面15a齐平地暴露的状态形成在树脂层15的一侧的面15a上的规定部位。
成为布线部的镀层12以与第1镀层11相同的形状形成在第1镀层11之上。
另外,成为布线部的镀层12的上表面成为粗化面。另外,第1镀层11所暴露的树脂层15的一侧的面成为粗糙面。
在成为布线部的镀层12之上,成为外部端子的第2镀层13以使上表面自树脂层15的另一侧的面15b暴露的状态局部地(例如距成为布线部的镀层12的外缘0.03mm以上的内侧)形成在成为布线部的镀层12的区域内。
此外,第1镀层11例如由依次层叠的Au镀层、Pd镀层以及Ni镀层构成。
成为布线部的镀层12例如由Ni镀层或Cu镀层构成。
第2镀层13例如由依次层叠的Ni镀层、Pd镀层以及Au镀层构成。
第2镀层13的表面(即Au镀层的表面)距树脂层15的一侧的面15a的高度H2高于成为布线部的镀层12的表面距树脂层15的一侧的面15a的高度H1。
并且,成为内部端子的镀层11和成为布线部的镀层12以及成为外部端子的镀层13的层叠体的侧面形状形成为大致L字形状(或如图1的(e)所示的那样形成为大致T字形状)。
树脂框部16’与树脂层15一体地形成于半导体装置用布线构件10的集合体的外周区域的树脂层15的一侧的面15a侧。
例如能够如下那样地制造这样构成的第1实施方式的多列型半导体装置用布线构件。另外,为了方便,对于在制造的各工序中实施的包含药液清洗、水清洗等在内的前处理、后处理等,省略说明。另外,在图2中,为了方便,示出了在一个半导体装置用布线构件的两侧形成树脂框部。
首先,在图2的(a)所示的成为基板的金属板1的两面层压抗蚀剂掩模用的干膜抗蚀剂R(参照图2的(b))。
接着,对于表面侧的干膜抗蚀剂R,使用形成有用于在半导体装置用布线构件的集合体的外周区域形成开口部的图案的玻璃掩模将表面侧曝光、显影,并且对于背面侧的干膜抗蚀剂R,使用照射整面的玻璃掩模将背面侧曝光、显影。然后,如图2的(c)所示,在表面形成在半导体装置用布线构件的集合体的外周区域具有开口部的第1抗蚀剂掩模,在背面形成覆盖整面的第1抗蚀剂掩模。另外,利用以往公知的方法进行曝光、显影。例如,通过在用玻璃掩模覆盖的状态下照射紫外线,使干膜抗蚀剂的被通过了玻璃掩模的紫外线照射到的部位相对于显影液的溶解性下降,去除除此之外的部分,从而形成抗蚀剂掩模。另外,在此使用负型的干膜抗蚀剂作为抗蚀剂,但是抗蚀剂掩模的形成也可以使用负型的液态抗蚀剂。此外,也可以通过使用正型的干膜抗蚀剂或者液态抗蚀剂使抗蚀剂的被通过了玻璃掩模的紫外线照射到的部分相对于显影液的溶解性增大,去除该部分,从而形成抗蚀剂掩模。
接着,自金属板的表面侧实施半蚀刻,在自开口部暴露的金属面形成凹部1a(参照图2的(d))。
接着,剥离表侧的面的第1抗蚀剂掩模(参照图2的(e))。然后,在剥离后的表侧的面层压干膜抗蚀剂R2(参照图2的(f))。
接着,对于表面侧的干膜抗蚀剂R2,使用覆盖凹部且形成有用于在规定位置形成内部端子、布线部以及外部端子的基部的图案(在此设为图案A)的玻璃掩模将表面侧曝光、显影,形成图案A的抗蚀剂掩模作为第2抗蚀剂掩模(参照图2的(g))。
接着,在金属板的自第2抗蚀剂掩模暴露的部位,例如按照Au镀层、Pd镀层的顺序以分别成为规定的厚度(例如0.003μm的Au镀层、0.03μm的Pd镀层)的方式分别实施镀Au、镀Pd,作为第1镀层11。
接着,在Pd镀层上,例如以Ni镀层(或Cu镀层)形成为与第1镀层的平面形状相同的形状的方式实施例如4μm左右的镀Ni(或镀Cu),作为成为布线部的镀层12。另外,优选的是,对于成为布线部的Ni镀层(或Cu镀层)实施粗化处理。图2的(h)示出此时的状态。
此外,将由第1镀层11和成为布线部的镀层12层叠而成的镀层的总厚度控制在5μm以下。当形成为超过5μm的镀层厚度时,在以覆盖第1镀层11和成为布线部的镀层12的方式形成用于形成后述的第2镀层的第3抗蚀剂掩模之际,第3抗蚀剂掩模会自金属板过度地突出,因此,空气容易进入第2抗蚀剂掩模的内部,故此并不理想。
另外,在形成Ni镀层作为成为布线部的镀层12的情况下,针对Ni镀层的粗化处理是通过对Ni镀层的表面实施蚀刻来进行的。另外,在形成Cu镀层作为成为布线部的镀层12的情况下,针对Cu镀层的粗化处理是通过对Cu镀层的表面实施阳极氧化处理或蚀刻来进行的。
另外,作为构成第1镀层11的半导体元件搭载面侧(即,最接近金属板的一侧)的镀层的金属,能够从Ni、Pd、Au、Ag、Sn、Cu等中适宜选择倒装法连接所需的种类。
接着,剥离表侧的面的第2抗蚀剂掩模(参照图2的(i))。然后,在剥离后的表侧的面层压干膜抗蚀剂R3(参照图2的(j))。此外,优选的是,在剥离形成于金属板的表侧的面的第2抗蚀剂掩模之后且在层压干膜抗蚀剂R3之前,将形成于金属板的成为布线部的镀层12作为掩模对金属板表面进行粗化处理。
接着,使用覆盖凹部且形成有用于在率先形成的成为布线部的镀层的区域内的一部分中的之后成为外部端子的部位叠合地形成镀层的图案(在此设为图案B)的玻璃掩模将表面侧曝光、显影,并形成图案B的抗蚀剂掩模作为第3抗蚀剂掩模(参照图2的(k))。
接着,在自第3抗蚀剂掩模暴露的、构成成为布线部的镀层12的Ni镀层(或Cu镀层)的表面,例如按照Ni镀层、Pd镀层、Au镀层的顺序以分别成为规定的厚度且使最上层的镀层(Au镀层)的面为第3抗蚀剂掩模的面的高度以下的方式分别实施镀Ni、镀Pd、镀Au,作为第2镀层13。图2的(l)示出此时的状态。优选的是,以使最上层的镀层的面比第3抗蚀剂掩模的面低3μm~13μm这样而形成有凹部的方式实施各个镀敷。当如此设置时,在搭载半导体装置之后与外部设备进行软钎焊连接之际,软钎料容易滞留于凹部,从而能够防止软钎料渗出。Ni镀层形成为例如20μm~50μm的厚度。此外,也可以在不设置Ni镀层的情况下,按照Pd镀层、Au镀层的顺序以分别成为规定的厚度的方式分别实施镀Pd、镀Au。另外,作为构成第2镀层13中的成为外部端子接合面的镀层的金属,能够从Ni、Pd、Au、Sn等中适宜选择能够与外部基材软钎焊连接的种类。
接着,剥离两面的抗蚀剂掩模(参照图2的(m))。
接着,在金属板上的与内部端子、布线部、外部端子相对应的各镀层突出的一侧,以使成为外部端子的第2镀层13的表面暴露的方式利用树脂密封凹部1a、其他的部位(参照图2的(n))。在树脂密封时,有时会由端子图案的镀敷形成的端子高度的不均导致树脂蔓延到外部端子面。在这种情况下,研磨密封的树脂的表面并使外部端子面暴露。
接着,通过实施蚀刻,将金属板溶解等方式,或者,通过剥下金属板,来去除金属板,如图2的(o)所示,使成为内部端子的第1镀层11的表面自树脂层15的面15a与面15a齐平地暴露,且在半导体装置用布线构件的集合体的外周与树脂层15一体地形成树脂框部16’。由此,完成了本实施方式的多列型半导体装置用布线构件。
如下那样地使用这样制造成的第1实施方式的半导体装置用布线构件来制造半导体装置。图3是表示使用经过图2所示的制造工序制造而得到的第1实施方式的多列型半导体装置用布线构件来制造树脂密封型半导体装置的制造工序的一个例子的说明图。图4是表示相对于图3所示的制造工序中的各个半导体装置用布线构件倒装法安装半导体元件的形态的图,图4的(a)是从半导体元件搭载侧看的俯视图,图4的(b)是图4的(a)的剖视图。
首先,将半导体元件20搭载在图3的(a)所示的半导体装置用布线构件的内部端子面侧,借助焊球14使半导体元件20的电极与自树脂面15a与树脂面15a齐平地暴露的内部端子相连接(参照图3的(b)、图4的(a)、图4的(b))。此外,在第1实施方式的半导体装置用布线构件中,由于暴露的内部端子的表面与树脂面15a齐平,因此能够以稳定的状态搭载半导体元件20。
接着,利用规定的密封材料17来密封借助焊球14连接的半导体元件20的靠内部端子侧的间隙(参照图3的(c))。
接着,利用密封树脂18密封搭载有半导体元件20的面(参照图3的(d))。
接着,将各个半导体装置区域切断(参照图3的(e))。
由此,完成了半导体装置。此外,在图3的(a)~图3的(e)中,以不改变半导体装置用布线构件的上下方向的方式进行图示。
将完成的半导体装置搭载于外部构件。在这种情况下,由于仅外部端子自树脂暴露,因而能够容易地与设于外部构件的连接用端子相连接。
采用第1实施方式的多列型半导体装置用布线构件,在树脂层15的一侧的面15a上的半导体装置用布线构件的集合体的外周区域与树脂层15一体地形成了树脂框部16’,因此,多列型半导体装置用布线构件被树脂框部16’加强,能够确保即使进行输送也不易变形的强度。
另外,采用第1实施方式的多列型半导体装置用布线构件,各个半导体装置用布线构件形成有利用布线部将内部端子和外部端子连接起来的镀层11、12、13的层叠体,因此,能够根据设计来调整内部端子和外部端子各自的安装节距。
另外,采用第1实施方式的多列型半导体装置用布线构件,构成为利用布线部将内部端子和外部端子连接起来的镀层11、12、13的层叠体的侧面形状呈大致L字形状或大致T字形状,因此,与树脂15之间的密合性得到提高,能够防止形成端子的镀覆膜自树脂脱离。
另外,采用第1实施方式的多列型半导体装置用布线构件,设成在成为布线部的镀层12之上使成为外部端子的第2镀层13局部地形成在成为布线部的镀层12的区域内的结构,因此,能够使成为外部端子的第2镀层13形成得较小,从而能够防止在半导体装置的背面作为外部端子暴露的第2镀层13的脱落、脱离。
另外,采用第1实施方式的多列型半导体装置用布线构件,在如图1的(d)所示那样形成为整体为相同宽度的矩形形状的情况下,能够使成为内部端子的面较大,因此,能够适应搭载电极的节距不同的、更多的半导体元件。
另外,采用第1实施方式的多列型半导体装置用布线构件,预先设置与内部端子和布线部厚度不同的外部端子,利用树脂密封内部端子和布线部,仅使外部端子自树脂层的另一侧的面暴露,因此,与以往的半导体装置用基板不同,不必在半导体装置的制造过程中蚀刻去除金属板、在与外部构件连接的连接面设置具有开口部的绝缘层,与其相应地,半导体装置的制造时的工序数量减少,生产率得到提高。
另外,采用第1实施方式的多列型半导体装置用布线构件,成为仅由层叠镀覆膜和树脂构成的构造,在倒装法安装后进行树脂密封之际,利用密封树脂18仅密封半导体装置用布线构件的树脂层15和暴露的镀覆膜,而未对膨胀系数大不相同的基材(金属板)的表面进行树脂密封,因此,能够减轻密封树脂18的固化后的翘曲。详细而言,与向构成基材的金属板进行的树脂密封相比,对于向树脂层进行树脂密封,由于树脂层和密封树脂这两者是物理特性为同系统的材料,因此密封树脂固化后的热收缩、热膨胀变小。并且,未如专利文献1、2所记载的半导体装置用基板那样在形成密封树脂部之后去除基材。其结果,密封树脂的固化后的翘曲变小。
另外,采用第1实施方式的多列型半导体装置用布线构件,在半导体装置的制造工序中不需要蚀刻去除构成基材的金属板、用于在与外部设备连接的连接面形成开口部的加工(阻焊剂的涂敷、曝光、显影),因此,不存在水分、药液渗入而使半导体装置劣化的担忧。
因而,采用第1实施方式的多列型半导体装置用布线构件及其制造方法,能够使半导体装置薄型化、小型化,使构成端子部的镀覆膜与树脂之间的密合性提高,能够使搭载半导体元件的内部端子面和与半导体元件进行电连接的内部端子部的高度均等,并且在半导体装置的制造工序中能够省略蚀刻去除金属板的工序、形成仅使外部端子部暴露的开口部的工序,能够减轻密封树脂固化后的树脂的翘曲,削减半导体装置制造时的工序数量,能够成品率良好地量产可靠性较高的树脂密封型半导体装置。
实施例
接着,说明本发明的多列型半导体装置用布线构件及其制造方法的实施例。
另外,在各工序中实施包含药液清洗、水清洗等在内的前处理、后处理是通常的处理,因此省略记载。
首先,作为金属板1,准备了也可用作引线框材料的板厚0.15mm的铜材(参照图2的(a))。
在第1抗蚀剂掩模形成工序中,在金属板1的两面层压有厚度25μm的干膜抗蚀剂R(参照图2的(b))。
接着,在表面侧使用形成有用于在半导体装置用布线构件的集合体的外周区域形成开口部的图案的玻璃掩模对表面侧的干膜抗蚀剂R进行曝光、显影,形成了在半导体装置用布线构件的集合体的外周区域具有开口部的第1抗蚀剂掩模。对于背面侧的干膜抗蚀剂R,使用照射整面的玻璃掩模对背面侧进行曝光、显影,形成了覆盖整面的第1抗蚀剂掩模。该曝光、显影与以往的加工方法同样,通过使曝光用的玻璃掩模密合于干膜抗蚀剂R并照射紫外线,从而将各个图案曝光于干膜抗蚀剂R,利用碳酸钠进行了显影(参照图2的(c))。
接着,自金属板的表面侧实施半蚀刻,在自开口部暴露的金属面形成了凹部1a(参照图2的(d))。
接着,剥离表侧的面的第1抗蚀剂掩模(参照图2的(e)),在剥离后的表侧的面层压干膜抗蚀剂R2(参照图2的(f))。
接着,在表面侧使用覆盖凹部且形成有用于在规定位置形成镀层的图案A的玻璃掩模对表面侧的干膜抗蚀剂R进行曝光、显影,形成了使之后形成镀层的部分开口的第2抗蚀剂掩模(参照图2的(g))。
在接下来的镀敷工序中,在对自形成于表侧的面的第2抗蚀剂掩模暴露的金属板进行了通常的镀敷前处理之后,按照镀Au、镀Pd、镀Ni的顺序以Au为0.01μm、Pd为0.03μm、Ni为4.0μm的方式实施了镀敷(参照图2的(h))。
接着,剥离表侧的面的第2抗蚀剂掩模(参照图2的(i)),在表侧的面层压干膜抗蚀剂R3(参照图2的(j))。此时,需要与之后形成的第2金属镀层的厚度相应地选定抗蚀剂的厚度,在本实施例中,将第2金属镀层形成为15μm~40μm,因此,以使最上层的镀层的面为第3抗蚀剂掩模的面的高度以下的方式仅表面侧使用厚度为50μm的抗蚀层,背面侧使用厚度为25μm的抗蚀层。
然后,使用形成有用于在率先形成的镀层的一部分且是之后成为外部端子的部分叠合地形成镀层的图案B的玻璃掩模进行曝光、显影,形成了第3抗蚀剂掩模(参照图2的(k))。
在接下来的镀敷工序中,在自形成的抗蚀剂掩模暴露的镀Ni面,按照镀Ni、镀Pd、镀Au的顺序以Ni为20.0μm、Pd为0.03μm、Au为0.01μm的方式实施镀敷(参照图2的(l)),接着去除了两面的抗蚀剂掩模(参照图2的(m))。
接着,在金属板的与内部端子、布线部、外部端子相对应的各镀层突出的一侧,以使成为外部端子的第2镀层13的表面暴露的方式利用树脂密封凹部1a、其他的部位(参照图2的(n))。
接着,蚀刻去除金属板,从而制作出在半导体装置用布线构件的集合体的外周形成了树脂框部16’的多列型半导体装置用布线构件(参照图2的(o))。
将完成的多列型半导体装置用布线构件的由树脂15固定的镀层作为布线,在与金属板接触的面侧搭载半导体元件并与内部端子实现导通(参照图3的(b)),利用密封树脂18密封半导体元件搭载部(参照图3的(d)),切断各个半导体装置区域,从而得到外部端子的表面自树脂15的面暴露的状态的半导体装置(参照图3的(e))。
以上,说明了本发明的多列型半导体装置用布线构件的实施方式和实施例,但本发明的多列型半导体装置用布线构件并不限定于上述实施方式和实施例的结构。
例如,在第1实施方式的多列型半导体装置用布线构件中,第1镀层使用Au、Pd,成为布线部的镀层即金属镀层使用Ni,第2镀层使用Ni、Pd、Au,但本发明的多列型半导体装置用布线构件的形成第1镀层、成为布线部的镀层、第2镀层所使用的镀层的组合并不限定于此,作为变形例,也可以将实施了以下的表1所示的镀敷的第1镀层、成为布线部的镀层、第2镀层组合起来,构成本发明的多列型半导体装置用布线构件。另外,在表1中,以在各变形例中从栏的上方依次实施镀敷的方式进行了表示。
表1 构成半导体装置用布线构件的镀层的组合
产业上的可利用性
本发明的多列型半导体装置用布线构件在需要组装表面安装型的密封树脂型半导体装置的领域中是有用的。
附图标记说明
1、金属板(基材);10、半导体装置用布线构件;11、第1镀层;12、成为布线部的镀层;13、第2镀层;14、焊球;15、树脂层;15a、树脂层的一侧的面;15b、树脂层的另一侧的面;16’、树脂框部;17、密封材料;18、密封树脂;20、半导体元件。
Claims (8)
1.一种多列型半导体装置用布线构件,其特征在于,
该多列型半导体装置用布线构件是半导体装置用布线构件呈矩阵状排列而成的,该半导体装置用布线构件在树脂层的一侧的面上的规定部位以使下表面暴露于该树脂层的一侧的面的状态形成有成为内部端子的第1镀层,并形成有与所述第1镀层相连接的成为布线部的镀层,并且在所述成为布线部的镀层之上以使上表面自所述树脂层的另一侧的面暴露的状态在该成为布线部的镀层的区域内局部地形成有成为外部端子的第2镀层,构成所述内部端子、所述布线部以及所述外部端子的镀层的层叠体的侧面形状形成为大致L字形状或大致T字形状,
在所述树脂层的一侧的面上的、各个所述半导体装置用布线构件呈矩阵状排列而成的半导体装置用布线构件的集合体的外周区域与该树脂层一体地形成有树脂框部。
2.根据权利要求1所述的多列型半导体装置用布线构件,其特征在于,
所述成为布线部的镀层以与所述第1镀层相同的形状形成在该第1镀层之上。
3.根据权利要求1或2所述的多列型半导体装置用布线构件,其特征在于,
在所述第1镀层之上形成的所述成为布线部的镀层的上表面是粗化面。
4.根据权利要求1或2所述的多列型半导体装置用布线构件,其特征在于,
所述第1镀层所暴露的所述树脂层的一侧的面是粗糙面。
5.一种多列型半导体装置用布线构件的制造方法,该多列型半导体装置用布线构件是半导体装置用布线构件呈矩阵状排列而成的,该多列型半导体装置用布线构件的制造方法的特征在于,包括以下工序:
在金属板的另一侧的面上形成在半导体装置用布线构件的集合体的外周区域具有开口部的第1抗蚀剂掩模;
自所述金属板的另一侧实施半蚀刻,在自开口部暴露的金属面形成凹部;
剥离形成于所述金属板的另一侧的面的第1抗蚀剂掩模;
在所述金属板的另一侧的面形成覆盖所述凹部且具有以图案A形成的开口部的第2抗蚀剂掩模;
在以所述图案A形成的开口部形成成为内部端子的第1镀层和与所述第1镀层相连接的成为布线部的镀层;
剥离形成于所述金属板的另一侧的面的第2抗蚀剂掩模;
在所述金属板的另一侧的面形成覆盖所述凹部且具有以图案B形成的开口部的第3抗蚀剂掩模,该具有以图案B形成的开口部的第3抗蚀剂掩模在所述成为布线部的镀层的区域内使所述成为布线部的镀层的一部分暴露;
在以所述图案B形成的开口部形成成为外部端子的第2镀层;
剥离形成于所述金属板的所述第3抗蚀剂掩模;
在所述金属板和所述成为布线部的镀层的未形成有所述第2镀层的部位之上以使该第2镀层的上表面暴露且填埋所述凹部的方式形成树脂层;以及去除所述金属板。
6.根据权利要求5所述的多列型半导体装置用布线构件的制造方法,其特征在于,
所述成为布线部的镀层以与所述第1镀层相同的形状形成在该第1镀层之上。
7.根据权利要求5或6所述的多列型半导体装置用布线构件的制造方法,其特征在于,
在形成所述成为布线部的镀层之后且在形成所述第2抗蚀剂掩模之前,对所述成为布线部的镀层的上表面实施粗化处理或使所述成为布线部的镀层形成为粗化镀层。
8.根据权利要求5所述的多列型半导体装置用布线构件的制造方法,其特征在于,
该多列型半导体装置用布线构件的制造方法包含以下工序:在剥离形成于所述金属板的另一个面的所述第2抗蚀剂掩模之后,将形成于所述金属板的所述成为布线部的镀层作为掩模对所述金属板表面进行粗化处理。
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