CN109148398A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN109148398A
CN109148398A CN201810577543.8A CN201810577543A CN109148398A CN 109148398 A CN109148398 A CN 109148398A CN 201810577543 A CN201810577543 A CN 201810577543A CN 109148398 A CN109148398 A CN 109148398A
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China
Prior art keywords
electrode
semiconductor
pattern
semiconductor chip
hole
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Granted
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CN201810577543.8A
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CN109148398B (zh
Inventor
郑祥楠
金逸俊
姜善远
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

公开了一种半导体封装，包括：半导体芯片；在半导体芯片上的第一外部电容器，包括第一电极和第二电极；在半导体芯片上的第二外部电容器，包括第一电极图案和第二电极图案；以及在半导体芯片上的导电图案，电连接到第一外部电容器的第一电极和第二外部电容器的第一电极图案。第一外部电容器的第二电极与第二外部电容器的第二电极图案绝缘。

Description

半导体封装
相关申请的交叉引用
本申请要求于2017年6月19日提交的韩国专利申请No.10-2017-0077432的优先权，其全部内容通过引用并入本文。
技术领域
本发明构思的实施例涉及半导体封装，更具体地涉及包括电容器的半导体封装。
背景技术
对于半导体器件的高集成度，已经提出了一种用于堆叠多个半导体芯片的方法，其中多芯片封装具有安装在单个半导体封装中的多个半导体芯片或者堆叠的不同芯片作为一个系统操作的系统级封装。对于高性能半导体器件，需要增强电源完整性。可以通过分析期望的电源/电流是否理想地从源传输到集成电路来评估电源完整性(PI)。正在进行研究以通过滤除半导体器件的电源电压或接地电压的噪声来改善电源完整性。
发明内容
本发明构思的一些实施例提供了一种具有增强的电源完整性的半导体封装。
本发明构思的目的不限于上述目的；从以下描述中，本领域技术人员将清楚地理解上面未提及的其他目的。
根据本发明构思的示例性实施例，一种半导体封装可以包括：半导体芯片；第一外部电容器，在所述半导体芯片上并包括第一电极和第二电极；第二外部电容器，在所述半导体芯片上并包括第一电极图案和第二电极图案；以及导电图案，在所述半导体芯片上并且电连接到所述第一外部电容器的所述第一电极和所述第二外部电容器的所述第一电极图案。所述第一外部电容器的所述第二电极可以与所述第二外部电容器的所述第二电极图案绝缘。
根据本发明构思的示例性实施例，一种半导体封装可以包括：半导体芯片；第一金属图案和第二金属图案，布置在所述半导体芯片上并且彼此电绝缘；导电图案，在所述半导体芯片上；第一外部电容器，在所述半导体芯片上；以及第二外部电容器，在所述半导体芯片上。所述第一外部电容器的第一电极可以通过所述导电图案电连接到所述第二外部电容器的第一电极图案。所述第一外部电容器的第二电极可以电连接到所述第一金属图案。所述第二外部电容器的第二电极图案可以电连接到所述第二金属图案。
根据本发明构思的示例性实施例，一种半导体封装可以包括：多个堆叠的半导体芯片；多个外部电容器，彼此间隔开并且各自包括第一电极和第二电极；以及接地图案，在所述半导体芯片上并且电连接到所述外部电容器的第一电极。所述外部电容器的第二电极包括第一电源电极和电连接到与所述第一电源电极的电源端子不同的电源端子的第二电源电极。
附图说明
图1A是示出了根据本发明构思的示例性实施例的半导体封装的平面图；
图1B示出了沿图1A的线B-B’截取的截面图；
图1C示出了沿图1A的线C-C’截取的截面图；
图1D是示出了根据本发明构思的示例性实施例的半导体封装的截面图；
图2A是示出了根据本发明构思的示例性实施例的半导体封装的平面图；
图2B示出了沿图2A的线B-B’截取的截面图；
图2C示出了沿图2A的线D-D’截取的截面图；
图3A是示出了根据本发明构思的示例性实施例的半导体模块的平面图；
图3B示出了沿图3A的线B”-B”’截取的截面图；以及
图3C示出了沿图3A的线C”-C”’截取的截面图。
具体实施方式
在此，根据本发明构思对半导体封装和包括该半导体封装的半导体模块进行描述。
图1A是示出了根据本发明构思的示例性实施例的半导体封装的平面图。图1B示出了沿图1A的线B-B’截取的截面图。图1C示出了沿图1A的线C-C’截取的截面图。
参考图1A至图1C，半导体封装1可以包括：基板100、第一半导体芯片210、第二半导体芯片220、第三半导体芯片230；第一外部电容器C1和第二外部电容器C2；第一电源图案310；第二电源图案320；以及接地图案350。基板100可以包括印刷电路板(PCB)、硅基板等。基板100的底面上可以设置有第一电源端子101、第二电源端子102、接地端子105和信号端子107。第一电源电压V1可以被施加到第一电源端子101。第一电源电压V1可以是用于第一半导体芯片210、第二半导体芯片220和第三半导体芯片230的缓冲器或核心逻辑电路的输出电压Vdd。第二电源电压V2可以施加到第二电源端子102。第二电源电压V2可以是第一半导体芯片210、第二半导体芯片220和第三半导体芯片230的输出缓冲器电压Vddq。第二电源电压V2可以与第一电源电压V1不同。例如，第一电源电压V1和第二电源电压V2可以是正电压，且第二电源电压V2可以大于第一电源电压V1。接地电压Vg可以施加到接地端子105。
第一半导体芯片210、第二半导体芯片220和第三半导体芯片230可以分别堆叠在基板100上。第一半导体芯片210可以包括逻辑电路、存储器电路等或其组合。第一半导体芯片210可以充当控制器芯片，但不限于此。第一半导体芯片210可以包括第一下电源通孔211、第二下电源通孔212、下接地通孔215和下信号通孔217。第一半导体芯片210可以被第一下电源通孔211、第二下电源通孔212、下接地通孔215和下信号通孔217穿透。第一下电源通孔211、第二下电源通孔212、下接地通孔215和下信号通孔217可以各自包括诸如铜、铝、钨、钛、钽等的导电材料或其合金。如虚线所示，第一下电源通孔211可以连接到第一电源端子101，并且因此可以充当第一电源电压V1的供应路径。在本说明书中，短语“电连接/耦接”包括通过其他导电部件间接连接/耦接以及直接连接/耦接的含义。在图1B、图1C、图1D、图2B、图2C、图3B和图3C中，基板100中的虚线可以概念性地指示电压或电信号的流动路径。可以对流动路径进行各种修改。第二下电源通孔212可以与第一下电源通孔211绝缘。第二下电源通孔212可以连接到第二电源端子102，并且因此可以充当第二电源电压V2的供应路径。第二电源电压V2可以通过第二下电源通孔212提供给第二半导体芯片220和第三半导体芯片230。下接地通孔215可以布置在第一下电源通孔211和第二下电源通孔212之间。下接地通孔215可以连接到接地端子105，并且因此可以被施加接地电压Vg。下接地通孔215可以与第一下电源通孔211和第二下电源通孔212绝缘。
第一半导体芯片210中可以设置有第一内部电容器Cap1和第二内部电容器Cap2。尽管未示出，但是第一内部电容器Cap1可以包括彼此间隔开的第一端子和第二端子。第一端子可以电连接到下接地通孔215，并且第二端子可以电连接到第一下电源通孔211。可以在第一端子与第二端子之间设置绝缘层。第一电源电压V1和接地电压Vg可以被施加到第一半导体芯片210的集成电路(未示出)。在这种情况下，第一电源电压V1和接地电压Vg可以被第一内部电容器Cap1进行电压噪声滤波，然后可以被施加到第一半导体芯片210的集成电路。例如，第一内部电容器Cap1可以用于实现去耦电路，该去耦电路防止半导体器件的一部分中产生的噪声影响半导体器件的其他部分。
第二内部电容器Cap2可以包括彼此间隔开的第一电极端子和第二电极端子。第一电极端子可以电连接到下接地通孔215，并且第二电极端子可以电连接到第二下电源通孔212。可以在第一电极端子与第二电极端子之间设置绝缘层。第二电源电压V2可以被施加到第一半导体芯片210的集成电路。在这种情况下，第二电源电压V2和接地电压Vg可以被第二内部电容器Cap2进行电压噪声滤波，然后可以被施加到第一半导体芯片210的集成电路。例如，第二内部电容器Cap2可以用于实现去耦电路。
第二半导体芯片220可以包括第一中间电源通孔221、第二中间电源通孔222、中间接地通孔225和中间信号通孔227。第二半导体芯片220的第一中间电源通孔221、第二中间电源通孔222、中间接地通孔225和中间信号通孔220可以各自包括诸如铜、铝、钨、钛、钽等的导电材料或其合金。第二半导体芯片220的第一中间电源通孔221、第二中间电源通孔222和中间接地通孔225可以分别电连接到第一半导体芯片210的第一下电源通孔211、第二下电源通孔212和下接地通孔215。
第二半导体芯片220中可以包括第一内部电容器Cap1和第二内部电容器Cap2。尽管未示出，但是第一内部电容器Cap1的第一端子可以电连接到中间接地通孔225，并且第一内部电容器Cap1的第二端子可以电连接到第一中间电源通孔221。可以在第一端子与第二端子之间设置绝缘层。第一电源电压V1和接地电压Vg可以被第一内部电容器Cap1进行电压噪声滤波，然后可以被施加到第二半导体芯片220的集成电路(未示出)。第二内部电容器Cap2的第一电极端子可以电连接到中间接地通孔225，并且第二内部电容器Cap2的第二电极端子可以电连接到第二中间电源通孔222。可以在第一电极端子与第二电极端子之间设置绝缘层。第二电源电压V2和接地电压Vg可以被第二内部电容器Cap2进行电压噪声滤波，然后可以被施加到第二半导体芯片220的集成电路。
第二半导体芯片220可以充当存储器芯片，但不限于此。第二半导体芯片220可以包括多个堆叠的第二半导体芯片。备选地，第二半导体芯片220可以被设置为单个芯片。备选地，第二半导体芯片220可以被完全省略。为了简化描述，将在下文中解释其中提供单个第二半导体芯片220的示例。
第三半导体芯片230可以布置在第二半导体芯片220上。第三半导体芯片230可以包括第一上电源通孔231、第二上电源通孔232和上接地通孔235。第三半导体芯片230的第一上电源通孔231、第二上电源通孔232和上接地通孔235可以分别电连接到第二半导体芯片220的第一中间电源通孔221、第二中间电源通孔222和中间接地通孔225。第一电源电压V1、第二电源电压V2和接地电压Vg可以分别施加到第三半导体芯片230的第一上电源通孔231、第二上通孔232和上接地通孔235。第三半导体芯片230的第一上电源通孔231、第二上电源通孔232和上接地通孔235可以各自包括诸如铜、铝、钨、钛、钽等的导电材料或其合金。
第三半导体芯片230中可以设置有第一内部电容器Cap1和第二内部电容器Cap2。尽管未示出，但是在第三半导体芯片230中，第一内部电容器Cap1的第一端子可以电连接到上接地通孔235，并且第一内部电容器Cap1的第二端子可以电连接到第一上电源通孔231。可以在第一端子与第二端子之间设置绝缘层。第一电源电压V1和接地电压Vg可以被第一内部电容器Cap1进行电压噪声滤波，然后可以被施加到第三半导体芯片230的集成电路(未示出)。第二内部电容器Cap2的第一电极端子可以电连接到上接地通孔235，并且第二内部电容器Cap2的第二电极端子可以电连接到第二上电源通孔232。可以在第一电极端子与第二电极端子之间设置绝缘层。第二电源电压V2和接地电压Vg可以被第二内部电容器Cap2进行电压噪声滤波，然后可以被施加到第三半导体芯片230的集成电路。第三半导体芯片230可以充当存储器芯片，但不限于此。
第一电源图案310、第二电源图案320和接地图案350可以设置在第三半导体芯片230上。第一电源图案310、第二电源图案320和接地图案350可以各自包括导电材料。导电材料可以包括诸如铜、铝等的金属或其合金。
第一电源图案310可以耦接到第三半导体芯片230的第一上电源通孔231。第二电源图案320可以耦接到第三半导体芯片230的第二上电源通孔232。第一电源图案310可以与第二电源图案320间隔开并且绝缘。如图1A所示，当在平面图中查看时，第一电源图案310可以与第三半导体芯片230的第一上电源通孔231重叠。同样地，第二电源图案320可以与第三半导体芯片230的第二上电源通孔232重叠。
接地图案350可以设置在第一电源图案310与第二电源图案320之间。接地图案350可以与第一电源图案310和第二电源图案320间隔开并且电绝缘。接地图案350可以耦接到第三半导体芯片230的上接地通孔235。如图1A所示，当在平面图中查看时，接地图案350可以与第三半导体芯片230的上接地通孔235重叠。
第一外部电容器C1可以布置在第三半导体芯片230上。第一外部电容器C1可以包括第一电极410、第二电极420和电介质层430。电介质层430可以布置在第一电极410与第二电极420之间。第一电极410和第二电极420可以各自包括诸如金属的导电材料。第二电极420可以耦接到第一电源图案310。第一电源电压V1可以通过第一半导体芯片210的第一下电源通孔211、第二半导体芯片220的第一中间电源通孔221和第三半导体芯片230的第一上电源通孔231以及第一电源图案310而施加到第二电极420。第一电极410可以耦接到接地图案350。接地电压Vg可以通过第一半导体芯片210的下接地通孔215、第二半导体芯片220的中间接地通孔225和第三半导体芯片230的上接地通孔235以及接地图案350而施加到第一电极410。第一外部电容器C1可以滤除第一电源电压V1和接地电压Vg的电压噪声。由于第一外部电容器C1布置在第三半导体芯片230上，所以第一外部电容器C1可以减小其电容限制。例如，第一外部电容器C1的电容可以大于第一内部电容器Cap1的电容。可以由彼此并联连接的第一外部电容器C1和第一内部电容器Cap1形成第一电容器。第一电容器可以具有相应地连接到第一电源电压V1和接地电压Vg的相反端部。第一电容器可以表现出与第一外部电容器C1和第一内部电容器Cap1的电容之和相同的电容。
由于第一外部电容器C1通过第一下电源通孔211、第一中间电源通孔221和第一上电源通孔231以及下接地通孔215、中间接地通孔225和上接地通孔235而连接到第一内部电容器Cap1，因此与第一外部电容器C1通过基板100连接到第一半导体芯片210至第三半导体芯片230的集成电路(未示出)的情况相比，第一外部电容器C1与第一半导体芯片210至第三半导体芯片230的集成电路(未示出)之间的距离可以减小。因此，第一外部电容器C1与第一半导体芯片210至第三半导体芯片230的集成电路(未示出)之间的电感可以减小。电容器之间的电感减小可以增强半导体封装1的电源完整性。
第二外部电容器C2可以布置在第三半导体芯片230上。第二外部电容器C2可以滤除第二电源电压V2和接地电压Vg的电压噪声。第二外部电容器C2可以包括第一电极图案510、第二电极图案520和电介质图案530。电介质图案530可以插入在第一电极图案510与第二电极图案520之间。第一电极图案510和第二电极图案520可以各自包括诸如金属的导电材料。第二外部电容器C2的第一电极图案510可以耦接到接地图案350。接地电压Vg可以被施加到第一电极图案510。第二外部电容器C2的第二电极图案520可以耦接到第二电源图案320。第二电源电压V2可以通过第二下电源通孔212、第二中间电源通孔222和第二上电源通孔232以及第二电源图案320而施加到第二电极图案520。第二电极图案520可以与第一外部电容器C1的第二电极420绝缘。
由于第二外部电容器C2通过第二下电源通孔212、第二中间电源通孔222和第二上电源通孔232以及下接地通孔215、中间接地通孔225和上接地通孔235而连接到第一半导体芯片210至第三半导体芯片230的集成电路(未示出)，因此在长度方面，第二外部电容器C2与第一半导体芯片210至第三半导体芯片230之间的电连接路径可以减小。电连接路径的长度的减小可以增强半导体封装1的电源完整性。
第二外部电容器C2的电容可以大于第二内部电容器Cap2的电容。可以由彼此并联连接的第二外部电容器C2和第二内部电容器Cap2形成第二电容器。第二电容器可以具有相应地连接到第二电源电压V2和接地电压Vg的相反端部。第二电容器可以表现出与第二外部电容器C2和第二内部电容器Cap2的电容之和相同的电容。
电压噪声可以快速分散并且被滤除电压噪声的越来越多的电容器所滤除。随着滤除电压噪声的电容器的电容增加，电源完整性可以提高。电压噪声可以包括高频噪声。第一外部电容器C1和第二外部电容器C2可以共享接地图案350。接地图案350可以电连接到第一内部电容器Cap1、第一外部电容器C1、第二内部电容器Cap2和第二外部电容器C2。接地图案350可以用于将第一内部电容器Cap1、第一外部电容器C1、第二内部电容器Cap2和第二外部电容器C2彼此合并。例如，第一电容器和第二电容器可以彼此合并。如此，滤除电压噪声的电容器可以具有增加的电容。在一些实施例中，不仅第一电容器而且第二电容器可以滤除第一电源电压V1和接地电压Vg的电压噪声。不仅第二电容器而且第一电容器可以滤除第二电源电压V2和接地电压Vg的电压噪声。因此，电压噪声可以快速分散并且被第一电容器和第二电容器滤除。总之，半导体封装1可以提高电源完整性。
由于接地图案350布置在第三半导体芯片230上，因此第一外部电容器C1与第二外部电容器C2之间的电路径的长度可以减小。结果，第一外部电容器C1与第二外部电容器C2之间的电感可以减小。
如图1A所示，可以设置多个第一外部电容器C1，并且第一外部电容器C1可以彼此并联连接。同样地，可以设置多个第二外部电容器C2，并且第二外部电容器C2可以彼此并联连接。第一电容器和第二电容器的电容可以增加，并且因此，半导体封装1可以进一步提高电源完整性。为了简化描述，将在下文中描述包括单个第一外部电容器C1和单个第二外部电容器C2的示例。
虽然接地图案350被示出为与第一电极410和第一电极图案510直接接触，但是可以在接地图案350与第一电极410之间以及在接地图案350与第一电极图案510之间插入插入件(未示出)。互连端子800可以插入在第一半导体芯片210、第二半导体芯片220和第三半导体芯片230之间以及第一半导体芯片210和基板100之间。互连端子800可以将第一半导体芯片210、第二半导体芯片220和第三半导体芯片230彼此电连接。插入件和互连端子800可以包括凸块、焊料或柱。第一半导体芯片210、第二半导体芯片220和第三半导体芯片230可以包括对应的下信号通孔217、中间信号通孔227和上信号通孔237，将在下面参考图1C对此进行讨论。
第一半导体芯片210可以包括下信号通孔217，其充当信号端子107与第二半导体芯片220之间的电信号路径。第一半导体芯片210可以被配置为使得下信号通孔217可以与第一下电源通孔211、第二下电源通孔212和下接地通孔215绝缘。第二半导体芯片220可以包括电连接到信号端子107和第一半导体芯片210的下信号通孔217两者的中间信号通孔227。第二半导体芯片220可以被配置为使得中间信号通孔227可以与第一中间电源通孔221、第二中间电源通孔222和中间接地通孔225绝缘。
第三半导体芯片230可以是最上面的半导体芯片。第三半导体芯片230可以不包括下信号通孔217。第三半导体芯片230可以被配置为使得其集成电路(未示出)可以被设置得更靠近其底面230a。第三半导体芯片230的底面230a可以面向第二半导体芯片220。第三半导体芯片230的底面230a可以充当有源表面。来自第三半导体芯片230的集成电路的电信号可以通过第二半导体芯片220的中间信号通孔227和第一半导体芯片210的下信号通孔217传输到信号端子107。因此，可以在第三半导体芯片230与外部设备(未示出)之间传送电信号。
图1D示出了与图1A的线C-C’相对应的截面，示出了根据本发明构思的示例性实施例的半导体封装。下文中将省略前述内容的重复描述。
参考图1D，半导体封装1a可以包括基板100、第一半导体芯片210、第二半导体芯片220、第三半导体芯片230、第一外部电容器C1、第二外部电容器C2和接地图案350。基板100、第一外部电容器C1、第二外部电容器C2和接地图案350可以分别与图1A至图1C中所示的基板100、第一外部电容器C1、第二外部电容器C2和接地图案350相同。信号端子107、第一半导体芯片210和第二半导体芯片220可以分别与图1A至图1C中所示的信号端子107、第一半导体芯片210和第二半导体芯片220相同。第三半导体芯片230可以包括上信号通孔237。第三半导体芯片230可以被配置为使得其集成电路(未示出)可以被设置得更靠近其顶面230b。上信号通孔237可以耦接到第三半导体芯片230的集成电路。第三半导体芯片230的上信号通孔237可以耦接到第二半导体芯片220的中间信号通孔227。来自第三半导体芯片230的电信号可以通过第三半导体芯片230的上信号通孔237传输到信号端子107。因此，可以将电信号输入到第三半导体芯片230以及从第三半导体芯片230输出电信号。第三半导体芯片230的上信号通孔237可以与第一电源图案310、第二电源图案320和接地图案350绝缘。
尽管未示出，但是如图1B所讨论的，第三半导体芯片230可以包括第一上电源通孔231、第二上电源通孔232和上接地通孔235。
图2A是示出了根据本发明构思的示例性实施例的半导体封装的平面图。图2B示出了沿图2A的线B-B’截取的截面图。图2C示出了沿图2A的线D-D’截取的截面图。下文中将省略前述内容的重复描述。
参考图2A、图2B和图2C，半导体封装2可以包括基板100、第一半导体芯片210、第二半导体芯片220、第三半导体芯片230、第一电源图案310、第二电源图案320、接地图案350、第一外部电容器C1和第二外部电容器C2，并且还可以包括第三电源图案330和第三外部电容器C3。基板100上可以设置有接地端子105、第一电源端子101、第二电源端子102和第三电源端子103。如图2C所示，第三电源电压V3可以被施加到第三电源端子103。第三电源电压V3可以不同于施加到第一电源端子101的第一电源电压V1和施加到第二电源端子102的第二电源电压V2两者。第三电源电压V3可以是参考电压。第一半导体芯片210可以包括第一下电源通孔211、第二下电源通孔212和下接地通孔215，并且还可以包括第三下电源通孔213。第二半导体芯片220可以包括第一中间电源通孔221、第二中间电源通孔222和中间接地通孔225，并且还可以包括第三中间电源通孔223。第三半导体芯片230可以包括第一上电源通孔231、第二上电源通孔232和上接地通孔235，并且还可以包括第三上电源通孔233。第一半导体芯片210、第二半导体芯片220和第三半导体芯片230的第一下电源通孔211、第一中间电源通孔221和第一上电源通孔231、第二下电源通孔212、第二中间电源通孔222和第一上电源通孔231以及下接地通孔215、中间接地通孔225和上接地通孔235可以与图1A和图1B中所讨论的相同。第一半导体芯片210、第二半导体芯片220和第三半导体芯片230的第三下电源通孔213、第三中间电源通孔223和第三上电源通孔233可以各自包括导电材料。
如图2C所示，第三电源电压V3可以通过第三电源端子103提供给第一半导体芯片210、第二半导体芯片220和第三半导体芯片230。第三内部电容器Cap3可以设置在第一半导体芯片210、第二半导体芯片220和第三半导体芯片230中的每一个中。第三内部电容器Cap3可以具有相反的端部，其中一个端部连接到第一半导体芯片210的下接地通孔215、第二半导体芯片220的中间接地通孔225和第三半导体芯片230的上接地通孔235中的对应一个，另一个端部连接到第一半导体芯片210的第三下电源通孔213、第二半导体芯片220的第三中间电源通孔223和第三半导体芯片230的第三上电源通孔233中的对应一个。第三内部电容器Cap3还可以包括电介质层，该电介质层设置在第三内部电容器Cap3的相反端部之间。第三内部电容器Cap3可以滤除第三电源电压V3和接地电压Vg的电压噪声。
第三外部电容器C3可以布置在第三半导体芯片230上。第三外部电容器C3可以包括第一电极部分610、第二电极部分620和电介质部分630。第一电极部分610和第二电极部分620可以各自包括诸如金属等导电材料。电介质部分630可以布置在第一电极部分610与第二电极部分620之间。第二电极部分620可以耦接到第三电源图案330，并且因此可以被施加第三电源电压V3。第一电极部分610可以电耦接到接地图案350。接地电压Vg可以被施加到第一电极部分610。
可以由彼此并联连接的第三外部电容器C3和第三内部电容器Cap3形成第三电容器。第三电容器可以滤除第三电源电压V3和接地电压Vg的电压噪声。第三外部电容器C3可以通过接地图案350电连接到第一外部电容器C1和第二外部电容器C2。因此，半导体封装2可以提高电源完整性。尽管仅描述了单个第三外部电容器C3，但是将理解的是，可以设置多个第三外部电容器C3。
尽管未示出，但是如图1C所讨论的，第一半导体芯片210可以包括下信号通孔217，并且第二半导体芯片220可以包括中间信号通孔227。相反，第三半导体芯片230可以不包括上信号通孔237。备选地，如图1D所示，第三半导体芯片230还可以包括上信号通孔237。
图3A是示出了根据本发明构思的示例性实施例的半导体模块的平面图。图3B示出了沿图3A的线B”-B”’截取的截面图。图3C示出了沿图3A的线C”-C”’截取的截面图。下文中将省略前述内容的重复描述。
参考图3A至图3C，半导体模块10可以包括模块基板1000、半导体封装1和电子器件2000。模块基板1000可以包括印刷电路板(PCB)。半导体封装1可以安装在模块基板1000上。半导体封装1可以与图1A至图1C中所讨论的半导体封装1相同。例如，半导体封装1可以包括基板100、第一半导体芯片210、第二半导体芯片220、第三半导体芯片230、第一电源图案310、第二电源图案320、接地图案350、第一外部电容器C1和第二外部电容器C2。
电子器件2000可以安装在基板100上。电子器件2000可以布置为与第一半导体芯片210、第二半导体芯片220和第三半导体芯片230横向间隔开。如图3C中的虚线所示，电子器件2000可以通过基板100电连接到第一半导体芯片210、第二半导体芯片220和第三半导体芯片230。电子器件2000可以包括中央处理单元(CPU)、图形处理单元(GPU)等。
备选地，图2A至图2C所示的半导体封装2可以安装在可以制造半导体模块10的模块基板1000上。不同地，如图1D所示，第三半导体芯片230还可以包括上信号通孔237。
根据本文公开的示例性实施例，第一外部电容器可以通过接地图案电连接到第二外部电容器。第一外部电容器和第二外部电容器可以分别滤除第一电源电压、接地电压和第二电源电压的电压噪声。因此，半导体封装可以提高电源完整性。
本发明构思的该详细描述不应被解释为限于本文阐述的实施例，本发明构思旨在覆盖本发明的各种组合、修改和变化而不脱离本发明的精神和范围。所附权利要求应被解释为包括其他实施例。

Claims (20)

1.一种半导体封装，包括：
半导体芯片；
第一外部电容器，在所述半导体芯片上并包括第一电极和第二电极；
第二外部电容器，在所述半导体芯片上并包括第一电极图案和第二电极图案；以及
导电图案，在所述半导体芯片上并且电连接到所述第一外部电容器的所述第一电极和所述第二外部电容器的所述第一电极图案，
其中所述第一外部电容器的所述第二电极与所述第二外部电容器的所述第二电极图案绝缘。
2.根据权利要求1所述的半导体封装，其中：
所述第二电极电连接到第一电源端子，以及
所述第二电极图案电连接到与所述第一电源端子不同的第二电源端子。
3.根据权利要求1所述的半导体封装，其中所述半导体芯片包括：
接地通孔，耦接到所述导电图案；
第一电源通孔，电连接到所述第二电极；以及
第二电源通孔，电连接到所述第二电极图案。
4.根据权利要求3所述的半导体封装，其中所述半导体芯片还包括第一内部电容器，所述第一内部电容器包括第一端子和第二端子，
其中所述第一端子和所述第二端子分别电连接到所述接地通孔和所述第一电源通孔。
5.根据权利要求4所述的半导体封装，其中所述半导体芯片还包括第二内部电容器，所述第二内部电容器包括第一电极端子和第二电极端子，
其中所述第一电极端子和所述第二电极端子分别电连接到所述接地通孔和所述第二电源通孔。
6.根据权利要求1所述的半导体封装，还包括：
第一电源图案，在所述半导体芯片上并且耦接到所述第二电极；以及
第二电源图案，在所述半导体芯片上并且耦接到所述第二电极图案，
其中当在平面图中查看时，所述导电图案设置在所述第一电源图案与所述第二电源图案之间并且与所述第一电源图案和所述第二电源图案间隔开。
7.根据权利要求1所述的半导体封装，其中所述导电图案电连接到接地端子。
8.根据权利要求1所述的半导体封装，其中所述半导体芯片包括彼此堆叠的多个半导体芯片。
9.根据权利要求8所述的半导体封装，还包括：
基板；以及
在所述基板上的电子器件，
其中所述多个半导体芯片安装在所述基板上并且与所述电子器件横向间隔开。
10.一种半导体封装，包括：
半导体芯片；
第一金属图案和第二金属图案，布置在所述半导体芯片上并且彼此电绝缘；
导电图案，在所述半导体芯片上；
第一外部电容器，在所述半导体芯片上；以及
第二外部电容器，在所述半导体芯片上，
其中所述第一外部电容器的第一电极通过所述导电图案电连接到所述第二外部电容器的第一电极图案，
其中所述第一外部电容器的第二电极电连接到所述第一金属图案，以及
其中所述第二外部电容器的第二电极图案电连接到所述第二金属图案。
11.根据权利要求10所述的半导体封装，其中所述导电图案电连接到接地端子。
12.根据权利要求11所述的半导体封装，其中：
所述第一外部电容器的所述第二电极电连接到第一电源端子，以及
所述第二外部电容器的所述第二电极图案电连接到与所述第一电源端子不同的第二电源端子。
13.根据权利要求10所述的半导体封装，其中所述半导体芯片包括：
接地通孔，耦接到所述导电图案；
第一电源通孔，电连接到所述第一金属图案；以及
第二电源通孔，电连接到所述第二金属图案并与所述第一电源通孔绝缘。
14.根据权利要求10所述的半导体封装，还包括：第一内部电容器，在所述半导体芯片中，
其中所述第一内部电容器与所述第一外部电容器并联连接。
15.根据权利要求14所述的半导体封装，还包括：第二内部电容器，在所述半导体芯片中并与所述第二外部电容器并联连接。
16.根据权利要求10所述的半导体封装，还包括：第三外部电容器，在所述半导体芯片上，
其中所述第三外部电容器通过所述导电图案连接到所述第一外部电容器和所述第二外部电容器。
17.根据权利要求10所述的半导体封装，其中所述半导体芯片包括：
下部半导体芯片，包括第一下部电源通孔、第二下部电源通孔、下部接地通孔和下部信号通孔；以及
上部半导体芯片，在所述下部半导体芯片上并且包括第一上部电源通孔、第二上部电源通孔和上部接地通孔，
其中所述上部半导体芯片不包括信号通孔。
18.一种半导体封装，包括：
多个堆叠的半导体芯片；
多个外部电容器，彼此间隔开并且各自包括第一电极和第二电极；以及
接地图案，在所述半导体芯片上并且电连接到所述外部电容器的第一电极，
其中所述外部电容器的第二电极包括：
第一电源电极；以及
第二电源电极，电连接到与所述第一电源电极的电源端子不同的电源端子。
19.根据权利要求18所述的半导体封装，其中每个半导体芯片包括第一电源通孔、第二电源通孔和接地通孔，
其中所述接地通孔耦接到所述接地图案，
其中所述第一电源通孔连接到所述第一电源电极；以及
其中所述第二电源通孔连接到所述第二电源电极。
20.根据权利要求18所述的半导体封装，其中所述第二电极还包括第三电源电极，以及
其中所述第三电源电极电连接到与所述第一电源电极和所述第二电源电极的电源端子不同的电源端子。
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