WO2022000150A1 - 堆叠存储器及存储系统 - Google Patents

堆叠存储器及存储系统 Download PDF

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Publication number
WO2022000150A1
WO2022000150A1 PCT/CN2020/098645 CN2020098645W WO2022000150A1 WO 2022000150 A1 WO2022000150 A1 WO 2022000150A1 CN 2020098645 W CN2020098645 W CN 2020098645W WO 2022000150 A1 WO2022000150 A1 WO 2022000150A1
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Prior art keywords
volatile memory
die
memory die
stacked
data
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PCT/CN2020/098645
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English (en)
French (fr)
Inventor
景蔚亮
王正波
崔靖杰
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华为技术有限公司
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Priority to PCT/CN2020/098645 priority Critical patent/WO2022000150A1/zh
Priority to EP20943730.0A priority patent/EP4156189A4/en
Priority to CN202080101884.3A priority patent/CN115699187A/zh
Publication of WO2022000150A1 publication Critical patent/WO2022000150A1/zh
Priority to US18/146,996 priority patent/US12014058B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1697—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2297—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/141—Battery and back-up supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Definitions

  • the present application relates to the field of memory, and in particular, to a stacked memory and a storage system.
  • multiple layers of memory dies can be stacked to form a stacked memory.
  • the stacking number of memory dies in the stacked memory is also increasing, but due to the limitation of the internal space of the installed electronic equipment, the thickness of each layer of memory dies is getting thinner and thinner, resulting in a decrease in the reliability of the entire memory and high stacking.
  • the upper memory die may experience power and signal integrity degradation due to parasitic capacitance and parasitic resistance.
  • circuits for improving power integrity and signal integrity occupy the space of one layer of die alone, and when the thickness of each layer of die remains unchanged, the height of the entire stacked memory will be increased, and the height of the entire stacked memory will be increased. In the same case, the thickness of each layer of the die will be reduced, which will further reduce the reliability.
  • Embodiments of the present application provide a stacked memory and a storage system, which are used to prevent the power integrity and signal integrity of the stacked memory from deteriorating without increasing the number of dies.
  • a stacked memory including a stacked volatile memory die, a nonvolatile memory die, and a control die; wherein the nonvolatile memory die includes a nonvolatile memory array and peripheral circuits, the peripheral circuits include power integrity circuits and signal integrity circuits; the power integrity circuits are used to optimize the power integrity of the power obtained from the lower die and transmit it to the upper die; the power integrity optimization includes filtering out At least one of voltage noise and IR drop reduction; signal integrity circuit is used to optimize the signal integrity of the signal obtained from the lower die and transmit it to the upper die; signal integrity optimization includes reducing common mode noise, impedance matching at least one of them.
  • the stacked memory includes stacked volatile memory dies and non-volatile memory dies.
  • a non-volatile memory die includes a non-volatile memory array and peripheral circuits.
  • the peripheral circuits include a power integrity circuit and a signal integrity circuit, wherein the power integrity circuit is used to optimize the power integrity of the power obtained from the lower layer die and transmit it to the upper layer die; the signal integrity circuit is used to obtain the power from the lower layer. The signal acquired by the die is optimized for signal integrity and then transmitted to the upper die.
  • Non-volatile memory arrays can be used to store data
  • peripheral circuits can be used to improve power and signal integrity between the bottom die and the top die of the stacked memory
  • the peripheral circuits do not occupy a single layer of the die,
  • the power integrity and signal integrity of the stacked memory are prevented from degrading without increasing the number of dies.
  • the stacked memory is further stacked with a control die, and the control die is used to: control the peripheral circuit to store data in the volatile memory die to the non-volatile memory die; or, The peripheral circuits are controlled to store data from the non-volatile memory die to the volatile memory die.
  • the control die stores the data in the volatile memory die to the non-volatile memory die, realizing data backup; the control die stores the data in the non-volatile memory die to the volatile memory die slice, to achieve data recovery. It not only improves the reliability of data storage, but also realizes data backup and recovery within the chip, eliminating the need for data transmission between chips, reducing energy consumption during data backup and recovery.
  • control die is specifically used to: control the peripheral circuit to store data in the volatile memory die to the non-volatile memory die when detecting that the working power supply is powered off; When the working power is restored, the peripheral circuit is controlled to store the data in the non-volatile memory die to the volatile memory die.
  • the stacked memory can be used for power-down data backup.
  • the data is checkpoint data
  • the control die is specifically used to: control the peripheral circuit to copy the data in the volatile memory die when the checkpoint data backup command is received or the timing reaches the backup cycle.
  • the control die when the checkpoint data backup command is received or the timing reaches the backup period, the control die is specifically configured to: if the free storage resources in the non-volatile memory die are higher than the threshold, then The current checkpoint state data is stored to the free storage resources of the non-volatile memory die; otherwise, the current checkpoint state data is overwritten with the oldest checkpoint state data.
  • This implementation prevents insufficient storage space to back up checkpoint state data.
  • the non-volatile memory array and peripheral circuits are implemented on the same substrate of the non-volatile memory die. That is, the non-volatile memory array and peripheral circuits are implemented in a two-dimensional planar structure on the same substrate of the non-volatile memory die.
  • the non-volatile storage array includes a first non-volatile storage array and a second non-volatile storage array, the first non-volatile storage array and the second non-volatile storage array
  • the arrays are implemented on both sides of the peripheral circuits on the same layer.
  • the non-volatile memory die is a symmetrical structure, and the time delay of the peripheral circuits reading and writing the data stored in the two non-volatile memory arrays is very small.
  • the non-volatile memory array and peripheral circuits are implemented on different layers of the non-volatile memory die. That is, the non-volatile memory array and peripheral circuits are implemented on different layers of the non-volatile memory die in a three-dimensional stacked structure.
  • the non-volatile memory die further includes a substrate, a first metal layer group and a second metal layer group, peripheral circuits are implemented on the substrate, the first metal layer group, the non-volatile The non-volatile memory array, the second metal layer group and the substrate are sequentially stacked on different layers of the non-volatile memory die. That is, the non-volatile memory array and peripheral circuits are implemented on different layers of the non-volatile memory die in a three-dimensional stacked structure.
  • the memory cell types of the non-volatile memory array include flash memory, ferroelectric random access memory, magnetic memory, phase change random access memory, or resistive random access memory.
  • the volatile memory die includes a first volatile memory die and a second volatile memory die, the first volatile memory die, the non-volatile memory die , a second volatile memory die, and a control die are stacked in sequence.
  • the volatile memory die includes a first volatile memory die and a second volatile memory die
  • the nonvolatile memory die includes the first nonvolatile memory die and a second non-volatile memory die, the first volatile memory die, the first non-volatile memory die, the second volatile memory die, the second non-volatile memory die and the The control dies are stacked one after the other.
  • the volatile memory die, the non-volatile memory die, and the control die are stacked in sequence.
  • a storage system comprising: the stacked memory according to the first aspect and any of its implementations, a working power supply and a backup power supply; when the storage system is in normal operation, the working power supply performs the operation of the stacked memory Power supply; when the working power is cut off, switch to the backup power supply to supply power to the stacking memory; when the working power is restored, switch to the working power supply to supply the stacking memory.
  • FIG. 1 is a schematic structural diagram of a storage system according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another storage system provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram 1 of a stacked memory provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another storage system provided by an embodiment of the present application.
  • FIG. 5 is a second schematic structural diagram of a stacked memory according to an embodiment of the present application.
  • FIG. 6 is a third structural schematic diagram of a stacked memory provided by an embodiment of the present application.
  • FIG. 7 is a fourth schematic structural diagram of a stacked memory provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a non-volatile memory die provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another non-volatile memory die provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another non-volatile memory die provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a power integrity circuit and a signal integrity circuit provided by an embodiment of the application;
  • FIG. 12 is a schematic package diagram of a stacked memory and a processor according to an embodiment of the present application.
  • the word "exemplary” is used to mean serving as an example, illustration or illustration. Any embodiment or design described in this application as "exemplary” should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of the word example is intended to present a concept in a concrete way.
  • Signal Integrity In stacked memory, memory dies are stacked using through silicon vias (TSVs) and/or bonding (bonding) techniques, resulting in parasitic capacitance and parasitic resistance .
  • Signal Integrity means that after the signal is transmitted from the bottom die to the upper die through TSV and/or bonding, it can still meet the requirements of normal operation.
  • Signal integrity problems include, but are not limited to, impedance matching problems (ringing, crosstalk), common mode noise (ground bounce, IR drop) and the like during signal transmission.
  • Power Integrity In stacked memory, power integrity refers to the fact that after the supply voltage is transferred from the bottom die to the top die through TSV and/or bonding, it still meets the requirements for normal operation. Power integrity issues include, but are not limited to, IR drop of the power supply voltage during transmission, voltage noise (such as large noise introduced by current changes when reading and writing DRAM), and the like.
  • a checkpoint is when a processor synchronizes pages in memory and pages in a shared memory buffer at a specific point in time.
  • the processor can be a chip.
  • it can be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), or a central processing unit.
  • It can be a central processor unit (CPU), a network processor (NP), a digital signal processing circuit (DSP), or a microcontroller (MCU) , it can also be a programmable logic device (PLD) or other integrated chips.
  • FPGA field programmable gate array
  • ASIC application specific integrated circuit
  • SoC system on chip
  • CPU central processor unit
  • NP network processor
  • DSP digital signal processing circuit
  • MCU microcontroller
  • PLD programmable logic device
  • a stacked memory is a memory formed by stacking multiple layers of memory dies, and each layer of memory dies includes a memory array formed by arranging a plurality of memory cells.
  • Volatile memory refers to memory whose stored data disappears when the power supply is turned off.
  • the volatile memories involved in the embodiments of the present application include: dynamic random access memory (dynamic random access memory, DRAM), high-bandwidth memory (high-bandwidth memory, HBM), hybrid memory cube (hybrid memory cube, HMC) and the like.
  • Non-volatile memory refers to memory whose stored data does not disappear when the power supply is turned off. Non-volatile memory is divided into non-rewritable memory and rewritable memory according to whether it can be rewritten.
  • the non-volatile memory involved in the embodiments of this application refers to rewritable memory, including: flash memory, ferroelectric random access memory (ferroelectric random access memory) random access memory (FeRAM), magnetic memory (magnetic, MRAM), phase change random access memory (PRAM), resistance switching random access memory (ReRAM), etc.
  • FeRAM is a ferroelectric film capacitor that replaces the conventional charge storage capacitor.
  • the polarization reversal of the ferroelectric film capacitor is used to store data.
  • MRAM uses magnetic field polarization instead of electric charge to store data.
  • PRAM stores data by using the difference in conductivity exhibited by special materials when they transform between crystalline and amorphous states.
  • ReRAM stores data with different resistance values.
  • the embodiment of the present application provides a storage system based on non-volatile dual inline memory modules (NVDIMM), which is used to improve the data reliability of the stacked memory.
  • the storage system includes: a volatile memory 11 , an NVDIMM 12 , a working power supply 13 and a backup power supply 14 .
  • the memory in NVDIMM 12 may be stacked memory.
  • the volatile memory 11 may include HBM, HMC, or the like.
  • the volatile memory 11 and the NVDIMM 12 are connected through a bus.
  • the working power supply 13 supplies power to the work of the volatile memory 11 and the NVDIMM 12.
  • the backup power supply 14 is switched to supply power to the work of the volatile memory 11 and the NVDIMM 12, and the data stored in the volatile memory 11 is backed up and stored in the NVDIMM 12.
  • the standby power supply 14 is switched to supply power to the work of the volatile memory 11 and the NVDIMM 12, and the data stored in the NVDIMM 12 is restored to the volatile memory 11.
  • the above-mentioned storage system consumes a lot of energy due to data transmission between chips, which imposes higher requirements on the backup power supply, increases the cost, and reduces the battery life of the electronic device.
  • the embodiment of the present application provides another storage system for implementing backup and recovery of checkpoint data.
  • the storage system includes: a processor 21 and a dual inline memory module (dual inline memory modules, DIMM) 22 .
  • DIMM dual inline memory modules
  • the processor 21 When the processor 21 runs the program, it periodically backs up the checkpoint data to the stack memory of the DIMM 22 through the double data rate (DDR) bus. The point data is restored to the processor 21, thereby preventing the processor 21 from crashing in a long-running program.
  • the storage system performs the backup and recovery of checkpoint data, it also consumes a lot of energy due to the data transmission between chips.
  • Embodiments of the present application provide a stacked memory for preventing power integrity and signal integrity degradation.
  • Embodiments of the present application provide a stacked memory for improving the power integrity and signal integrity of the stacked memory.
  • the stacked memory includes at least one volatile memory die 31 , at least one buffer die 32 and a control die 33 .
  • Volatile memory die 31, buffer die 32, and control die 33 are stacked by through silicon via (TSV) and/or bonding techniques.
  • TSV through silicon via
  • the control die 33 is used to control read and write operations to each volatile memory die 31 .
  • the buffer die 32 is not used to store data, but integrates decoupling capacitors, amplifiers, etc., to improve power integrity and signal integrity for data transmission between the control die 33 and the volatile memory die 31 .
  • the buffer die 32 occupies the space of one layer of die alone, and the height of the entire stacked memory will increase when the thickness of each layer of die remains unchanged. This reduces the thickness of each layer of the die, further reducing reliability.
  • Embodiments of the present application provide another storage system.
  • the stacked memory in the storage system includes stacked non-volatile memory dies and volatile memory dies, and is in a peripheral circuit of the non-volatile memory dies.
  • data transmission can be performed between non-volatile memory die and volatile memory die, data backup and data recovery can be realized through data transmission inside the chip, energy consumption is reduced, and the requirement for backup power is reduced, so that it can be Reduce costs and increase the battery life of electronic devices.
  • the storage system includes a stack memory 41 , a working power supply 42 , a backup power supply 43 , and optionally, a processor 44 .
  • the operation of the stack memory 41 and the processor 44 is powered by the operating power supply 42 when the entire storage system is in normal operation.
  • the backup power supply 43 is switched to supply power to the operations of the stack memory 41 and the processor 44 .
  • the working power supply 42 resumes power supply, the operation of the stack memory 41 and the processor 44 is switched to be powered by the working power supply 42 again.
  • the stacked memory includes: a volatile memory die 51 , a non-volatile memory die 52 and a control die 53 .
  • Volatile memory die 51, non-volatile memory die 52, and control die 53 are stacked by through silicon via (TSV) and/or bonding techniques.
  • TSV through silicon via
  • This application does not limit the stacking order of the volatile memory die 51, the non-volatile memory die 52 and the control die 53:
  • the volatile memory die 51 the non-volatile memory die 52 , and the control die 53 may be stacked in sequence.
  • the volatile memory die 51 includes a first volatile memory die 51A and a second volatile memory die 51B
  • the nonvolatile memory die 52 includes a first nonvolatile memory die 52 volatile memory die 52A and second non-volatile memory die 52B, first volatile memory die 51A, first non-volatile memory die 52A, second volatile memory die 51B, second The non-volatile memory die 52B are stacked in sequence, and then stacked with the control die 53 , that is, the volatile memory die 51 and the non-volatile memory die 52 are stacked at intervals and then stacked with the control die 53 .
  • the volatile memory die 51 includes a first volatile memory die 51A and a second volatile memory die 51B, the first volatile memory die 51A, the nonvolatile The memory die 52 and the second volatile memory die 51B are stacked in sequence, and then stacked with the control die 53 in sequence, that is, the nonvolatile memory die 52 is stacked between the two volatile memory die.
  • the non-volatile memory die includes a non-volatile memory array 521 and peripheral circuits 522 .
  • the non-volatile memory array 521 includes a plurality of non-volatile memory cells arranged in sequence.
  • the peripheral circuit 522 includes a read, write, and erase drive circuit, a data judgment circuit, and a command sending circuit, and these circuits are used to control reading and writing of data stored in the non-volatile memory array 521 .
  • the peripheral circuit 522 further includes a power integrity (PI) circuit 5221 and a signal integrity (SI) circuit 5222 .
  • the PI circuit 5221 is used for power integrity optimization of the power supply voltage obtained from the lower die (eg control die) (eg via TSV) and then transferred (eg via TSV) to the upper die (eg volatile memory die) , to improve the power integrity between the lower die and the upper die of the stacked memory;
  • SI circuits are used to optimize the signal integrity of the signal obtained from the lower die (eg through TSV) and transmit (eg through TSV) to the Upper die to improve signal integrity between the lower and upper dies of the stacked memory.
  • Power integrity optimization includes, but is not limited to, filtering out voltage noise (exemplary boost circuits as shown in Figure 11, A, B), reducing IR drop (exemplarily linear as shown in Figure 11, C at least one of voltage regulators).
  • Signal integrity optimization includes, but is not limited to, reducing common-mode noise (an exemplary differential amplifier as shown in Figure 11, D, and a filter, as shown in E), and implementing impedance matching (an exemplary, as shown in F in Figure 11). at least one of the impedance matching circuits shown).
  • the production process of the non-volatile memory die includes a front-end process and a back-end process.
  • the front-end process includes photolithography, etching machine, cleaning machine, ion implantation, chemical mechanical planarization, etc.
  • the back-end process includes wire bonding, bonding (Bonder), flux cooper backing (FCB), ball grid array (BGA) ball placement, inspection, testing, etc.
  • the peripheral circuit can be realized through the previous process flow.
  • the peripheral circuit of the stacked memory of FIG. 5 can improve the power integrity and signal of the stacked memory on the basis of the existing control of reading and writing data stored in the non-volatile memory array. Integrity, i.e. circuits that improve power integrity and signal integrity are integrated into the non-volatile memory die without taking up the space of a single layer of the die and therefore without increasing the height of the stacked memory.
  • the present application does not limit the stacking manner of the non-volatile memory array and peripheral circuits.
  • the non-volatile memory array 521 and the peripheral circuit 522 may be implemented on the same substrate of a non-volatile memory die.
  • the nonvolatile memory array 521 may include a first nonvolatile memory array 5211 and a second nonvolatile memory array 5212 , a first nonvolatile memory array 5211 and a second nonvolatile memory array 5211
  • the memory array 5212 can be implemented on both sides of the peripheral circuits 522 on the same layer. It should be noted that the embodiments of the present application do not limit the number of non-volatile memory arrays in the same layer.
  • the non-volatile memory array 521 and the peripheral circuit 522 may be implemented on different layers of a non-volatile memory die.
  • the non-volatile memory die also includes a substrate 523 , a first set of metal layers 524 and a second set of metal layers 525 .
  • Peripheral circuitry 522 is implemented on a substrate 523, and a first metal layer set 524, non-volatile memory array 521, second metal layer set 525, and substrate 523 are sequentially stacked on different layers of a non-volatile memory die.
  • the first metal layer set 524 and the second metal layer set 525 are used to route traces within the non-volatile memory die.
  • the present application does not limit the number of layers of the volatile memory die 51, for example, it may be 8 layers, 16 layers, or the like.
  • the present application does not limit the storage unit types of the non-volatile storage array, and the storage unit types of the non-volatile storage array include but are not limited to flash memory, FeRAM, MRAM, PRAM, ReRAM, and the like.
  • the control die 53 is used for: backing up the data stored in the volatile memory die 51 to the non-volatile memory die 52 .
  • the data in non-volatile memory die 52 is stored to volatile memory die 51 .
  • control die 53 controls the peripheral circuit 522 to store the data in the volatile memory die 51 to the non-volatile memory die 52 when a power failure of the working power is detected.
  • control die 53 controls the peripheral circuit 522 to store the data in the non-volatile memory die 52 to the volatile memory die 51 .
  • the power detection module or other power detection modules in the control die 53 detects the power-off event, and the control die 53 starts the backup power supply and enters the power-off data backup mode, and the control die 53 will Part or all of the data stored in the volatile memory die 51 is stored in the first storage area in the non-volatile memory die 52, and the backup power can be turned off after completion. If the working power is restored, the power detection module or other power detection module in the control die 53 detects the power failure recovery event, and the control die 53 stores the data stored in the first storage area in the non-volatile memory die 52 Restore storage to volatile memory die 51 .
  • the storage system When a power-down event occurs, the storage system does not need to back up the data stored in the volatile memory to an external non-volatile memory; when a power-down recovery event occurs, the storage system does not need to back up the external non-volatile memory
  • the backed up data is stored in volatile memory. Data backup and recovery can be achieved within the stacked memory, which can reduce energy consumption, reduce the requirement for backup power, and thus reduce costs.
  • the data is the checkpoint data when the program is running.
  • the control die 53 controls the peripheral circuit 522 to store the volatile memory die on the volatile memory die.
  • the data in 51 is stored to non-volatile memory die 52 .
  • the peripheral circuit 522 is controlled to store the data in the nonvolatile memory die 52 to the volatile memory die 51 .
  • the stacked memory 41 and the processor 44 may be packaged on a package substrate, the stacked memory 41 and the processor 44 are electrically connected through a bus in the wiring layer, and the stacked memory 41 and the processor 44 are electrically connected.
  • the devices 44 are respectively electrically connected to the package substrate through the wiring layers.
  • the processor periodically sends a checkpoint data backup command to the control die 53 of the stacked memory according to the backup cycle.
  • the control die 53 receives the checkpoint data backup command, according to the parameters in the checkpoint data backup command, the volatile memory is bare.
  • the checkpoint data stored in the slice 51 is backed up and stored in the second storage area of the non-volatile memory die 52, that is, the control die 53 backs up the checkpoint data according to the instruction of the processor.
  • the checkpoint data stored in the volatile memory die 51 is backed up and stored in the second storage area of the non-volatile memory die 52, that is, the control die 53 can autonomously Back up the checkpoint data.
  • the processor sends a checkpoint data recovery command to the control die 53 of the stacked memory.
  • the control die 53 receives the checkpoint data recovery command, according to the parameters in the checkpoint data recovery command, the nonvolatile The latest checkpoint data stored in the second storage area of the volatile memory die 52 is restored to the volatile memory die 51 .
  • the storage system When periodically backing up the checkpoint data, the storage system does not need to back up the checkpoint data stored in the volatile memory to an external non-volatile memory; when restoring the checkpoint data, the storage system does not need to Checkpoint data backed up by external non-volatile memory is stored in volatile memory.
  • the backup and recovery of checkpoint data can be realized within the stack memory, which can reduce energy consumption.
  • the aforementioned first storage area and second storage area may be the same area or different areas, and when they are different areas, the storage system may perform power-off data storage and recovery and checkpoint data storage and recovery at the same time.
  • the current checkpoint data is stored to the non-volatile memory die 52 free storage resources, do not overwrite the earliest checkpoint data. Otherwise, in the order of first input first output (FIFO), the current checkpoint status data is overwritten with the oldest checkpoint data.
  • FIFO first input first output
  • the method By retaining the original technical characteristics of the hybrid high-bandwidth memory, the method has high integration, low implementation cost and difficulty, and can still ensure that the bottom control die and the top DRAM die can be controlled without increasing the cost of the die.
  • the integrity of the signal and power transmitted between them ensures the reliability of 3D memory chips with high stack counts.
  • control die stores the data in the volatile memory die to the non-volatile memory die to realize data backup; the control die stores the data in the non-volatile memory die to the volatile memory die Memory die, enabling data recovery. Not only the reliability of data storage is improved, but also by implementing data backup and recovery within the chip, data transmission between chips is unnecessary, and energy consumption during data backup and recovery is reduced.
  • the stacked memory includes stacked volatile memory dies and non-volatile memory dies.
  • a non-volatile memory die includes a non-volatile memory array and peripheral circuits.
  • the peripheral circuits include a power integrity circuit and a signal integrity circuit, wherein the power integrity circuit is used to optimize the power integrity of the power obtained from the lower layer die and transmit it to the upper layer die; the signal integrity circuit is used to obtain the power from the lower layer.
  • the signal acquired by the die is optimized for signal integrity and then transmitted to the upper die.
  • Non-volatile memory arrays can be used to store data
  • peripheral circuits can be used to improve power and signal integrity between the bottom die and the top die of the stacked memory
  • the peripheral circuits do not occupy a single layer of the die,
  • the power integrity and signal integrity of the stacked memory are prevented from degrading without increasing the number of dies.
  • the disclosed systems, devices and methods may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned embodiments it may be implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • a software program it can be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, all or part of the processes or functions described in the embodiments of the present application are generated.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server, or data center Transmission to another website site, computer, server or data center via wired (eg coaxial cable, optical fiber, Digital Subscriber Line, DSL) or wireless (eg infrared, wireless, microwave, etc.) means.
  • the computer-readable storage medium can be any available medium that can be accessed by a computer or data storage devices including one or more servers, data centers, etc. that can be integrated with the medium.
  • the usable medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a Solid State Disk (SSD)), and the like.
  • a magnetic medium eg, a floppy disk, a hard disk, a magnetic tape
  • an optical medium eg, a DVD
  • a semiconductor medium eg, a Solid State Disk (SSD)

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Abstract

本申请公开了一种堆叠存储器及存储系统，涉及存储器领域，用于防止堆叠存储器的电源完整性和信号完整性下降的同时不增加裸片的数目。堆叠存储器包括相堆叠的易失性存储器裸片、非易失性存储器裸片；其中，非易失性存储器裸片包括非易失性存储阵列和外围电路，外围电路包括电源完整性电路和信号完整性电路；电源完整性电路用于将从下层裸片获取的电源进行电源完整性优化后传输给上层裸片；信号完整性电路用于将从下层裸片获取的信号进行信号完整性优化后传输给上层裸片。

Description

堆叠存储器及存储系统 技术领域
本申请涉及存储器领域，尤其涉及一种堆叠存储器(stacked memory)及存储系统。
背景技术
为了提高单个存储器的存储空间，可以将多层存储器裸片(memory die)堆叠成堆叠存储器。堆叠存储器中存储器裸片的堆叠数目也越来越大，但是受所安装的电子设备内部空间限制，使得每一层存储器裸片的厚度却越来越薄，导致整个存储器可靠性下降，高堆叠数下，由于寄生电容和寄生电阻的影响，上层的存储器裸片可能出现电源完整性与信号完整性下降。现有技术中，改善电源完整性与信号完整性的电路单独占用一层裸片的空间，在每一层裸片厚度不变的情况下会增加整个堆叠存储器的高度，在整个堆叠存储器的高度不变的情况下会降低每一层裸片的厚度，进一步导致可靠性下降。
发明内容
本申请实施例提供一种堆叠存储器及存储系统，用于防止堆叠存储器的电源完整性和信号完整性下降的同时不增加裸片的数目。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供了一种堆叠存储器，包括相堆叠的易失性存储器裸片、非易失性存储器裸片和控制裸片；其中，非易失性存储器裸片包括非易失性存储阵列和外围电路，外围电路包括电源完整性电路和信号完整性电路；电源完整性电路用于将从下层裸片获取的电源进行电源完整性优化后传输给上层裸片；电源完整性优化包括滤除电压噪声、降低IR压降中至少一项；信号完整性电路用于将从下层裸片获取的信号进行信号完整性优化后传输给上层裸片；信号完整性优化包括降低共模噪声、阻抗匹配中至少一项。
本申请实施例提供的堆叠存储器，堆叠存储器包括相堆叠的易失性存储器裸片、非易失性存储器裸片。非易失性存储器裸片包括非易失性存储阵列和外围电路。外围电路包括电源完整性电路和信号完整性电路，其中，电源完整性电路用于将从下层裸片获取的电源进行电源完整性优化后传输给上层裸片；信号完整性电路用于将从下层裸片获取的信号进行信号完整性优化后传输给上层裸片。非易失性存储阵列可以用于存储数据，外围电路可以用于提高堆叠存储器的底部裸片与顶部裸片之间的电源完整性和信号完整性，该外围电路没有单独占用一层裸片，因此防止堆叠存储器的电源完整性和信号完整性下降的同时不增加裸片的数目。
在一种可能的实施方式中，堆叠储存器还堆叠有控制裸片，控制裸片用于：控制外围电路将易失性存储器裸片中的数据存储至非易失性存储器裸片；或者，控制外围电路将非易失性存储器裸片中的数据存储至易失性存储器裸片。控制裸片将易失性存储器裸片中的数据存储至非易失性存储器裸片，实现了数据的备份；控制裸片将非易失性存储器裸片中的数据存储至易失性存储器裸片，实现了数据的恢复。不仅提高了 数据存储的可靠性，并且通过在芯片内部实现数据备份和恢复，不必进行芯片之间的数据传输，降低了数据备份和恢复过程中能耗。
在一种可能的实施方式中，控制裸片具体用于：在检测到工作电源断电时，控制外围电路将易失性存储器裸片中的数据存储至非易失性存储器裸片；在检测到工作电源恢复供电时，控制外围电路将非易失性存储器裸片中的数据存储至易失性存储器裸片。该堆叠存储器可以应用于掉电数据备份。
在一种可能的实施方式中，数据为检查点数据，控制裸片具体用于：在接收到检查点数据备份命令或者计时达到备份周期时，控制外围电路将易失性存储器裸片中的数据存储至非易失性存储器裸片；在接收到检查点数据恢复命令时，控制外围电路将非易失性存储器裸片中的数据存储至易失性存储器裸片。即该堆叠存储器可以应用于检查点数据备份。
在一种可能的实施方式中，在接收到检查点数据备份命令或者计时达到备份周期时，控制裸片具体用于：如果非易失性存储器裸片中的空闲存储资源高于门限，则将当前的检查点状态数据存储至非易失性存储器裸片的空闲存储资源；否则，将当前的检查点状态数据覆盖最早的检查点状态数据。该实施方式可以防止没有足够的存储空间来备份检查点状态数据。
在一种可能的实施方式中，非易失性存储阵列和外围电路实现在非易失性存储器裸片的同一衬底上。也就是说，非易失性存储阵列和外围电路是以二维平面结构实现在非易失性存储器裸片的同一衬底上。
在一种可能的实施方式中，非易失性存储阵列包括第一非易失性存储阵列和第二非易失性存储阵列，第一非易失性存储阵列和第二非易失性存储阵列实现在同一层的外围电路的两侧。非易失性存储器裸片是一个对称结构，外围电路对两个非易失性存储阵列中存储的数据进行读写的时延相差很小。
在一种可能的实施方式中，非易失性存储阵列和外围电路实现在非易失性存储器裸片的不同层。也就是说，非易失性存储阵列和外围电路是以三维堆叠结构实现在非易失性存储器裸片的不同层。
在一种可能的实施方式中，非易失性存储器裸片还包括衬底、第一金属层组和第二金属层组，外围电路实现在衬底上，第一金属层组、非易失性存储阵列、第二金属层组和衬底依次堆叠在非易失性存储器裸片的不同层。也就是说，非易失性存储阵列和外围电路是以三维堆叠结构实现在非易失性存储器裸片的不同层。
在一种可能的实施方式中，非易失性存储阵列的存储单元类型包括闪存、铁电随机存取存储器、磁存储器、相变随机存取存储器或阻变随机存取存储器。
在一种可能的实施方式中，易失性存储器裸片包括第一易失性存储器裸片和第二易失性存储器裸片，第一易失性存储器裸片、非易失性存储器裸片、第二易失性存储器裸片和控制裸片依次堆叠。
在一种可能的实施方式中，易失性存储器裸片包括第一易失性存储器裸片和第二易失性存储器裸片，非易失性存储器裸片包括第一非易失性存储器裸片和第二非易失性存储器裸片，第一易失性存储器裸片、第一非易失性存储器裸片、第二易失性存储器裸片、第二非易失性存储器裸片和控制裸片依次堆叠。
在一种可能的实施方式中，易失性存储器裸片、非易失性存储器裸片和控制裸片依次堆叠。
第二方面，提供了一种存储系统，包括：如第一方面及其任一实施方式所述的堆叠存储器、工作电源和备用电源；在存储系统正常工作时由工作电源对堆叠存储器的工作进行供电；在工作电源断电时，切换至由备用电源对堆叠存储器的工作进行供电；在工作电源恢复供电时，重新切换至由工作电源对堆叠存储器的工作进行供电。
第二方面的技术效果可以参照第一方面及其任一实施方式的技术效果。
附图说明
图1为本申请实施例提供的一种存储系统的结构示意图；
图2为本申请实施例提供的另一种存储系统的结构示意图；
图3为本申请实施例提供的一种堆叠存储器的结构示意图一；
图4为本申请实施例提供的又一种存储系统的结构示意图；
图5为本申请实施例提供的一种堆叠存储器的结构示意图二；
图6为本申请实施例提供的一种堆叠存储器的结构示意图三；
图7为本申请实施例提供的一种堆叠存储器的结构示意图四；
图8为本申请实施例提供的一种非易失性存储器裸片的结构示意图；
图9为本申请实施例提供的另一种非易失性存储器裸片的结构示意图；
图10为本申请实施例提供的又一种非易失性存储器裸片的结构示意图；
图11为本申请实施例提供的一种电源完整性电路和信号完整性电路的结构示意图；
图12为本申请实施例提供的一种堆叠存储器和处理器的封装示意图。
具体实施方式
在本申请实施例中，“示例的”一词用于表示作例子、例证或说明。本申请中被描述为“示例”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用示例的一词旨在以具体方式呈现概念。
首先对本申请实施例涉及的一些概念进行描述：
信号完整性(signal integrity，SI)：在堆叠存储器中，存储器裸片通过穿硅过孔(through silicon via，TSV)和/或键合(bonding)技术相堆叠，因此会产生寄生电容和寄生电阻，信号完整性指信号通过TSV和/或键合从底层裸片传输到上层裸片后，仍能满足正常工作的要求。信号完整性问题包括但不限于信号在传输过程中的阻抗匹配问题(振铃(ringing)、串扰(crosstalk))、共模噪声(地弹、IR压降(drop))等。
电源完整性(power integrity，PI)：在堆叠存储器中，电源完整性指供电电压通过TSV和/或键合从底层裸片传输到上层裸片后，仍能满足正常工作的要求。电源完整性问题包含但不限于供电电压在传输过程中的IR压降(drop)、电压噪声(例如读写DRAM时由于电流变化而引入较大噪声)等。
检查点(checkpoint)是指处理器在特定的时间点对存储器上的页面以及共享内存缓冲区中的页面进行同步。
处理器可以是一个芯片。例如，可以是现场可编程门阵列(field programmable gate  array，FPGA)，可以是专用集成芯片(application specific integrated circuit，ASIC)，还可以是系统芯片(system on chip，SoC)，还可以是中央处理器(central processor unit，CPU)，还可以是网络处理器(network processor，NP)，还可以是数字信号处理电路(digital signal processor，DSP)，还可以是微控制器(micro controller unit，MCU)，还可以是可编程控制器(programmable logic device，PLD)或其他集成芯片。
堆叠存储器即由多层存储器裸片(memory die)堆叠而成的存储器，每一层存储器裸片包括由多个存储单元排列而成的存储阵列。
易失性存储器指当供电电源关闭后，所存储的数据消失的存储器。本申请实施例涉及的易失性存储器包括：动态随机存取存储器(dynamic random access memory，DRAM)、高带宽存储器(high-bandwidth memory，HBM)、混合存储器立方体(hybrid memory cube，HMC)等。
非易失性存储器指当供电电源关闭后，所存储的数据不会消失的存储器。非易失性存储器根据是否可改写分为不可改写存储器和可改写存储器，其中，本申请实施例中涉及的非易失性存储器指可改写存储器，包括：闪存、铁电随机存取存储器(ferroelectric random access memory，FeRAM)、磁存储器(magnetic，MRAM)、相变随机存取存储器(phase change random access memory，PRAM)、阻变随机存取存储器(resistance switching random access memory，ReRAM)等。FeRAM是以铁电薄膜电容取代常规的存储电荷的电容，基于铁电材料的高介电常数和铁电极化特性，利用铁电薄膜电容的极化反转来存储数据。MRAM是利用磁场极化而非电荷来存储数据。PRAM是利用特殊材料在晶态和非晶态之间相互转化时所表现出来的导电性差异来存储数据。ReRAM是以电阻值的不同来存储数据。
本申请实施例提供了一种基于非易失性双列直插式存储模块(non-volatile dual inline memory modules，NVDIMM)的存储系统，用于提高堆叠存储器的数据可靠性。如图1所示，该存储系统包括：易失性存储器11、NVDIMM 12、工作电源13和备用电源14。NVDIMM 12中的存储器可以为堆叠存储器。该易失性存储器11可以包括HBM、HMC等。
易失性存储器11和NVDIMM 12通过总线相连。在整个存储系统正常工作时由工作电源13对易失性存储器11和NVDIMM 12的工作进行供电。在工作电源13因为故障等原因断电时，切换至由备用电源14对易失性存储器11和NVDIMM 12的工作进行供电，并将易失性存储器11中存储的数据备份存储至NVDIMM 12中。在工作电源13重新恢复供电时，重新切换至由备用电源14对易失性存储器11和NVDIMM 12的工作进行供电，并将NVDIMM 12中存储的数据恢复至易失性存储器11中。
上述存储系统在进行数据备份和数据恢复时，因为进行芯片之间的数据传输，因此会消耗大量能量，对备用电源提出了较高要求，提高了成本，并且会降低电子设备的续航时间。
本申请实施例提供了另一种存储系统，用于实现对检查点数据进行备份和恢复。如图2所示，该存储系统包括：处理器21和双列直插式存储模块(dual inline memory modules，DIMM)22。
处理器21在运行程序时，定期将检查点数据通过双倍速率(double data rate，DDR) 总线备份至DIMM 22的堆叠存储器中，当程序运行出错时，将DIMM 22的堆叠存储器中存储的检查点数据恢复至处理器21，从而防止处理器21长时间运行程序出现崩溃。但该存储系统在进行检查点数据的备份和恢复时，同样因为进行芯片之间的数据传输而消耗大量能量。
另外，随着电子设备对存储空间要求越来越大，堆叠存储器中存储器裸片的堆叠数目也越来越大，但是受所安装的电子设备内部空间限制，使得每一层存储器裸片的厚度却越来越薄，导致整个存储器可靠性下降，例如过薄的存储芯片容易破碎、数据保持时间变小且高堆叠数下电源完整性与信号完整性下降。本申请实施例提供了一种堆叠存储器，用于防止电源完整性和信号完整性下降。
本申请实施例提供了一种堆叠存储器，用于提高堆叠存储器的电源完整性和信号完整性。如图3所示，该堆叠存储器包括至少一个易失性存储器裸片(volatile memory die)31、至少一个缓冲裸片32和控制裸片(control die)33。易失性存储器裸片31、缓冲裸片32以及控制裸片33通过穿硅过孔(through silicon via，TSV)和/或键合(bonding)技术相堆叠。
控制裸片33用于控制对各个易失性存储器裸片31的读写操作。缓冲裸片32不用于存储数据，而是集成了去耦电容和放大器等，用于改善控制裸片33与易失性存储器裸片31之间传输数据的电源完整性和信号完整性。
但是上述堆叠存储器中，缓冲裸片32单独占用一层裸片的空间，在每一层裸片厚度不变的情况下会增加整个堆叠存储器的高度，在整个堆叠存储器的高度不变的情况下会降低每一层裸片的厚度，进一步导致可靠性下降。
本申请实施例提供了另一种存储系统，该存储系统中的堆叠存储器，包括堆叠的非易失性存储器裸片和易失性存储器裸片，在非易失性存储器裸片的外围电路中实现提高信号完整性和电源完整性的电路，不会占用额外的存储器裸片。另外，可以在非易失性存储器裸片和易失性存储器裸片之间进行数据传输，通过芯片内部的数据传输实现数据备份和数据恢复，降低能量消耗，降低对备用电源的要求，从而可以降低成本，提高电子设备的续航时间。
如图4所示，该存储系统包括堆叠存储器41、工作电源42、备用电源43，可选的，还可以包括处理器44。
在整个存储系统正常工作时由工作电源42对堆叠存储器41和处理器44的工作进行供电。在工作电源42因为故障等原因断电时，切换至由备用电源43对堆叠存储器41和处理器44的工作进行供电。在工作电源42重新恢复供电时，重新切换至由工作电源42对堆叠存储器41和处理器44的工作进行供电。
如图5-图7所示，该堆叠存储器包括：易失性存储器裸片51、非易失性存储器裸片52和控制裸片53。易失性存储器裸片51、非易失性存储裸片52以及控制裸片53通过穿硅过孔(through silicon via，TSV)和/或键合(bonding)技术相堆叠。
本申请不限定易失性存储器裸片51、非易失性存储器裸片52以及控制裸片53的堆叠顺序：
示例性的，如图5所示，可以按照易失性存储器裸片51、非易失性存储器裸片52以及控制裸片53的顺序依次堆叠。
或者，如图6所示，易失性存储器裸片51包括第一易失性存储器裸片51A和第二易失性存储器裸片51B，非易失性存储器裸片52包括第一非易失性存储器裸片52A和第二非易失性存储器裸片52B，第一易失性存储器裸片51A、第一非易失性存储器裸片52A、第二易失性存储器裸片51B、第二非易失性存储器裸片52B依次堆叠，然后与控制裸片53依次堆叠，即易失性存储器裸片51和非易失性存储器裸片52间隔堆叠后再与控制裸片53堆叠。
或者，如图7所示，易失性存储器裸片51包括第一易失性存储器裸片51A和第二易失性存储器裸片51B，第一易失性存储器裸片51A、非易失性存储器裸片52、第二易失性存储器裸片51B依次堆叠，然后与控制裸片53依次堆叠，即非易失性存储器裸片52堆叠在两个易失性存储器裸片之间。
如图8-图10所示，非易失性存储器裸片包括非易失性存储阵列521和外围电路522。
其中，非易失性存储阵列521包括依次排列的多个非易失性存储单元。
外围电路522包括读、写、擦驱动电路、数据判断电路以及指令发送电路，这些电路用于控制对非易失性存储阵列521中存储的数据的读写。
如图11所示，外围电路522还包括电源完整性(PI)电路5221和信号完整性(SI)电路5222。PI电路5221用于将从下层裸片(例如控制裸片)获取(例如通过TSV)的供电电压进行电源完整性优化后传输(例如通过TSV)给上层裸片(例如易失性存储器裸片)，以提高堆叠存储器的下层裸片与上层裸片之间的电源完整性；SI电路用于将从下层裸片获取(例如通过TSV)的信号进行信号完整性优化后传输(例如通过TSV)给上层裸片，以提高堆叠存储器的下层裸片与上层裸片之间的信号完整性。
电源完整性优化包括但不限于滤除电压噪声(示例性的如图11中的A、B所示的升压电路)，降低IR压降(示例性的如图11中的C所示的线性稳压源)中至少一项。信号完整性优化包括但不限于降低共模噪声(示例性的如图11中的D所示的差分放大器、E所示的滤波器)，实现阻抗匹配(示例性的如图11中的F所示的阻抗匹配电路)中至少一项。
非易失性存储器裸片的生产工艺包括前道工艺流程和后道工艺流程，前道工艺流程包括光刻、刻蚀机、清洗机、离子注入、化学机械平坦等。后道工艺流程包括打线、压焊(Bonder)、焊剂铜垫衬(flux cooper backing，FCB)、球栅阵列(ball grid array，BGA)植球、检查、测试等。外围电路可以通过前道工艺流程来实现。
与图3的堆叠存储器相比，图5的堆叠存储器的外围电路在现有的控制对非易失性存储阵列中存储的数据的读写的基础上，可以提高堆叠存储器的电源完整性和信号完整性，即将提高电源完整性和信号完整性的电路集成在非易失性存储器裸片中，不会单独占用一层裸片的空间，因此不会增加堆叠存储器的高度。
本申请不限定非易失性存储阵列和外围电路的堆叠方式。在一种可能的实施方式中，如图8或图9所示，非易失性存储阵列521和外围电路522可以实现在一个非易失性存储器裸片的同一衬底上。如图9所示，非易失性存储阵列521可以包括第一非易失性存储阵列5211和第二非易失性存储阵列5212，第一非易失性存储阵列5211和第二非易失性存储阵列5212可以实现在同一层的外围电路522的两侧。需要说明的是， 本申请实施例不限定同一层的非易失性存储阵列的数目。
在另一种可能的实施方式中，如图10所示，非易失性存储阵列521和外围电路522可以实现在一个非易失性存储器裸片的不同层。例如，非易失性存储器裸片还包括衬底523、第一金属层组524和第二金属层组525。外围电路522实现在衬底523上，第一金属层组524、非易失性存储阵列521、第二金属层组525和衬底523依次堆叠在非易失性存储器裸片的不同层。第一金属层组524和第二金属层组525用于布置非易失性存储器裸片内的走线。
本申请不限定易失性存储器裸片51的层数，例如可以为8层、16层等。
本申请不限定非易失性存储阵列的存储单元类型，非易失性存储阵列的存储单元类型包括但不限于闪存、FeRAM、MRAM、PRAM、ReRAM等。
控制裸片53用于：将易失性存储器裸片51中的数据备份存储至非易失性存储器裸片52。或者，将非易失性存储器裸片52中的数据存储至易失性存储器裸片51。
在一种可能的实施方式中，在检测到工作电源断电时，控制裸片53控制外围电路522将易失性存储器裸片51中的数据存储至非易失性存储器裸片52。在检测到工作电源恢复供电时，控制裸片53控制外围电路522将非易失性存储器裸片52中的数据存储至易失性存储器裸片51。
示例性的，若工作电源突然断电，控制裸片53中的电源检测模块或其他电源检测模块检测到掉电事件，控制裸片53启动备用电源进入断电数据备份模式，控制裸片53将易失性存储器裸片51存储的部分或者全部数据存储至非易失性存储器裸片52中的第一存储区域，完成后可以关闭备用电源。若工作电源恢复供电，控制裸片53中的电源检测模块或其他电源检测模块检测到掉电恢复事件，控制裸片53将非易失性存储器裸片52中的第一存储区域中存储的数据恢复存储至易失性存储器裸片51。
在发生掉电事件时，存储系统不需要将易失性存储器中存储的数据备份至外部的非易失性存储器；在发生掉电恢复事件时，存储系统不需要将外部的非易失性存储器备份的数据存储至易失性存储器中。在堆叠存储器内部即可实现数据的备份和恢复，可以降低能量消耗，降低了对备用电源的要求，因此降低了成本。
在另一种可能的实施方式中，数据为程序运行时的检查点数据，在接收到检查点数据备份命令或者计时达到备份周期时，控制裸片53控制外围电路522将易失性存储器裸片51中的数据存储至非易失性存储器裸片52。在接收到检查点数据恢复命令时，控制外围电路522将非易失性存储器裸片52中的数据存储至易失性存储器裸片51。
示例性的，如图12所示，堆叠存储器41和处理器44可以封装在封装衬底上，堆叠存储器41和处理器44之间通过走线层中的总线电连接，并且堆叠存储器41和处理器44分别通过走线层与封装衬底电连接。
处理器按照备份周期定时向堆叠存储器的控制裸片53发送检查点数据备份命令，控制裸片53接收到检查点数据备份命令后，根据检查点数据备份命令中的参数，将易失性存储器裸片51中存储的检查点数据备份存储至非易失性存储器裸片52的第二存储区域，即控制裸片53根据处理器的指令对检查点数据进行备份。或者，控制裸片53计时达到备份周期时，将易失性存储器裸片51中存储的检查点数据备份存储至非易失性存储器裸片52的第二存储区域，即控制裸片53可以自主对检查点数据进行备 份。
当发生程序崩溃时，处理器向堆叠存储器的控制裸片53发送检查点数据恢复命令，控制裸片53接收到检查点数据恢复命令后，根据检查点数据恢复命令中的参数，将非易失性存储器裸片52的第二存储区域中存储的最新的检查点数据恢复存储至易失性存储器裸片51。
在对检查点数据进行周期性备份时，存储系统不需要将易失性存储器中存储的检查点数据备份至外部的非易失性存储器；在对检查点数据进行恢复时，存储系统不需要将外部的非易失性存储器备份的检查点数据存储至易失性存储器中。在堆叠存储器内部即可实现检查点数据的备份和恢复，可以降低能量消耗。
前文所述的第一存储区域和第二存储区域可以是相同区域或不同区域，当为不同区域时，该存储系统可以同时进行断电数据存储和恢复以及检查点数据存储和恢复。
在接收到检查点数据备份命令或者计时达到备份周期时，如果非易失性存储器裸片52中的空闲存储资源高于门限，则将当前的检查点数据存储至非易失性存储器裸片52的空闲存储资源，不覆盖最早的检查点数据。否则，按照先入先出(first input first output，FIFO)的顺序，将当前的检查点状态数据覆盖最早的检查点数据。
通过将该方法保留了混合型高带宽存储器原有的技术特点，集成度高、实现成本及难度低，在不增加裸片成本的基础上，仍可保证在底部控制裸片与顶部DRAM裸片之间传输的信号完整性和电源的完整性，确保具有高堆叠数的三维存储芯片可靠性。
另外，控制裸片将易失性存储器裸片中的数据存储至非易失性存储器裸片，实现了数据的备份；控制裸片将非易失性存储器裸片中的数据存储至易失性存储器裸片，实现了数据的恢复。不仅提高了数据存储的可靠性，并且通过在芯片内部实现数据备份和恢复，不必进行芯片之间的数据传输，降低了数据备份和恢复过程中能耗。
综上所述，本申请实施例提供的堆叠存储器及存储系统，堆叠存储器包括相堆叠的易失性存储器裸片、非易失性存储器裸片。非易失性存储器裸片包括非易失性存储阵列和外围电路。外围电路包括电源完整性电路和信号完整性电路，其中，电源完整性电路用于将从下层裸片获取的电源进行电源完整性优化后传输给上层裸片；信号完整性电路用于将从下层裸片获取的信号进行信号完整性优化后传输给上层裸片。非易失性存储阵列可以用于存储数据，外围电路可以用于提高堆叠存储器的底部裸片与顶部裸片之间的电源完整性和信号完整性，该外围电路没有单独占用一层裸片，因此防止堆叠存储器的电源完整性和信号完整性下降的同时不增加裸片的数目。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所 述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式来实现。该计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或者数据中心通过有线(例如同轴电缆、光纤、数字用户线(Digital Subscriber Line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可以用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)，光介质(例如，DVD)、或者半导体介质(例如固态硬盘(Solid State Disk，SSD))等。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种堆叠存储器，其特征在于，包括相堆叠的易失性存储器裸片、非易失性存储器裸片；其中，所述非易失性存储器裸片包括非易失性存储阵列和外围电路，所述外围电路包括电源完整性电路和信号完整性电路；
    所述电源完整性电路用于将从下层裸片获取的电源进行电源完整性优化后传输给上层裸片；所述电源完整性优化包括滤除电压噪声、降低IR压降中至少一项；
    所述信号完整性电路用于将从下层裸片获取的信号进行信号完整性优化后传输给上层裸片；所述信号完整性优化包括降低共模噪声、阻抗匹配中至少一项。
  2. 根据权利要求1所述的堆叠存储器，其特征在于，所述堆叠存储器还堆叠有控制裸片，所述控制裸片用于：
    控制所述外围电路将所述易失性存储器裸片中的数据存储至所述非易失性存储器裸片；或者，控制所述外围电路将所述非易失性存储器裸片中的数据存储至所述易失性存储器裸片。
  3. 根据权利要求2所述的堆叠存储器，其特征在于，所述控制裸片具体用于：
    在检测到工作电源断电时，控制所述外围电路将所述易失性存储器裸片中的数据存储至所述非易失性存储器裸片；
    在检测到所述工作电源恢复供电时，控制所述外围电路将所述非易失性存储器裸片中的数据存储至所述易失性存储器裸片。
  4. 根据权利要求2所述的堆叠存储器，其特征在于，所述数据为检查点数据，所述控制裸片具体用于：
    在接收到检查点数据备份命令或者计时达到备份周期时，控制所述外围电路将所述易失性存储器裸片中的数据存储至所述非易失性存储器裸片；
    在接收到检查点数据恢复命令时，控制所述外围电路将所述非易失性存储器裸片中的数据存储至所述易失性存储器裸片。
  5. 根据权利要求4所述的堆叠存储器，其特征在于，在接收到检查点数据备份命令或者计时达到备份周期时，所述控制裸片具体用于：
    如果所述非易失性存储器裸片中的空闲存储资源高于门限，则将当前的检查点状态数据存储至所述非易失性存储器裸片的空闲存储资源；
    否则，将当前的所述检查点状态数据覆盖最早的检查点状态数据。
  6. 根据权利要求1-5任一项所述的堆叠存储器，其特征在于，所述非易失性存储阵列和所述外围电路实现在所述非易失性存储器裸片的同一衬底上。
  7. 根据权利要求6所述的堆叠存储器，其特征在于，所述非易失性存储阵列包括第一非易失性存储阵列和第二非易失性存储阵列，所述第一非易失性存储阵列和所述第二非易失性存储阵列实现在同一层的所述外围电路的两侧。
  8. 根据权利要求1-5任一项所述的堆叠存储器，其特征在于，所述非易失性存储阵列和所述外围电路实现在所述非易失性存储器裸片的不同层。
  9. 根据权利要求8所述的堆叠存储器，其特征在于，所述非易失性存储器裸片还包括衬底、第一金属层组和第二金属层组，所述外围电路实现在所述衬底上，所述第一金属层组、所述非易失性存储阵列、所述第二金属层组和所述衬底依次堆叠在所述 非易失性存储器裸片的不同层。
  10. 根据权利要求1-9任一项所述的堆叠存储器，其特征在于，所述非易失性存储阵列的存储单元类型包括闪存、铁电随机存取存储器、磁存储器、相变随机存取存储器或阻变随机存取存储器。
  11. 根据权利要求1-10任一项所述的堆叠存储器，其特征在于，所述易失性存储器裸片包括第一易失性存储器裸片和第二易失性存储器裸片，所述第一易失性存储器裸片、所述非易失性存储器裸片、所述第二易失性存储器裸片依次堆叠。
  12. 根据权利要求1-10任一项所述的堆叠存储器，其特征在于，所述易失性存储器裸片包括第一易失性存储器裸片和第二易失性存储器裸片，所述非易失性存储器裸片包括第一非易失性存储器裸片和第二非易失性存储器裸片，所述第一易失性存储器裸片、所述第一非易失性存储器裸片、所述第二易失性存储器裸片、第二非易失性存储器裸片依次堆叠。
  13. 根据权利要求1-10任一项所述的堆叠存储器，其特征在于，所述易失性存储器裸片、所述非易失性存储器裸片依次堆叠。
  14. 一种存储系统，其特征在于，包括：如权利要求1-13任一项所述的堆叠存储器、工作电源和备用电源；
    在所述存储系统正常工作时由所述工作电源对所述堆叠存储器的工作进行供电；在所述工作电源断电时，切换至由所述备用电源对所述堆叠存储器的工作进行供电；在所述工作电源恢复供电时，重新切换至由所述工作电源对所述堆叠存储器的工作进行供电。
PCT/CN2020/098645 2020-06-28 2020-06-28 堆叠存储器及存储系统 WO2022000150A1 (zh)

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