CN109087862A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
CN109087862A
CN109087862A CN201710447863.7A CN201710447863A CN109087862A CN 109087862 A CN109087862 A CN 109087862A CN 201710447863 A CN201710447863 A CN 201710447863A CN 109087862 A CN109087862 A CN 109087862A
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layer
doped region
semiconductor devices
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gate structure
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CN201710447863.7A
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CN109087862B (zh
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201710447863.7A priority Critical patent/CN109087862B/zh
Priority to US16/003,949 priority patent/US10541314B2/en
Publication of CN109087862A publication Critical patent/CN109087862A/zh
Priority to US16/708,754 priority patent/US10847632B2/en
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Abstract

一种半导体器件及其形成方法，其中方法包括：提供基底；形成掺杂区、初始覆盖层和介质层，掺杂区位于基底中，初始覆盖层位于掺杂区表面，介质层位于初始覆盖层和基底上；在介质层中形成通孔，所述通孔暴露出初始覆盖层的表面；刻蚀通孔底部的初始覆盖层，使初始覆盖层形成目标覆盖层，所述目标覆盖层包括通孔底部暴露出的硅化区，硅化区的厚度小于初始覆盖层的厚度；采用自对准硅化工艺使硅化区形成金属硅化物层，金属硅化物层与掺杂区接触。所述方法使得半导体器件的性能得到提高。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体器件及其形成方法。
背景技术
MOS晶体管是现代集成电路中最重要的元件之一。MOS晶体管的基本结构包括：半导体衬底；位于半导体衬底表面的栅极结构，位于栅极结构一侧半导体衬底内的源区和位于栅极结构另一侧半导体衬底内的漏区。MOS晶体管的工作原理是：通过在栅极结构施加电压，调节通过栅极结构底部沟道的电流来产生开关信号。
然而，现有技术形成的MOS晶体管的性能较差。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法，以提高半导体器件的性能。
为解决上述问题，本发明提供一种半导体器件的形成方法，包括：提供基底；形成掺杂区、初始覆盖层和介质层，掺杂区位于基底中，初始覆盖层位于掺杂区表面，介质层位于初始覆盖层和基底上；在介质层中形成通孔，所述通孔暴露出初始覆盖层的表面；刻蚀通孔底部的初始覆盖层，使初始覆盖层形成目标覆盖层，所述目标覆盖层包括通孔底部暴露出的硅化区，硅化区的厚度小于初始覆盖层的厚度；采用自对准硅化工艺使硅化区形成金属硅化物层，金属硅化物层与掺杂区接触。
可选的，还包括：在形成通孔之前，形成栅极结构，栅极结构位于基底上，掺杂区分别位于栅极结构两侧的基底中，介质层还位于栅极结构上；所述通孔分别位于栅极结构两侧的介质层中。
可选的，所述基底包括半导体衬底和位于半导体衬底上的鳍部；所述栅极结构横跨所述鳍部、覆盖鳍部的部分侧壁表面和部分顶部表面；所述掺杂区分别位于栅极结构两侧的鳍部中。
可选的，刻蚀通孔底部的初始覆盖层的工艺为各向异性干刻工艺。
可选的，所述初始覆盖层和所述目标覆盖层的材料为掺杂导电离子的多晶硅。
可选的，所述初始覆盖层的厚度为8纳米～15纳米。
可选的，所述自对准硅化工艺包括：在通孔底部露出的硅化区表面形成金属层；进行退火处理，使金属层和硅化区反应以形成金属硅化物层。
可选的，所述金属层的材料包括钛；所述金属硅化物层的材料包括硅化钛。
可选的，所述硅化区的厚度为2纳米～6纳米。
可选的，所述介质层包括第一层间介质层和第二层间介质层；形成所述栅极结构、掺杂区、初始覆盖层和介质层的方法包括：在所述基底上形成伪栅极结构；在伪栅极结构两侧的基底中分别形成预掺杂层；在所述预掺杂层表面形成初始覆盖层，初始覆盖层中具有导电离子；进行退火工艺，使初始覆盖层中的导电离子向预掺杂层扩散，使预掺杂层形成掺杂区；形成第一层间介质层，第一层间介质层覆盖伪栅极结构侧壁和初始覆盖层，所述第一层间介质层还位于基底上；形成第一层间介质层后，去除伪栅极结构，形成栅极开口；在所述栅极开口中形成栅极结构；在第一层间介质层和栅极结构上形成第二层间介质层。
可选的，所述初始覆盖层的厚度为8纳米～15纳米；在进行退火工艺之前，所述初始覆盖层中导电离子的浓度为5E20tom/cm3～5E21atom/cm3，进行退火工艺之后，所述掺杂区中导电离子的浓度为3E20atom/cm3～1E21atom/cm3。
可选的，所述半导体器件为P型晶体管；所述预掺杂层的材料为锗硅；所述掺杂区的材料为含有导电离子的锗硅，所述导电离子的导电类型为P型。
可选的，还包括：在进行所述自对准硅化工艺之前，还包括：对通孔底部暴露出的硅化区进行非晶化处理。
可选的，所述非晶化处理的方法为离子注入工艺。
可选的，所述离子注入工艺采用的离子为锗离子或者碳离子。
可选的，还包括：形成所述金属硅化物层后，在所述通孔中形成插塞。
本发明还提供一种半导体器件，包括：基底；位于基底中的掺杂区；位于掺杂区表面的目标覆盖层，所述目标覆盖层包括位于掺杂区表面的硅化区和位于掺杂区表面的非硅化区，硅化区与非硅化区邻接，硅化区的厚度小于非硅化区的厚度；位于掺杂区表面的金属硅化物层，金属硅化物层位于目标覆盖层硅化区中；位于目标覆盖层、金属硅化物层和基底上的介质层；位于介质层中的通孔，所述通孔暴露出所述金属硅化物层。
可选的，所述金属硅化物层的材料包括硅化钛。
可选的，所述目标覆盖层的材料为掺杂导电离子的多晶硅。
与现有技术相比，本发明的技术方案具有以下优点：
本发明技术方案提供的半导体器件的形成方法中，所述金属硅化物层表面用于和插塞接触。所述金属硅化物层和掺杂区直接接触，而金属硅化物层材料的导电性能优于初始覆盖层的材料的导电性能，以降低自插塞至掺杂区电流路径上插塞和掺杂区之间的电阻。由于刻蚀通孔底部的初始覆盖层，使目标覆盖层中硅化区的厚度小于初始覆盖层的厚度，因此硅化区的厚度较小。而通孔底部的硅化区用于在自对准硅化工艺中形成金属硅化物层，因此使通孔底部的金属硅化物层的厚度较小。进而在自金属硅化物层至掺杂区的电流传导方向上，金属硅化物层的电阻较小，以降低插塞和掺杂区之间的接触电阻。
附图说明
图1至图8是本发明一实施例中半导体器件形成过程的结构示意图。
具体实施方式
正如背景技术所述，现有技术形成的半导体器件的性能较差。
一种半导体器件的形成方法，包括：提供基底；形成掺杂区、覆盖层和介质层，掺杂区位于基底中，覆盖层位于掺杂区表面，覆盖层中具有导电离子，覆盖层中的导电离子用于通过退火工艺向掺杂区中扩散；介质层位于覆盖层和基底上；在介质层中形成通孔，所述通孔暴露出覆盖层的表面；采用自对准硅化工艺使通孔底部的覆盖层形成金属硅化物层；在通孔中形成插塞，金属硅化物层和插塞接触。
所述自对准硅化工艺的过程包括：在通孔底部的覆盖层表面形成金属层；进行退火处理，使金属层和覆盖层反应而形成金属硅化物层。
然而，上述方法形成的半导体器件的性能较差，经研究发现，原因在于：
所述金属硅化物层需要和掺杂区直接接触，即在插塞和掺杂区之间的覆盖层全部转化为金属硅化物层。而金属硅化物层材料的导电性能优于初始覆盖层的材料的导电性能，因此，金属硅化物层和掺杂区直接接触，能够降低自插塞至掺杂区电流路径上插塞和掺杂区之间的电阻。
所述覆盖层中的导电离子用于通过退火工艺向掺杂区中扩散，从而使得掺杂区中具有导电离子。为了使退火工艺后掺杂区中导电离子具有较高的浓度，不仅需要在退火工艺之前覆盖层中的导电离子的浓度较高，而且需要覆盖层的厚度较厚，以使覆盖层容纳较多总量的高浓度的导电离子，这样，有足够的导电离子在退火工艺中扩散进入掺杂区中。
由于覆盖层的厚度较厚，且需要金属硅化物层和掺杂区直接接触，因此金属硅化物层的厚度较厚，在插塞至掺杂区的电流传导方向上，金属硅化物层的电阻较大，导致插塞和掺杂区之间的接触电阻较大，降低了半导体器件的性能。
为了解决上述问题，本发明提供一种半导体器件的形成方法，刻蚀通孔底部的初始覆盖层，使初始覆盖层形成目标覆盖层，所述目标覆盖层包括通孔底部暴露出的硅化区，硅化区的厚度小于初始覆盖层的厚度；之后，采用自对准硅化工艺使硅化区形成金属硅化物层，金属硅化物层与掺杂区接触。所述方法使半导体器件的性能提高。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1至图8是本发明一实施例中半导体器件形成过程的结构示意图。
参考图1，提供基底100。
本实施例中，所述半导体器件为鳍式场效应晶体管。在其它实施例中，半导体器件为平面式的MOS晶体管、三级管或二极管。
本实施例中，所述基底100包括半导体衬底101和位于半导体衬底101上的鳍部102。在其它实施例中，所述基底为平面式的半导体衬底。
所述半导体衬底101可以是单晶硅，多晶硅或非晶硅；所述半导体衬底101也可以是硅、锗、锗化硅、砷化镓等半导体材料；所述半导体衬底101可以是单层结构，半导体衬底101也可以是复合结构，如绝缘体上硅；所述半导体衬底101还可以是其它半导体材料，这里不再一一举例。本实施例中，所述半导体衬底101的材料为硅。
所述鳍部102通过图形化半导体衬底101而形成。或者，在半导体衬底101上形成鳍部材料层，通过图形化鳍部材料层而形成鳍部102。
本实施例中，所述半导体衬底101上还具有覆盖鳍部102部分侧壁的隔离结构103，隔离结构103的顶部表面低于鳍部102的顶部表面。所述隔离结构103的材料包括氧化硅。
所述鳍部102的数量为一个或多个。
继续参考图1，形成掺杂区110、初始覆盖层120和介质层130，掺杂区110位于基底100中，初始覆盖层120位于掺杂区110表面，介质层130位于初始覆盖层120和基底100上。
本实施例中，还包括：形成栅极结构140，栅极结构140位于基底100上，掺杂区110分别位于栅极结构140两侧的基底100中，介质层130还位于栅极结构140上。
所述介质层130和栅极结构140还位于隔离结构103上。
具体的，所述栅极结构140横跨所述鳍部102、覆盖鳍部102的部分侧壁表面和部分顶部表面；所述掺杂区110分别位于栅极结构140两侧的鳍部102中。
本实施例中，在栅极结构140的延伸方向上，栅极结构140横跨多个鳍部102。在其它实施例中，在栅极结构的延伸方向上，栅极结构横跨一个鳍部。
所述栅极结构140包括横跨鳍部102的栅介质层141和位于栅介质层141上的栅电极层142。所述栅介质层141位于隔离结构103部分表面、覆盖鳍部102的部分顶部表面和部分侧壁表面。
所述栅介质层141的材料为高K(K大于3.9)介质材料。所述栅电极层142的材料为金属。
所述介质层130包括第一层间介质层131和第二层间介质层132，第一层间介质层131位于半导体衬底101和隔离结构103上、覆盖栅极结构140侧壁、鳍部102和初始覆盖层120，第二层间介质层132位于第一层间介质层131上和栅极结构140的顶部上。
所述介质层130的材料包括氧化硅。
形成所述栅极结构140、掺杂区110、初始覆盖层120和介质层130的方法包括：在所述基底100上形成伪栅极结构，具体的，在半导体衬底101和隔离结构103上形成伪栅极结构，伪栅极结构横跨所述鳍部102、覆盖鳍部102的部分侧壁表面和部分顶部表面；在伪栅极结构两侧的基底100中分别形成预掺杂层，具体的，在伪栅极结构两侧鳍部102中分别形成预掺杂层；在所述预掺杂层表面形成初始覆盖层120，初始覆盖层120中具有导电离子；进行退火工艺，使初始覆盖层120中的导电离子向预掺杂层扩散，使预掺杂层形成掺杂区110；形成第一层间介质层131，第一层间介质层131覆盖伪栅极结构侧壁和初始覆盖层120，所述第一层间介质层131还位于基底100上；形成第一层间介质层131后，去除伪栅极结构，形成栅极开口；在所述栅极开口中形成栅极结构140；在第一层间介质层131和栅极结构140上形成第二层间介质层132。
所述初始覆盖层120的材料为掺杂导电离子的多晶硅。
在进行退火工艺之前，所述初始覆盖层120中导电离子的浓度为5E20tom/cm3～5E21atom/cm3，进行退火工艺之后，所述掺杂区120中导电离子的浓度为3E20atom/cm3～1E21atom/cm3。
在一个实施例中，所述半导体器件为P型晶体管；所述预掺杂层的材料为锗硅，所述掺杂区110的材料为含有导电离子的锗硅，所述导电离子的导电类型为P型，如硼离子或铟离子。
在一个实施例中，预掺杂层中锗的摩尔数与硅的摩尔数的比例为35％～55％。
在另一个实施例中，所述半导体器件为N型晶体管；所述预掺杂层的材料为硅，所述掺杂区110的材料为含有导电离子的硅，所述导电离子的导电类型为N型，如磷离子或砷离子。
本实施例中，初始覆盖层120中的导电离子向预掺杂层扩散，使得掺杂区110中具有导电离子，优点包括：避免通过离子注入的方式向预掺杂层中注入导电离子，避免注入损耗；当所述半导体器件的类型为P型时，若通过原位掺杂的方法使掺杂区110中具有导电离子，由于预掺杂层中锗的摩尔比例较高，因此导电离子较难通过原位掺杂的方法进入预掺杂层110中，而本实施例中，在退火工艺之前，初始覆盖层120中的导电离子具有高的浓度，且通过在退火工艺中使初始覆盖层120中的导电离子容易扩散进入预掺杂层中，从而实现掺杂区110中具有较高的导电离子浓度。
一方面，在退火工艺之前，初始覆盖层120中的导电离子具有高的浓度，另一方面，在退火工艺采用的温度较高，对导电离子的扩散有较大的驱动作用。因此，在退火工艺中使初始覆盖层120中的导电离子容易扩散进入掺杂区110中。
所述退火工艺采用的温度比采用外延工艺形成掺杂区110采用的温度高。在一个具体的实施例中，所述退火工艺采用的温度为900摄氏度～1100摄氏度，如1000摄氏度。
在一个实施例中，所述初始覆盖层的厚度为8纳米～15纳米。若所述初始覆盖层的厚度大于15纳米，导致工艺浪费，寄生电容较大，且使得栅极结构140横跨的相邻鳍部202之间可填充的空间较小，第一层间介质层131较难填充在栅极结构140横跨的相邻鳍部202之间；若所述初始覆盖层的厚度小于8纳米，导致初始覆盖层120中的导电离子的总量较少，初始覆盖层120中用于给掺杂区110中扩散的导电离子总数较少，难以在掺杂区110中形成较高浓度的导电离子。
参考图2，在介质层130中形成通孔150，所述通孔150暴露出初始覆盖层120的表面。
具体的，在栅极结构140两侧的介质层130中分别形成通孔150，所述通孔150暴露出初始覆盖层120的表面。
参考图3，刻蚀通孔150底部的初始覆盖层120，使初始覆盖层120形成目标覆盖层121，所述目标覆盖层121包括通孔150底部暴露出的硅化区，硅化区的厚度小于初始覆盖层120的厚度。
刻蚀通孔150底部的初始覆盖层120的工艺为各向异性干刻工艺。
所述目标覆盖层121包括位于掺杂区110表面的硅化区和位于掺杂区110表面的非硅化区，硅化区与非硅化区邻接，硅化区的厚度小于非硅化区的厚度。
所述初始覆盖层120在后续的自对准硅化工艺中用于形成金属硅化物层，而金属硅化物层的厚度在工艺设计中的厚度较小。为了实现金属硅化物层和掺杂区110直接接触，因此需要降低通孔150底部的初始覆盖层120的厚度。
本实施例中，在后续进行自对准硅化工艺之前，还包括：对通孔150底部暴露出的硅化区进行非晶化处理。在其它实施例中，对通孔底部暴露出的硅化区不形成非晶化处理。
参考图4，对通孔150底部暴露出的硅化区进行非晶化处理。
所述非晶化处理的作用包括：使通孔150底部暴露出的硅化区的材料表面呈非晶态，从而使后续在形成的金属硅化物层的表面粗糙度较低。
对通孔150底部暴露出的硅化区进行非晶化处理，使得在通孔150底部的硅化区表面形成非晶层122。
后续金属硅化物层的表面粗糙度较低，以进一步降低后续插塞和掺杂区110之间的接触电阻。
所述非晶化处理包括离子注入工艺。
本实施例中，所述离子注入工艺采用的离子为碳离子或锗离子，原因为：碳离子或锗离子为即不属于N型离子，也不属于P型离子，因此所述碳离子或锗离子对掺杂区110的电学性能影响较小。
接着，采用自对准硅化工艺使硅化区形成金属硅化物层，金属硅化物层与掺杂区110接触。
所述自对准硅化工艺包括：在通孔150底部露出的硅化区表面形成金属层；进行退火处理，使金属层和硅化区反应以形成金属硅化物层。
本实施例中，还包括：在形成金属硅化物层的过程中，形成阻挡层，所述阻挡层位于所述通孔150侧壁和金属硅化物层表面。在其它实施例中，形成金属硅化物层后，形成阻挡层。
下面参考图5至图6介绍形成金属硅化物层和阻挡层的过程。
参考图5，在通孔150底部露出的硅化区表面、通孔150侧壁和介质层130上形成金属层151；在所述金属层151表面形成阻挡层152。
所述金属层151的材料包括钛。所述阻挡层152的材料包括氮化钛。
形成所述金属层151的工艺为沉积工艺，如溅射工艺。形成所述阻挡层152的工艺为沉积工艺，如溅射工艺、化学气相沉积工艺或原子层沉积工艺。
参考图6，进行退火处理，使金属层和硅化区反应以形成金属硅化物层160，金属硅化物层160与掺杂区110接触。
当所述金属层151的材料为钛时，所述金属硅化物层160的材料为硅化钛(TiSiX)。在此情况下，金属层151和硅化区反应形成的金属硅化物层160中的缺陷较少。
所述金属硅化物层160和掺杂区110直接接触，即在后续插塞和掺杂区110之间的硅化区全部转化为金属硅化物层160。而金属硅化物层160材料的导电性能优于硅化区的材料的导电性能，因此，金属硅化物层160和掺杂区110直接接触，能够降低自插塞至掺杂区电流路径上插塞和掺杂区110之间的电阻。
本实施例中，刻蚀通孔150底部的初始覆盖层120，使目标覆盖层121中硅化区的厚度小于初始覆盖层120的厚度，因此硅化区的厚度较小。而通孔150底部的硅化区用于在自对准硅化工艺中形成金属硅化物层160，因此使金属硅化物层160的厚度较小。进而，在自插塞至掺杂区110的电流传导方向上，金属硅化物层160的电阻较小，以降低插塞和掺杂区110之间的接触电阻。
所述硅化区的厚度不能过小，否则导致硅化区和金属层反应相变的难度较大，难以发生相变而形成金属硅化物层160。
当金属层的材料为钛时，所述硅化区的厚度需要大于等于2纳米。在一个实施例中，所述硅化区的厚度为2纳米～6纳米。
形成所述金属硅化物层160后，在所述通孔150中形成插塞。
参考图7，在通孔150中(参考图6)以及介质层130上形成插塞材料层170。
所述插塞材料层170的材料为金属，如钨。
形成所述插塞材料层170的工艺为沉积工艺，如化学气相沉积工艺。
本实施例中，所述插塞材料层170还覆盖通孔150侧壁的金属层151和阻挡层152、以及介质层130顶部的金属层151和阻挡层152。
参考图8，去除介质层130上的插塞材料层170，以形成插塞171。
在去除介质层130上的插塞材料层170的过程中，去除介质层130顶部的金属层151和阻挡层152，简化了工艺。
形成插塞171后，插塞171和金属硅化物层160之间、以及插塞171和介质层130之间具有阻挡层152，所述阻挡层152用于阻挡插塞171中原子扩散。
相应的，本实施例还提供一种采用上述方法形成的半导体器件，请参考图6，包括：基底；位于基底100中的掺杂区110；位于掺杂区110表面的目标覆盖层121，所述目标覆盖层121包括位于掺杂区110表面的硅化区和位于掺杂区110表面的非硅化区，硅化区与非硅化区邻接，硅化区的厚度小于非硅化区的厚度；位于掺杂区110表面的金属硅化物层160，金属硅化物层160位于目标覆盖层硅化区中；位于目标覆盖层121、金属硅化物层160和基底100上的介质层130；位于介质层130中的通孔150，所述通孔150暴露出所述金属硅化物层160。
所述金属硅化物层160的材料包括硅化钛。
所述目标覆盖层121的材料为掺杂导电离子的多晶硅。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (19)

1.一种半导体器件的形成方法，其特征在于，包括：
提供基底；
形成掺杂区、初始覆盖层和介质层，掺杂区位于基底中，初始覆盖层位于掺杂区表面，介质层位于初始覆盖层和基底上；
在介质层中形成通孔，所述通孔暴露出初始覆盖层的表面；
刻蚀通孔底部的初始覆盖层，使初始覆盖层形成目标覆盖层，所述目标覆盖层包括通孔底部暴露出的硅化区，硅化区的厚度小于初始覆盖层的厚度；
采用自对准硅化工艺使硅化区形成金属硅化物层，金属硅化物层与掺杂区接触。
2.根据权利要求1所述的半导体器件的形成方法，其特征在于，还包括：在形成通孔之前，形成栅极结构，栅极结构位于基底上，掺杂区分别位于栅极结构两侧的基底中，介质层还位于栅极结构上；所述通孔分别位于栅极结构两侧的介质层中。
3.根据权利要求2所述的半导体器件的形成方法，其特征在于，所述基底包括半导体衬底和位于半导体衬底上的鳍部；所述栅极结构横跨所述鳍部、覆盖鳍部的部分侧壁表面和部分顶部表面；所述掺杂区分别位于栅极结构两侧的鳍部中。
4.根据权利要求1所述的半导体器件的形成方法，其特征在于，刻蚀通孔底部的初始覆盖层的工艺为各向异性干刻工艺。
5.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述初始覆盖层和所述目标覆盖层的材料为掺杂导电离子的多晶硅。
6.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述初始覆盖层的厚度为8纳米～15纳米。
7.根据权利要求1所述的半导体器件的形成方法，其特征在于，所述自对准硅化工艺包括：在通孔底部露出的硅化区表面形成金属层；进行退火处理，使金属层和硅化区反应以形成金属硅化物层。
8.根据权利要求7所述的半导体器件的形成方法，其特征在于，所述金属层的材料包括钛；所述金属硅化物层的材料包括硅化钛。
9.根据权利要求8所述的半导体器件的形成方法，其特征在于，所述硅化区的厚度为2纳米～6纳米。
10.根据权利要求2所述的半导体器件的形成方法，其特征在于，所述介质层包括第一层间介质层和第二层间介质层；形成所述栅极结构、掺杂区、初始覆盖层和介质层的方法包括：在所述基底上形成伪栅极结构；在伪栅极结构两侧的基底中分别形成预掺杂层；在所述预掺杂层表面形成初始覆盖层，初始覆盖层中具有导电离子；进行退火工艺，使初始覆盖层中的导电离子向预掺杂层扩散，使预掺杂层形成掺杂区；形成第一层间介质层，第一层间介质层覆盖伪栅极结构侧壁和初始覆盖层，所述第一层间介质层还位于基底上；形成第一层间介质层后，去除伪栅极结构，形成栅极开口；在所述栅极开口中形成栅极结构；在第一层间介质层和栅极结构上形成第二层间介质层。
11.根据权利要求10所述的半导体器件的形成方法，其特征在于，所述初始覆盖层的厚度为8纳米～15纳米；在进行退火工艺之前，所述初始覆盖层中导电离子的浓度为5E20tom/cm3～5E21atom/cm3，进行退火工艺之后，所述掺杂区中导电离子的浓度为3E20atom/cm3～1E21atom/cm3。
12.根据权利要求10所述的半导体器件的形成方法，其特征在于，所述半导体器件为P型晶体管；所述预掺杂层的材料为锗硅；所述掺杂区的材料为含有导电离子的锗硅，所述导电离子的导电类型为P型。
13.根据权利要求1所述的半导体器件的形成方法，其特征在于，还包括：在进行所述自对准硅化工艺之前，还包括：对通孔底部暴露出的硅化区进行非晶化处理。
14.根据权利要求13所述的半导体器件的形成方法，其特征在于，所述非晶化处理的方法为离子注入工艺。
15.根据权利要求14所述的半导体器件的形成方法，其特征在于，所述离子注入工艺采用的离子为锗离子或者碳离子。
16.根据权利要求1所述的半导体器件的形成方法，其特征在于，还包括：形成所述金属硅化物层后，在所述通孔中形成插塞。
17.一种半导体器件，其特征在于，包括：
基底；
位于基底中的掺杂区；
位于掺杂区表面的目标覆盖层，所述目标覆盖层包括位于掺杂区表面的硅化区和位于掺杂区表面的非硅化区，硅化区与非硅化区邻接，硅化区的厚度小于非硅化区的厚度；
位于掺杂区表面的金属硅化物层，金属硅化物层位于目标覆盖层硅化区中；
位于目标覆盖层、金属硅化物层和基底上的介质层；
位于介质层中的通孔，所述通孔暴露出所述金属硅化物层。
18.根据权利要求17所述的半导体器件，其特征在于，所述金属硅化物层的材料包括硅化钛。
19.根据权利要求17所述的半导体器件，其特征在于，所述目标覆盖层的材料为掺杂导电离子的多晶硅。
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