CN109037202B - 具有多栅极晶体管结构的半导体装置 - Google Patents

具有多栅极晶体管结构的半导体装置 Download PDF

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CN109037202B
CN109037202B CN201810563690.XA CN201810563690A CN109037202B CN 109037202 B CN109037202 B CN 109037202B CN 201810563690 A CN201810563690 A CN 201810563690A CN 109037202 B CN109037202 B CN 109037202B
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metal line
region
semiconductor device
gate
active region
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CN109037202A (zh
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金孝真
千宽永
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本申请公开一种半导体装置。所述半导体装置包括：单元区，其包括在第一方向上延伸的第一有源区和第二有源区及其之间的分离区。单元区具有第一宽度。第一栅极结构和第二栅极结构布置在单元区上，所述二者在第一方向上彼此间隔开，并且在第二方向上延伸。第一金属线和第二金属线布置在单元区上，所述二者在第一方向上延伸，并且彼此间隔开第一间距。第一金属线和第二金属线中的每一个具有第二宽度。第一栅极接触件将第一栅极结构与第一金属线电连接。第一栅极接触件的至少一部分覆盖分离区。第二栅极接触件将第二栅极结构与第二金属线电连接。第二栅极接触件的至少一部分覆盖分离区。第一宽度除以第一间距和第二宽度之和的结果为六或更小。

Description

具有多栅极晶体管结构的半导体装置
相关申请的交叉引用
本申请要求于2017年6月9日在韩国知识产权局提交的韩国专利申请No.10-2017-0072391的权益，该申请的公开内容通过引用方式整体并入本文。
技术领域
本公开涉及半导体装置。
背景技术
对于半导体装置密度增大，已提出多栅极晶体管作为缩放技术之一，根据该技术，在衬底上形成鳍形或纳米线形的多沟道有源图案(或硅体)，随后在多沟道有源图案的表面上形成栅极。
这种多栅极晶体管由于其使用三维沟道而允许容易的缩放。此外，可提高电流控制能力而不需要增加多栅极晶体管的栅极长度。这种结构可有效地抑制其中沟道区的电势受到漏极电压的影响的短沟道效应(SCE)。
发明内容
本公开的示例性实施例可解决现有技术的问题。示例性实施例可提供一种半导体装置结构，其能够降低在由单元区的宽度、金属线之间的间距和金属线的宽度之间的关系限定的单元区中，将栅极接触件与源极/漏极接触件分离的工艺的难度水平。
一些实施例提供了一种半导体装置，该半导体装置包括：单元区，其包括在第一方向上延伸的第一有源区和第二有源区以及所述第一有源区与第二有源区之间的分离区。所述单元区在垂直于第一方向的第二方向上具有第一宽度。第一栅极结构和第二栅极结构布置在所述单元区上，所述二者在第一方向上彼此间隔开，并且在第二方向上延伸。第一金属线和第二金属线布置在单元区上，所述二者在第一方向上延伸，并且在第二方向上彼此间隔开第一间距。第一金属线和第二金属线中的每一个在第二方向上具有第二宽度。第一栅极接触件将第一栅极结构与第一金属线电连接。第一栅极接触件的至少一部分覆盖所述分离区。第二栅极接触件将第二栅极结构与第二金属线电连接。第二栅极接触件的至少一部分覆盖所述分离区。第一宽度除以第一间距和第二宽度之和的结果为六或更小。
其它实施例提供了一种半导体装置，该半导体装置包括：单元区，其包括第一有源区、第二有源区和所述第一有源区与第二有源区之间的分离区。多条金属线布置在所述单元区上，所述金属线在第一方向上延伸，并且在垂直于第一方向的第二方向上彼此间隔开。栅极结构布置为横向于所述多条金属线，并且在第二方向上延伸。栅极接触件至少部分地覆盖所述分离区，并且将所述多条金属线中的至少一条与栅极结构电连接。在所述第一有源区、分离区和第二有源区上在第二方向上彼此间隔开的所述多条金属线的数量为三或四。
另一些实施例提供了一种半导体装置，该半导体装置包括：单元区，其包括在第一方向上延伸的第一有源区和第二有源区以及形成在所述第一有源区与第二有源区之间的分离区，所述单元区在垂直于第一方向的第二方向上具有第一宽度。第一栅极结构和第二栅极结构布置在所述单元区上，所述二者在第一方向上彼此间隔开，并且在第二方向上延伸。第一金属线覆盖所述第一有源区，在第一方向上延伸，并且在第二方向上具有第二宽度。第二金属线至少部分地覆盖所述分离区，在第二方向上与第一金属线间隔开第一间距，并且在第一方向上延伸。第三金属线至少部分地覆盖所述分离区，在第二方向上与第二金属线间隔开第二间距，并且在所述第一方向上延伸。第四金属线覆盖第二有源区，在第二方向上与第三金属线间隔开第三间距，并且在第一方向上延伸。第一栅极接触件将第一栅极结构与第二金属线电连接。第二栅极接触件将第二栅极结构与第三金属线电连接。所述第一、第二和第三间距基本相同，并且第一宽度除以第一间距和第二宽度之和的结果为六或更小。
附图说明
通过参照附图来详细描述本公开的示例性实施例，本公开的以上和其它目的、特征和优点将对于本领域普通技术人员变得更显而易见。
图1是根据一些实施例的半导体装置的布局图。
图2是示出图1的布局图的第一级制程(first level step)的布局的布局图。
图3是示出图1的布局图的第一级制程和第二级制程的布局的布局图。
图4是示出图1的布局图的第三级制程的布局的布局图。
图5是沿着图2的线A-A截取的剖视图。
图6是沿着图2的线B-B截取的剖视图。
图7是根据本公开的其它实施例的半导体装置的布局图。
图8是根据本公开的另一些实施例的半导体装置的布局图。
图9是根据另一些实施例的半导体装置的布局图。
图10是根据另一些实施例的半导体装置的布局图。
图11和图12是根据另一些实施例的半导体装置的剖视图。
具体实施方式
下文中，将参照图1至图6来描述根据本公开的一些实施例的半导体装置。
图1是根据本公开的一些实施例的半导体装置的布局图。图2是示出图1的布局图的第一级制程的布局的布局图。图3是示出图1的布局图的第一级制程和第二级制程的布局的布局图。图4是示出图1的布局图的第三级制程的布局的布局图。图5是沿着图2的线A-A截取的剖视图。图6是沿着图2的线B-B截取的剖视图。
参照图1至图6，根据本公开的一些实施例的半导体装置包括单元区CR、第一有源区AR1、第二有源区AR2、分离区STI、第一栅极结构G1、第二栅极结构G2、第三栅极结构G3和第四栅极结构G4、第一鳍式图案F1、第二鳍式图案F2、第三鳍式图案F3和第四鳍式图案F4、第一金属线M11、第二金属线M12、第三金属线M13和第四金属线M14、第五金属线M5、第六金属线M6、第一栅极接触件CB11、第二栅极接触件CB12、源极/漏极区SDR以及第一源极/漏极接触件CA1、第二源极/漏极接触件CA2、第三源极/漏极接触件CA3、第四源极/漏极接触件CA4、第五源极/漏极接触件CA5和第六源极/漏极接触件CA6。
单元区CR可包括第一有源区AR1、第二有源区AR2和分离区STI。具体地说，单元区CR可包括第一电源导轨区、在第二方向Y上邻近于第一电源导轨区的第一有源区AR1、在第二方向Y上邻近于第一有源区AR1的分离区STI、在第二方向Y上邻近于分离区STI的第二有源区AR2和在第二方向上邻近于第二有源区AR2的第二电源导轨区。
在这种情况下，第一电源导轨区、第一有源区AR1、分离区STI、第二有源区AR2和第二电源导轨区可各自形成为在第一方向X上延伸。
单元区CR可代表一个单元。单元区CR在第二方向Y上具有第一宽度Hc。
在第一电源导轨区、第二电源导轨区和分离区STI中的每一个中，可布置在第一方向上延伸的伪鳍式图案。如本文所用，“伪鳍式图案”意指未被积极地(actively)使用的鳍式图案。然而，为了解释方便，在图1至图3中，未示出伪鳍式图案。
第一电源导轨区和第二电源导轨区可用于将功率供应至整个单元区CR。例如，第一电源导轨区可供应正电压，而第二电源导轨区可供应负电压。然而，实施例不限于此。
第一有源区AR1可包括第一鳍式图案F1和第二鳍式图案F2，所述二者中的每一个在第一方向X上延伸，并且在第三方向Z上从衬底(图5的101)突出。第一鳍式图案F1可在第二方向Y上与第二鳍式图案F2间隔开。
第二有源区AR2可包括第三鳍式图案F3和第四鳍式图案F4，所述二者中的每一个在第一方向X上延伸，并且在第三方向Z上从衬底(图5的101)突出。第三鳍式图案F3可在第二方向Y上与第四鳍式图案F4间隔开。
第一栅极结构G1、第二栅极结构G2、第三栅极结构G3和第四栅极结构G4可在单元区CR上在第一方向X上彼此间隔开，并且其中的每一个可在第二方向Y上延伸。第一栅极结构G1、第二栅极结构G2、第三栅极结构G3和第四栅极结构G4可布置在第一鳍式图案F1、第二鳍式图案F2、第三鳍式图案F3和第四鳍式图案F4上，以与第一鳍式图案F1、第二鳍式图案F2、第三鳍式图案F3和第四鳍式图案F4中的每一个交叉。参照图5和图6，例如，第四栅极结构G4可布置于在第一方向X上延伸并且从衬底101突出的第一鳍式图案F1上，以使得第四栅极结构G4与第一鳍式图案F1交叉。
例如，衬底101可为块状硅或绝缘体上的硅(SOI)。在一些实施例中，衬底101可为硅衬底，或者可包括诸如硅锗、锑化铟、碲化铅化合物、砷化铟、磷化铟、砷化镓或锑化镓等其它材料。在一些实施例中，衬底101可为其上形成有外延层的底部衬底。
第四栅极结构G4可包括栅极绝缘膜130和栅电极120。栅极间隔件140可布置于在第二方向Y上延伸的第四栅电极G4的两个侧壁上。
栅极绝缘膜130可布置在第一鳍式图案F1与栅电极120之间。栅极绝缘膜130可布置在第一鳍式图案F1的上表面和侧表面上，如图6所示。栅极绝缘膜130可布置在栅电极120与场绝缘膜110之间。
例如，栅极绝缘膜130可包括界面膜131和高k电介质绝缘膜132，如图5和图6所示。然而，实施例不限于此。例如，在一些实施例中，可省略界面膜131。
界面膜131可布置在第一鳍式图案F1的上表面和侧表面上，如图6所示。界面膜131可不沿着栅极间隔件140的侧壁布置。例如，界面膜131可包括氧化硅膜。然而，实施例不限于此。
高k电介质绝缘膜132可布置在栅电极120与界面膜131之间。高k电介质绝缘膜132可布置在栅极间隔件140与栅电极120之间。高k电介质绝缘膜132可沿着栅极间隔件140的侧壁布置。
高k电介质绝缘膜132可包括比氧化硅膜具有更高介电常数的高k电介质材料。例如，高k电介质材料可包括氧化铪、铪硅氧化物、氧化镧、镧铝氧化物、氧化锆、锆硅氧化物、氧化钽、氧化钛、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、氧化钇、氧化铝、铅钪钽氧化物和铅锌铌酸盐中的一个或多个。然而，实施例不限于此。当如上所述省略界面膜131时，高k电介质绝缘膜132可不仅包括上述高k电介质材料，其还包括氧化硅膜、氧氮化硅膜或氮化硅膜等。
栅电极120可布置在高k电介质绝缘膜132上。栅电极120可包括金属，例如W、Al和TiN中的至少一种。然而，实施例不限于此。在一些实施例中，栅电极120可不包括金属，而是替代地包括诸如Si、SiGe等半导体。
源极/漏极区SDR可布置在第四栅极结构G4的两侧上。源极/漏极区SDR可布置在第一鳍式图案F1中。第一鳍式图案F1可被部分地蚀刻，然后，可在其中蚀刻了第一鳍式图案F1的部分中形成源极/漏极区SDR。源极/漏极区SDR可为提升的源极/漏极区。因此，源极/漏极区SDR的上表面可高于第一鳍式图案F1的上表面。
当半导体装置是PMOS晶体管时，源极/漏极区SDR可包括压应力材料。例如，压应力材料可为比Si具有更大晶格常数的材料，诸如SiGe。压应力材料可对第四栅极结构G4下方的第一鳍式图案F1(即，对沟道区)施加压应力，并因此提高所述沟道区中的载流子的迁移率。
当半导体装置是NMOS晶体管时，源极/漏极区SDR可与衬底101包括相同材料或者包括拉应力材料。例如，当衬底101是Si时，源极/漏极区SDR可为Si。然而，在一些实施例中，源极/漏极区SDR可为比Si具有更小的晶格常数的材料，诸如SiC或SiP。源极/漏极区SDR可通过外延生长而形成。
虽然图5和图6中未示出，但可在源极/漏极区SDR上布置硅化物膜。硅化物膜可沿着源极/漏极区SDR的上表面形成。当源极/漏极区SDR接触源极/漏极接触件时，硅化物膜可用于降低表面电阻、接触电阻等，并且可包括诸如Pt、Ni、Co等的导电材料。在一些实施例中，半导体装置可不包括硅化物膜。
层间绝缘膜150可覆盖栅极间隔件140的侧表面和源极/漏极区SDR的上表面。下文中描述的源极/漏极接触件可布置为穿过层间绝缘膜150，并因此与源极/漏极SDR电连接。
虽然上面的描述是关于第四栅极结构G4的，但是第一栅极结构G1、第二栅极结构G2和第三栅极结构G3也具有与第四栅极结构G4相同的结构。
参照图1和图4，在单元区CR上，半导体装置可包括在第一方向X上延伸并且在第二方向Y上彼此间隔开的第一金属线M11、第二金属线M12、第三金属线M13、第四金属线M14、第五金属线M5和第六金属线M6。第一金属线M11、第二金属线M12、第三金属线M13、第四金属线M14、第五金属线M5和第六金属线M6中的每个可包括金属，所述金属例如铜(Cu)、铝(Al)、金(Au)、银(Ag)、钨(W)、钛(Ti)、氮化钛(TiN)和氮化钨(WN)中的至少一种。然而，实施例不限于此。
第五金属线M5可在第一方向X上延伸，在第二方向Y上与第一有源区AR1间隔开，并且布置在第一电源导轨区上的单元区CR的一侧上。
第五金属线M5可仅部分地覆盖单元区CR，如可从图1和图4中看出的。第五金属线M5的不覆盖单元区CR的其它部分可覆盖邻近于单元区CR的另一单元区。因此，第五金属线M5可将单元区CR与邻近的单元区电连接。
第六金属线M6可在第一方向X上延伸，在第二方向Y上与第二有源区AR2间隔开，并且布置在第二电源导轨区上的单元区CR的另一侧上。第六金属线M6可仅部分地覆盖单元区CR，如可从图1和图4中看出的。第六金属线M6的不覆盖单元区CR的其它部分可覆盖邻近于单元区CR的另一单元区。因此，第六金属线M6可将单元区CR与邻近的单元区电连接。
第一金属线M11可在第一有源区AR1上在第一方向X上延伸，并在第二方向Y上与第五金属线M5间隔开。第一金属线M11在第二方向Y上可具有第二宽度W1。
第二金属线M12可在分离区STI上在第一方向X上延伸。第二金属线M12的一部分可部分地覆盖第一有源区AR1，如图1和图4所示。然而，实施例不限于此。在一些实施例中，第二金属线M12可仅布置在分离区STI上。
第二金属线M12可在第二方向Y上与第一金属线M11间隔开第一间距P1。第二金属线M12可在第二方向Y上具有第三宽度W2。
第三金属线M13可在分离区STI上在第一方向X上延伸。第三金属线M13的一部分可部分地覆盖第二有源区AR2，如图1和图4所示。然而，实施例不限于此。在一些实施例中，第三金属线M13可仅布置在分离区STI上。
第三金属线M13可在第二方向Y上与第二金属线M12间隔开第二间距P2。第三金属线M13可在第二方向Y上具有第四宽度W3。
第四金属线M14可在第二有源区AR2上在第一方向X上延伸。第四金属线M14可在第二方向Y上与第三金属线M13间隔开第三间距P3，并且在第二方向Y上与第六金属线M6间隔开。第四金属线M14可在第二方向Y上具有第五宽度W4。
第一金属线M11的第二宽度W1、第二金属线M12的第三宽度W2、第三金属线M13的第四宽度W3和第四金属线M14的第五宽度W4可相同。然而，实施例不限于此。在一些实施例中，第一金属线M11的第二宽度W1、第二金属线M12的第三宽度W2、第三金属线M13的第四宽度W3和第四金属线M14的第五宽度W4中的至少一个可与其它的宽度不同。
第一金属线M11与第二金属线M12之间的第一间距P1、第二金属线M12与第三金属线M13之间的第二间距P2、以及第三金属线M13与第四金属线M14之间的第三间距P3可相同。然而，实施例不限于此。在一些实施例中，第一金属线M11与第二金属线M12之间的第一间距P1、第二金属线M12与第三金属线M13之间的第二间距P2、以及第三金属线M13与第四金属线M14之间的第三间距P3中的至少一个可与其它的间距不同。
根据本公开的一些实施例的半导体装置可包括单元区CR，所述单元区CR由以下各项限定：单元区CR在第二方向Y上的第一宽度Hc、第一金属线M11、第二金属线M12、第三金属线M13和第四金属线M14中的每一个在第二方向Y上的宽度W1、W2、W3、W4以及第一金属线M11、第二金属线M12、第三金属线M13和第四金属线M14之间在第二方向Y上的间距P1、P2、P3的关系。
例如，可将根据本公开的一些实施例的半导体装置的单元区CR限定为以下情况：其中，第一宽度Hc除以第一宽度W1与第一间距P1之和的结果为六或更小。在这种情况下，布置在单元区CR上的金属线的数量可三个或四个。然而，实施例不限于此。在一些实施例中，布置在单元区CR上的金属线的数量可变化，只要其满足上述关系即可。
参照图1和图3，第一源极/漏极接触件CA1、第二源极/漏极接触件CA2和第三源极/漏极接触件CA3可在第一方向上彼此间隔开，并且布置在第一有源区AR1上。第四源极/漏极接触件CA4、第五源极/漏极接触件CA5和第六源极/漏极接触件CA6可在第一方向上彼此间隔开，并且布置在第二有源区AR2上。虽然图1和图3中示出了第一源极/漏极接触件CA1、第二源极/漏极接触件CA2和第三源极/漏极接触件CA3仅布置在第一有源区AR1上，并且第四源极/漏极接触件CA4、第五源极/漏极接触件CA5和第六源极/漏极接触件CA6仅布置在第二有源区AR2上，但这仅是为了解释方便，并且实施例不限于此。第一源极/漏极接触件CA1、第二源极/漏极接触件CA2、第三源极/漏极接触件CA3、第四源极/漏极接触件CA4、第五源极/漏极接触件CA5和第六源极/漏极接触件CA6中的至少一个也可布置在分离区STI上，并且与第二金属线M12或第三金属线M13电连接。第一源极/漏极接触件CA1、第二源极/漏极接触件CA2、第三源极/漏极接触件CA3、第四源极/漏极接触件CA4、第五源极/漏极接触件CA5和第六源极/漏极接触件CA6中的至少一个也可布置在第一电源导轨区或第二电源导轨区上，并且可与第五金属线M5或第六金属线M6电连接。
参照图1和图3，第一源极/漏极接触件CA1、第二源极/漏极接触件CA2和第三源极/漏极接触件CA3可将第一有源区AR1与第一金属线M11电连接。第四源极/漏极接触件CA4、第五源极/漏极接触件CA5和第六源极/漏极接触件CA6可将第二有源区AR2与第四金属线M14电连接。
第一栅极接触件CB11的至少一部分可覆盖分离区STI。在一些实施例中，第一栅极接触件CB11可仅覆盖分离区STI。第一栅极接触件CB11的邻近于第一有源区AR1的边缘可布置在第一有源区AR1与分离区STI之间的边界B1上。然而，实施例不限于此。在一些实施例中，第一栅极接触件CB11的一部分可覆盖第一有源区AR1。第一栅极接触件CB11可将第三栅极结构G3与第二金属线M12电连接。
第二栅极接触件CB12的至少一部分可覆盖分离区STI。在一些实施例中，第二栅极接触件CB12可仅覆盖分离区STI。也就是说，第二栅极接触件CB12的邻近于第二有源区AR2的边缘可布置在第二有源区AR2与分离区STI之间的边界B2上。然而，实施例不限于此。在一些实施例中，第二栅极接触件CB12的一部分可覆盖第二有源区AR2。第二栅极接触件CB12可将第二栅极结构G2与第三金属线M13电连接。
第一源极/漏极接触件CA1、第二源极/漏极接触件CA2、第三源极/漏极接触件CA3、第四源极/漏极接触件CA4、第五源极/漏极接触件CA5和第六源极/漏极接触件CA6以及第一栅极接触件CB11和第二栅极接触件CB12可包括例如W、Al、Cu等的导电材料，但是实施例不限于此。
在根据本公开的一些实施例的半导体装置中，将第一栅极接触件CB11的至少一部分和第二栅极接触件CB12的至少一部分中的每一个布置在分离区STI上是可能的，从而在第一栅极接触件CB11和第二栅极接触件CB12与第一源极/漏极接触件CA1、第二源极/漏极接触件CA2、第三源极/漏极接触件CA3、第四源极/漏极接触件CA4、第五源极/漏极接触件CA5和第六源极/漏极接触件CA6之间有效地彼此分离。通过避免将第一栅极接触件CB11和第二栅极接触件CB12邻近于第一源极/漏极接触件CA1、第二源极/漏极接触件CA2、第三源极/漏极接触件CA3、第四源极/漏极接触件CA4、第五源极/漏极接触件CA5和第六源极/漏极接触件CA6放置，降低用于将源极/漏极接触件与栅极接触件彼此分离的工艺的难度水平是可能的。
下文中，将参照图7来描述根据本公开的其它实施例的半导体装置。所述描述将着重于与图1所示的半导体装置的不同。
图7是根据本公开的其它实施例的半导体装置的布局图。参照图7，第一栅极接触件CB21的一部分覆盖第一有源区AR1，并且第二栅极接触件CB12仅覆盖分离区STI。在这种情况下，有效地将第一栅极接触件CB21、第二源极/漏极接触件CA2和第三源极/漏极CA3彼此分离是可能的，从而降低制造工艺的难度水平。与图7所示的实施例不同，在一些实施例中，第二栅极接触件CB12的一部分可覆盖第二有源区AR2，并且第一栅极接触件CB21可仅覆盖分离区STI。
下文中，将参照图8来描述根据本公开的另一些实施例的半导体装置。所述描述将着重于与图1所示的半导体装置的不同。
图8是根据本公开的另一些实施例的半导体装置的布局图。参照图8，第一栅极接触件CB21的一部分覆盖第一有源区AR1，并且第二栅极接触件CB22的一部分覆盖第二有源区AR2。在这种情况下，有效地将第一栅极接触件CB21、第二源极/漏极接触件CA2和第三源极/漏极CA3彼此分离，并且将第二栅极接触件CB22、第四源极/漏极接触件CA4和第五源极/漏极接触件CA5彼此分离是可能的，从而降低所述工艺的难度水平。
下文中，将参照图9来描述根据本公开的另一些实施例的半导体装置。所述描述将着重于与图1所示的半导体装置的不同。
图9是根据本公开的另一些实施例的半导体装置的布局图。参照图9，第一金属线、第二金属线、第三金属线和第四金属线中的至少一个在第二方向Y上的宽度与其余金属线在第二方向Y上的宽度不同。第一金属线、第二金属线、第三金属线和第四金属线之间在第二方向Y上的间距中的至少一个与其余金属线之间在第二方向Y上的间距不同。
例如，参照图9，第三金属线M23在第二方向Y上的第六宽度W5小于第一金属线M11、第二金属线M12和第四金属线M14的宽度W1、W2、W4中的每一个。第二金属线M12与第三金属线M23之间在第二方向Y上的第四间距P4和第三金属线M23与第四金属线M14之间在第二方向Y上的第五间距P5中的每一个大于第一间距P1。然而，这仅是示例，并且在一些实施例中，与图9所示的不同，第三金属线M23在第二方向Y上的第六宽度W5可大于其它金属线M11、M12、M14的宽度W1、W2、W4中的每一个。在一些实施例中，除第三金属线M23以外的金属线在第二方向Y上的宽度可与其余金属线在第二方向Y上的宽度不同。
下文中，将参照图10来描述根据本公开的另一些实施例的半导体装置。所述描述将着重于与图1所示的半导体装置的不同。
图10是根据本公开的另一些实施例的半导体装置的布局图。参照图10，在第一有源区AR1、分离区STI和第二有源区AR2上，布置了三条金属线。第一金属线M31布置在第一有源区AR1上，第二金属线M32布置在分离区STI上，并且第三金属线M33布置在第二有源区AR2上。在这种情况下，第一金属线M31具有第七宽度W6，第二金属线M32具有第八宽度W7，第三金属线M33具有第九宽度W8。第七宽度至第九宽度(W6、W7、W8)可相同，但是实施例不限于此。在一些实施例中，第七宽度至第九宽度(W6、W7、W8)中的任一个可与其它宽度不同。第一金属线M31与第二金属线M32之间在第二方向Y上的第六间距P6可与第二金属线M32与第三金属线M33之间在第二方向Y上的第七间距P7相同。第一栅极接触件CB31将第三栅极结构G3与第二金属线M32电连接，并且第二栅极接触件CB32将第二栅极结构G2与第二金属线M32电连接。
下文中，将参照图11和图12来描述根据本公开的另一些实施例的半导体装置。所述描述将着重于与图1所示的半导体装置的不同。
参照图11和图12，半导体装置包括其中栅极结构中的每一个竖直地堆叠的多条纳米线。例如，第四栅极结构G4可包括栅极绝缘膜230、栅电极220、第一纳米线261和第二纳米线262。在第四栅极结构G4中，第一纳米线261堆叠在衬底201上，第二纳米线262堆叠在第一纳米线261上。虽然在图11和图12中示出了堆叠了两条纳米线261、262，但是实施例不限于此。在一些实施例中，在衬底201的第一鳍式图案F1上，可堆叠一条或者三条或更多条纳米线。
第一纳米线261可在衬底201上在第一方向X上延伸，并且可与衬底201间隔开。具体地说，第一纳米线261可与第一鳍式图案F1间隔开。第一纳米线261可覆盖第一鳍式图案F1。第一纳米线261可不布置在场绝缘膜210上而是布置在第一鳍式图案F1上。
第二纳米线262可在第一纳米线261上在第一方向X上延伸，并且可与第一纳米线261间隔开。第二纳米线262可覆盖第一鳍式图案F1。第二纳米线262可不布置在场绝缘膜210上而是布置在第一鳍式图案F1上。
栅电极220可布置在场绝缘膜210上和第一鳍式图案F1上。栅电极220可在第二方向Y上延伸。栅电极220可围绕与第一鳍式图案F1的上表面间隔开的第一纳米线261的外围。栅电极220还可布置于在第一纳米线261与第一鳍式图案F1之间限定的空间中。栅电极220可围绕第二纳米线262的外围。栅电极220也可形成于在第一纳米线261与第二纳米线262之间限定的空间中。
外间隔件241可布置于在第二方向Y上延伸的栅电极220的侧壁上。内间隔件242可布置在第一纳米线261的两侧上，以彼此面对。内间隔件242可布置在第二纳米线262的两侧上，以彼此面对。内间隔件242可布置在第一鳍式图案F1的上表面与第一纳米线261之间，以及第一纳米线261与第二纳米线262之间。内间隔件242可由第一纳米线261、第二纳米线262、第一鳍式图案F1和外间隔件241围绕。内间隔件242可介于第一鳍式图案F1的上表面与第一纳米线261之间以及第一纳米线261与第二纳米线262之间。
例如，外间隔件241可包括氮化硅(SiN)、氧氮化硅(SiON)、氧化硅(SiO2)和氧碳氮化硅(SiOCN)或者它们的组合。例如，内间隔件242可包括低k电介质材料，例如氮化硅(SiN)、氧氮化硅(SiON)、氧化硅(SiO2)、氧碳氮化硅(SiOCN)或者它们的组合。低k电介质材料可为具有比氧化硅更小的介电常数的材料。
栅极绝缘膜230可布置在第一纳米线261与栅电极220之间，以及第二纳米线262与栅电极220之间。栅极绝缘膜230可沿着第二纳米线262的外围布置。栅极绝缘膜230也可布置在场绝缘膜210与栅电极220之间、第一鳍式图案F1与栅电极220之间、外间隔件241与栅电极220之间、以及内间隔件242与栅电极220之间。
例如，栅极绝缘膜230可包括界面膜231和高k电介质绝缘膜232，如图11和图12所示。然而，实施例不限于此。在一些实施例中，可省略界面膜231。
由于界面膜231可沿着第一纳米线261的外围形成，因此其可布置在第一纳米线261与栅电极220之间以及第一鳍式图案F1与栅电极220之间。高k电介质绝缘膜232可布置在第一纳米线261与栅电极220之间、第一鳍式图案F1与栅电极220之间、场绝缘膜210与栅电极220之间、外间隔件241与栅电极220之间、以及内间隔件242与栅电极220之间。层间绝缘膜250可覆盖外间隔件241的侧表面和源极/漏极区SDR的上表面。
虽然上面参照附图描述了本公开的示例性实施例，但是实施例不限于这些实施例，而是可按照各种形式制造，并且应该理解，本公开所属技术领域的技术人员将能够按照不同的具体形式来实施本公开，而不改变本公开的技术概念或特征。因此，应该理解，上述实施例仅是示出性的，并且不应被理解为是限制性的。

Claims (19)

1.一种半导体装置，包括：
单元区，其包括在第一方向上延伸的第一有源区和第二有源区以及所述第一有源区与所述第二有源区之间的分离区，所述单元区在垂直于所述第一方向的第二方向上具有第一宽度；
所述单元区上的第一栅极结构和第二栅极结构，所述第一栅极结构和第二栅极结构在所述第一方向上彼此间隔开，并且在所述第二方向上延伸；
所述单元区上的第一金属线和第二金属线，所述第一金属线和第二金属线在所述第一方向上延伸，并且在所述第二方向上彼此间隔开第一间距，所述第一金属线和第二金属线中的每一个在所述第二方向上具有第二宽度；
第一栅极接触件，其将所述第一栅极结构与所述第一金属线电连接，所述第一栅极接触件的至少一部分覆盖所述分离区；以及
第二栅极接触件，其将所述第二栅极结构与所述第二金属线电连接，所述第二栅极接触件的至少一部分覆盖所述分离区，其中，所述第一宽度除以所述第一间距和所述第二宽度之和的结果为六或更小，
其中，所述第二栅极接触件的边缘布置在所述第二有源区与所述分离区之间的边界上。
2.根据权利要求1所述的半导体装置，其中，所述第一栅极接触件和所述第二栅极接触件仅布置在所述分离区上。
3.根据权利要求2所述的半导体装置，其中，第一栅极接触件的边缘布置在所述第一有源区与所述分离区之间的边界上。
4.根据权利要求1所述的半导体装置，其中，所述第一栅极接触件的一部分覆盖所述第一有源区。
5.根据权利要求1所述的半导体装置，
其中，所述第一有源区包括在所述第一方向上延伸并且从衬底突出的第一鳍式图案，并且
其中，所述第二有源区包括在所述第一方向上延伸并且从所述衬底突出的第二鳍式图案。
6.根据权利要求1所述的半导体装置，其中，所述第一栅极结构包括：
在所述第一方向上延伸的第一纳米线；
在所述第一方向上延伸的第二纳米线，其布置在所述第一纳米线上，并且与所述第一纳米线间隔开；以及
栅电极，其围绕所述第一纳米线和所述第二纳米线。
7.根据权利要求1所述的半导体装置，其中，所述第一金属线的至少一部分和所述第二金属线的至少一部分覆盖所述分离区。
8.根据权利要求1所述的半导体装置，还包括：
在所述第一有源区上，在所述第一方向上延伸并且在第所述二方向上与所述第一金属线间隔开第二间距的第三金属线；以及
在所述第二有源区上，在所述第一方向上延伸并且在所述第二方向上与所述第二金属线间隔开第三间距的第四金属线，
其中，所述第一间距、第二间距和第三间距相同，并且所述第一金属线和所述第二金属线仅布置在所述分离区上。
9.一种半导体装置，包括：
单元区，其包括第一有源区、第二有源区和所述第一有源区与所述第二有源区之间的分离区；
所述单元区上的多条金属线，所述多条金属线在第一方向上延伸，并且在垂直于所述第一方向的第二方向上彼此间隔开；
栅极结构，其横向于所述多条金属线，并且在所述第二方向上延伸；以及
栅极接触件，其至少部分地覆盖所述分离区，并且将所述多条金属线中的至少一条与所述栅极结构电连接，
其中，在所述第一有源区、所述分离区和所述第二有源区上在所述第二方向上彼此间隔开的所述多条金属线的数量为三或四，
其中，所述栅极接触件的边缘布置在所述第二有源区与所述分离区之间的边界上。
10.根据权利要求9所述的半导体装置，其中，所述多条金属线在所述第二方向上彼此间隔开第一间距。
11.根据权利要求10所述的半导体装置，其中，所述单元区在所述第二方向上具有第一宽度，其中，所述多条金属线中的每一条在所述第二方向上具有第二宽度，并且其中，所述第一宽度除以所述第二宽度和所述第一间距之和的结果为六或更小。
12.根据权利要求9所述的半导体装置：
其中，所述第一有源区包括在所述第一方向上延伸并且从衬底突出的第一鳍式图案，并且
其中，所述第二有源区包括在所述第一方向上延伸并且从所述衬底突出的第二鳍式图案。
13.根据权利要求9所述的半导体装置，其中，所述栅极结构包括：
在所述第一方向上延伸的第一纳米线；
在所述第一方向上延伸的第二纳米线，其布置在所述第一纳米线上，并且与所述第一纳米线间隔开；以及
栅电极，其围绕所述第一纳米线和所述第二纳米线。
14.根据权利要求9所述的半导体装置，还包括：
第一源极/漏极接触件，其将所述第一有源区与所述多条金属线中的第一条电连接；以及
第二源极/漏极接触件，其将所述第二有源区与所述多条金属线中的第二条电连接。
15.一种半导体装置，包括：
单元区，其包括在第一方向上延伸的第一有源区和第二有源区以及形成在所述第一有源区与所述第二有源区之间的分离区，所述单元区在垂直于所述第一方向的第二方向上具有第一宽度；
所述单元区上的第一栅极结构和第二栅极结构，所述第一栅极结构和第二栅极结构在所述第一方向上彼此间隔开，并且在所述第二方向上延伸；
第一金属线，其覆盖所述第一有源区，在所述第一方向上延伸，并且在所述第二方向上具有第二宽度；
第二金属线，其至少部分地覆盖所述分离区，在所述第二方向上与所述第一金属线间隔开第一间距，并且在所述第一方向上延伸；
第三金属线，其至少部分地覆盖所述分离区，在所述第二方向上与所述第二金属线间隔开第二间距，并且在所述第一方向上延伸；
第四金属线，其覆盖所述第二有源区，在所述第二方向上与所述第三金属线间隔开第三间距，并且在所述第一方向上延伸；
第一栅极接触件，其将所述第一栅极结构与所述第二金属线电连接；以及
第二栅极接触件，其将所述第二栅极结构与所述第三金属线电连接，
其中，所述第一间距、所述第二间距和所述第三间距相同，并且其中，所述第一宽度除以所述第一间距和所述第二宽度之和的结果为六或更小，并且
其中，所述第二栅极接触件的边缘布置在所述第二有源区与所述分离区之间的边界上。
16.根据权利要求15所述的半导体装置，其中，所述第一栅极接触件的至少一部分和所述第二栅极接触件的至少一部分覆盖所述分离区。
17.根据权利要求15所述的半导体装置，还包括：
第一源极/漏极接触件，其将所述第一有源区与所述第一金属线电连接；以及
第二源极/漏极接触件，其将所述第二有源区与所述第四金属线电连接。
18.根据权利要求15所述的半导体装置，其中，所述第一金属线、第二金属线、第三金属线和第四金属线中的每一个在所述第二方向上具有第二宽度。
19.根据权利要求15所述的半导体装置，其中，所述第二金属线、第三金属线和第四金属线中的至少一个在所述第二方向上的宽度与所述第二宽度不同。
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