CN108695290A - 封装结构 - Google Patents
封装结构 Download PDFInfo
- Publication number
- CN108695290A CN108695290A CN201710366949.7A CN201710366949A CN108695290A CN 108695290 A CN108695290 A CN 108695290A CN 201710366949 A CN201710366949 A CN 201710366949A CN 108695290 A CN108695290 A CN 108695290A
- Authority
- CN
- China
- Prior art keywords
- insulating substrate
- encapsulating structure
- groove
- structure according
- line part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 228
- 229910052751 metal Inorganic materials 0.000 claims abstract description 137
- 239000002184 metal Substances 0.000 claims abstract description 137
- 239000000463 material Substances 0.000 claims abstract description 37
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 18
- 230000002093 peripheral effect Effects 0.000 claims description 17
- -1 polyethylene Polymers 0.000 claims description 15
- 229910052737 gold Inorganic materials 0.000 claims description 14
- 239000010931 gold Substances 0.000 claims description 14
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 13
- 229910044991 metal oxide Inorganic materials 0.000 claims description 13
- 150000004706 metal oxides Chemical class 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 11
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 10
- 229920000728 polyester Polymers 0.000 claims description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 238000001465 metallisation Methods 0.000 claims description 9
- 229910052763 palladium Inorganic materials 0.000 claims description 9
- 229910052709 silver Inorganic materials 0.000 claims description 9
- 239000004332 silver Substances 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 239000010937 tungsten Substances 0.000 claims description 9
- 229910052720 vanadium Inorganic materials 0.000 claims description 9
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 claims description 9
- XLJMAIOERFSOGZ-UHFFFAOYSA-N cyanic acid Chemical compound OC#N XLJMAIOERFSOGZ-UHFFFAOYSA-N 0.000 claims description 8
- 229920000642 polymer Polymers 0.000 claims description 8
- 230000004913 activation Effects 0.000 claims description 7
- 239000000206 moulding compound Substances 0.000 claims description 7
- 239000004417 polycarbonate Substances 0.000 claims description 7
- 229920000089 Cyclic olefin copolymer Polymers 0.000 claims description 6
- 239000004713 Cyclic olefin copolymer Substances 0.000 claims description 6
- 229920000106 Liquid crystal polymer Polymers 0.000 claims description 6
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 claims description 6
- 239000004734 Polyphenylene sulfide Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229920000122 acrylonitrile butadiene styrene Polymers 0.000 claims description 6
- 229920001707 polybutylene terephthalate Polymers 0.000 claims description 6
- 229920000069 polyphenylene sulfide Polymers 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 5
- 239000004952 Polyamide Substances 0.000 claims description 5
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- 239000011651 chromium Substances 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 229910052741 iridium Inorganic materials 0.000 claims description 5
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052742 iron Inorganic materials 0.000 claims description 5
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 229920002647 polyamide Polymers 0.000 claims description 5
- 229920000139 polyethylene terephthalate Polymers 0.000 claims description 5
- 239000005020 polyethylene terephthalate Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 229910052703 rhodium Inorganic materials 0.000 claims description 5
- 239000010948 rhodium Substances 0.000 claims description 5
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- 229910052725 zinc Inorganic materials 0.000 claims description 5
- 239000011701 zinc Substances 0.000 claims description 5
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 claims description 4
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 claims description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 4
- 229920002292 Nylon 6 Polymers 0.000 claims description 4
- 239000004698 Polyethylene Substances 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 4
- 238000004891 communication Methods 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 229920001568 phenolic resin Polymers 0.000 claims description 4
- 239000005011 phenolic resin Substances 0.000 claims description 4
- 229920002492 poly(sulfone) Polymers 0.000 claims description 4
- 229920000515 polycarbonate Polymers 0.000 claims description 4
- 239000004431 polycarbonate resin Substances 0.000 claims description 4
- 229920005668 polycarbonate resin Polymers 0.000 claims description 4
- 229920000573 polyethylene Polymers 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 239000011135 tin Substances 0.000 claims description 4
- 239000004593 Epoxy Substances 0.000 claims description 3
- 239000004721 Polyphenylene oxide Substances 0.000 claims description 3
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 3
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 3
- 229920006380 polyphenylene oxide Polymers 0.000 claims description 3
- 239000004641 Diallyl-phthalate Substances 0.000 claims 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 claims 2
- QUDWYFHPNIMBFC-UHFFFAOYSA-N bis(prop-2-enyl) benzene-1,2-dicarboxylate Chemical compound C=CCOC(=O)C1=CC=CC=C1C(=O)OCC=C QUDWYFHPNIMBFC-UHFFFAOYSA-N 0.000 claims 2
- 150000001875 compounds Chemical class 0.000 claims 2
- 229920001577 copolymer Polymers 0.000 claims 2
- 150000002466 imines Chemical class 0.000 claims 2
- 239000011521 glass Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 15
- 238000000034 method Methods 0.000 description 15
- 230000036961 partial effect Effects 0.000 description 15
- 238000007747 plating Methods 0.000 description 10
- 238000000059 patterning Methods 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000004676 acrylonitrile butadiene styrene Substances 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- XECAHXYUAAWDEL-UHFFFAOYSA-N acrylonitrile butadiene styrene Chemical compound C=CC=C.C=CC#N.C=CC1=CC=CC=C1 XECAHXYUAAWDEL-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- KKEYFWRCBNTPAC-UHFFFAOYSA-N Terephthalic acid Chemical compound OC(=O)C1=CC=C(C(O)=O)C=C1 KKEYFWRCBNTPAC-UHFFFAOYSA-N 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 description 2
- UHOVQNZJYSORNB-UHFFFAOYSA-N monobenzene Natural products C1=CC=CC=C1 UHOVQNZJYSORNB-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- OMIHGPLIXGGMJB-UHFFFAOYSA-N 7-oxabicyclo[4.1.0]hepta-1,3,5-triene Chemical compound C1=CC=C2OC2=C1 OMIHGPLIXGGMJB-UHFFFAOYSA-N 0.000 description 1
- CERQOIWHTDAKMF-UHFFFAOYSA-M Methacrylate Chemical compound CC(=C)C([O-])=O CERQOIWHTDAKMF-UHFFFAOYSA-M 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 150000001408 amides Chemical class 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 238000007334 copolymerization reaction Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 150000005690 diesters Chemical class 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 150000002118 epoxides Chemical class 0.000 description 1
- 235000019253 formic acid Nutrition 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000002905 metal composite material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 125000001997 phenyl group Chemical group [H]C1=C([H])C([H])=C(*)C([H])=C1[H] 0.000 description 1
- 239000012994 photoredox catalyst Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000193 polymethacrylate Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
- H01L2224/49173—Radial fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/85411—Tin (Sn) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85439—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85444—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85447—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/85464—Palladium (Pd) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/85466—Titanium (Ti) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/85472—Vanadium (V) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/85484—Tungsten (W) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
本发明提供一种封装结构包括导线架、绝缘基材、多个导通孔、图案化金属层以及芯片。导线架包括多个接点。绝缘基材包覆导线架。导通孔设置于绝缘基材上并连通接点。图案化金属层覆盖绝缘基材的外表面并包括沟槽以及线路部。线路部连接并覆盖导通孔及接点。沟槽环绕线路部,以使线路部与其余的图案化金属层电性绝缘,其中沟槽所暴露的绝缘基材的表面低于外表面。芯片设置于绝缘基材上并与线路部电性连接。
Description
技术领域
本发明实施例涉及一种封装结构,尤其涉及一种芯片的封装结构。
背景技术
现今的信息社会下,人类对电子产品的依赖性与日俱增。为因应现今电子产品高速度、高效能、且轻薄短小的要求,具有可挠曲特性的软性电路板已逐渐应用于各种电子装置中,例如:移动电话(Mobile Phone)、笔记型电脑(Notebook PC)、数码相机(digitalcamera)、平板电脑(tablet PC)、打印机(printer)与影碟机(disk player)等。
一般而言,线路板的制作主要是将绝缘基板的单面或相对两表面上进行前处理、溅镀(sputter)、压合铜或电镀铜,再进行黄光处理,以于此绝缘基板的单面或相对两表面上形成线路层。然而,此处理的步骤繁复,且溅镀的处理的成本较高。此外,利用图案化干膜层作电镀屏障所形成的图案化线路层较难以达到现今对细线路(fine pitch)的需求。再者,绝缘基板的材料多半采用聚酰亚胺或是ABF(Ajinomoto build-up film)树脂,其价格较昂贵。因此,目前封装基板的制作不仅步骤繁复,且成本亦偏高。
发明内容
本发明实施例提供一种封装结构,其可直接于绝缘基材上形成线路,因而可简化处理及降低生产成本,更可符合细线路的需求。
本发明实施例的封装结构包括导线架、绝缘基材、多个第一导通孔、图案化金属层以及芯片。导线架包括多个第一接点。绝缘基材包覆导线架。第一导通孔设置于绝缘基材上并连通第一接点。图案化金属层覆盖绝缘基材的外表面并包括第一沟槽以及线路部。线路部连接并覆盖第一导通孔及第一接点,第一沟槽环绕线路部,以使线路部与其余的图案化金属层电性绝缘,其中第一沟槽所暴露的绝缘基材的表面低于外表面。芯片设置于绝缘基材上并与线路部电性连接。
在本发明的一实施例中,上述的绝缘基材的材料包括环氧化合物(epoxy)、邻苯二甲酸二烯丙酯(DAP)、苯并环丁烯(BCB)、聚脂、丙烯酸酯、氟素聚合物、聚亚苯基氧化物、聚酰亚胺、酚醛树脂、聚砜、硅素聚合物、BT树脂(Bismaleimide-Triazine modified epoxyresin)、氰酸聚酯、聚乙烯、聚碳酸酯树脂、丙烯腈-丁二烯-苯乙烯共聚物、聚对苯二甲酸乙二酯(PET)、聚对苯二甲酸丁二酯(PBT)、液晶高分子(liquid crystal polyester,LCP)、聚酰胺(PA)、尼龙6、共聚聚甲醛(POM)、聚苯硫醚(PPS)、聚碳酸脂(polycarbonate,PC)、聚甲基丙烯酸甲脂(polymethacrylate,PMMA)、ABS树脂(Acrylonitrile Butadiene Styrene,ABS)或环状烯烃共聚物(COC)。
在本发明的一实施例中,上述的绝缘基材的材料不包括适于被激光、等离子体或机械刀具激活为可进行金属化镀膜的金属氧化复合物。
在本发明的一实施例中,上述的绝缘基材的材料包括适于被激光、等离子体或机械刀具激活为可进行金属化镀膜的金属氧化复合物。
在本发明的一实施例中,上述的金属氧化复合物包括锌、铜、银、金、镍、钯、铂、钴、铑、铱、铟、铁、锰、铝、铬、钨、钒、钽、钛或其任意组合。
在本发明的一实施例中,上述的图案化金属层还包括多个外部接垫,设置于绝缘基材相对于芯片的下表面并电性连接第一接点。
在本发明的一实施例中,上述的导线架包括多个外部接垫,暴露于绝缘基材之外并电性连接第一接点。
在本发明的一实施例中,上述的绝缘基材还包括第二导通孔,设置于绝缘基材上并电性连接导线架的接地电极,且其余的图案化金属层覆盖并电性连接第二导通孔。
在本发明的一实施例中,上述的绝缘基材还包括元件设置槽,芯片及第一导通孔设置于元件设置槽内。
在本发明的一实施例中,上述的芯片通过打线接合技术或覆晶封装技术而电性连接至线路部。
在本发明的一实施例中,上述的导线架还包括至少一第二接点,绝缘基材还包括至少一开口,以暴露第二接点,线路部连接并覆盖开口及第二接点。
在本发明的一实施例中,上述的绝缘基材还包括第二沟槽,其位于第一沟槽所框围的范围内并与第一沟槽之间维持间隙,线路部覆盖第二沟槽以及间隙,第二沟槽的底面低于外表面。
在本发明的一实施例中,上述的图案化金属层的材料包括金、钯、银、锡、钨、钛、钒或铜。
在本发明的一实施例中,上述的导线架包括金属柱阵列,且第一接点包括多个金属柱。
在本发明的一实施例中,上述的导线架还包括芯片座,金属柱围绕芯片座设置。
在本发明的一实施例中,上述的绝缘基材还包括开口,以暴露芯片座的顶面。
在本发明的一实施例中,上述的芯片座的底面与各金属柱的下表面共平面。
在本发明的一实施例中,上述的封装结构还包括多个第三导通孔,设置于绝缘基材上,绝缘基材覆盖芯片座的周缘区域,第三导通孔连接周缘区域,且线路部连接第三导通孔。
在本发明的一实施例中,上述的导线架还包括芯片座,芯片座包括凹口,凹口的底面与金属柱阵列的下表面共平面。
在本发明的一实施例中,上述的绝缘基材还包括开口,以暴露底面,且金属柱围绕芯片座。
在本发明的一实施例中,上述的绝缘基材覆盖芯片座的周缘区域,且芯片座的下表面突出于绝缘基材的下表面。
在本发明的一实施例中,上述的封装结构还包括多个第三导通孔,设置于绝缘基材上,绝缘基材覆盖芯片座的周缘区域,周缘区域围绕凹口,第三导通孔连接周缘区域,且线路部连接第三导通孔。
在本发明的一实施例中,上述的封装结构还包括模塑料,覆盖芯片以及绝缘基材的上表面。
本发明实施例的一种封装结构包括导线架、绝缘基材、多个第一导通孔、图案化金属层以及芯片。导线架包括多个第一接点以及至少一第二接点。绝缘基材包覆导线架并包括至少一开口,开口暴露第二接点。第一导通孔设置于绝缘基材上并连通第一接点。图案化金属层覆盖绝缘基材的外表面并包括第一沟槽以及线路部,线路部连接并覆盖第一导通孔、第一接点、开口及第二接点,第一沟槽环绕线路部,以使线路部与其余的图案化金属层电性绝缘,其中第一沟槽所暴露的绝缘基材的表面低于外表面。芯片设置于绝缘基材上并与线路部电性连接。
本发明实施例的一种封装结构包括基板、绝缘基材以及图案化金属层。基板包括多个电性接点、有源表面以及相对有源表面的背面,电性接点设置于有源表面。绝缘基材设置于基板上并至少覆盖有源表面。第一导通孔设置于绝缘基材上并连通电性接点。图案化金属层覆盖绝缘基材的外表面并包括第一沟槽以及第一线路部,第一线路部连接并覆盖第一导通孔及电性接点,第一沟槽环绕线路部,以使第一线路部与其余的图案化金属层电性绝缘,其中第一沟槽所暴露的绝缘基材的表面低于外表面。
在本发明的一实施例中,上述的绝缘基材还包括第二沟槽,其位于第一沟槽所框围的范围内并与第一沟槽之间维持间隙,线路部覆盖第二沟槽以及间隙,第二沟槽的底面低于外表面。
在本发明的一实施例中,上述的基板还包括多个基板贯孔,贯穿基板并电性连通基板的有源表面以及背面。
在本发明的一实施例中,上述的绝缘基材覆盖背面。
在本发明的一实施例中,上述的封装结构还包括多个第二导通孔,贯穿覆盖背面的绝缘基材并电性连接基板贯孔,其中图案化金属层更包括第三沟槽以及第二线路部,第二线路部连接并覆盖第二导通孔,第二沟槽环绕第二线路部,以使第二线路部与其余的图案化金属层电性绝缘,其中第二沟槽所暴露的绝缘基材的表面低于外表面。
在本发明的一实施例中,上述的封装结构还包括至少一芯片,设置于绝缘基材上并电性连接第二线路部。
基于上述,本发明实施例的封装结构可先对绝缘基材进行全面化镀而形成覆盖绝缘基材的外表面的金属层,再以激光、等离子体或机械刀具等手段于金属层上形成第一沟槽,以将欲形成线路部的部分与其余的金属层电性绝缘而形成图案化金属层。因此,被刻划后所暴露出的绝缘基材的表面会低于被图案化金属层所覆盖的绝缘基材的外表面。并且,依此处理所形成的封装结构可有效简化处理步骤,更可避免在激光烧熔以形成线路的过程中在线路边缘形成溢镀铜而导致线路间距无法有效缩小的问题。
再者,线路部以外的其余的图案化金属层会大面积地覆盖绝缘基材的表面,因而可作为接地/屏蔽之用,降低静电放电及电磁干扰的影响。并且,本发明实施例的绝缘基材可通过模塑(molding)的方式定型,故对其厚度及外型上具有较大的设计弹性。因此,本发明的封装结构不仅可提升其设计弹性,更可轻易符合细线路的标准,且可有效简化处理步骤及降低生产成本及封装结构的整体厚度。
为让本发明实施例的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
图1是依照本发明的一实施例的一种封装结构的俯视示意图;
图2是依照本发明的一实施例的一种封装结构的局部剖面示意图;
图2A是依照本发明的一实施例的一种封装结构的局部剖面示意图;
图3是依照本发明的一实施例的一种封装结构的俯视示意图;
图4是依照本发明的一实施例的一种封装结构的局部剖面示意图;
图5是依照本发明的一实施例的一种封装结构的制作流程俯视示意图;
图6是依照本发明的一实施例的一种封装结构的局部剖面示意图;
图7是依照本发明的一实施例的一种封装结构的仰视示意图;
图8是依照本发明的一实施例的一种封装结构的俯视示意图;
图9是依照本发明的一实施例的一种封装结构的导线架的示意图;
图10是依照本发明的一实施例的一种封装结构的剖面示意图;
图11是依照本发明的一实施例的一种封装结构的剖面示意图;
图12是依照本发明的一实施例的一种封装结构的剖面示意图;
图13是依照本发明的一实施例的一种封装结构的剖面示意图;
图14及图15是依照本发明的一实施例的一种封装结构的制作流程剖面示意图;
图16是依照本发明的一实施例的一种封装结构的剖面示意图。
附图标记说明:
100、100a:封装结构
110、110a、110b:导线架
112:第一接点、电性接点、金属柱
112a:接地电极
114:第二接点
116:芯片座
116a:蚀刻阻障层
116b:凹口
120:绝缘基材
122:元件设置槽
124:开口
126:第二沟槽
128:凹槽
130:第一导通孔
140:图案化金属层
142:第一沟槽
144:线路部、第一线路部
146:外部接垫
148:第二线路部
150:芯片
152:导线
153:导电凸块
160:第二导通孔
170:第三导通孔
180:模塑料
190:基板
192:电性接点
194:基板贯孔
S1:有源表面
S2:背面
具体实施方式
有关本发明实施例的前述及其他技术内容、特点与功效,在以下配合参考附图的各实施例的详细说明中,将可清楚的呈现。以下实施例中所提到的方向用语,例如:“上”、“下”、“前”、“后”、“左”、“右”等,仅是参考附图的方向。因此,使用的方向用语是用来说明,而并非用来限制本发明实施例。并且,在下列各实施例中,相同或相似的元件将采用相同或相似的标号。
图1是依照本发明的一实施例的一种封装结构的俯视示意图。图2是依照本发明的一实施例的一种封装结构的局部剖面示意图。请同时参照图1及图2,在本实施例中,封装结构100包括导线架110、绝缘基材120、多个第一导通孔130、图案化金属层140以及芯片150。导线架110包括多个第一接点112。绝缘基材120包覆导线架110。在本实施例中,绝缘基材120可利用模塑成形的方式而将绝缘材料模塑成包覆导线架110的绝缘基材120,其可例如作为封装结构100的基板之用。如此,绝缘基材120的厚度及形状可依产品需求而自由调整。因此,本实施例的封装结构100不仅可简化处理,提升设计的弹性,并且,封装结构100的最大厚度更可有效降低。
举例来说,绝缘基材120的材料可包括环氧树脂、聚脂、丙烯酸酯、氟素聚合物、聚亚苯基氧化物、聚酰亚胺、酚醛树脂、聚砜、硅素聚合物、BT树脂(Bismaleimide-Triazinemodified epoxy resin)、氰酸聚酯、聚乙烯、聚碳酸酯树脂、丙烯腈-丁二烯-苯乙烯共聚物、聚对苯二甲酸乙二酯(PET)、聚对苯二甲酸丁二酯(PBT)、液晶高分子(liquid crystalpolyester,LCP)、聚酰胺(PA)、尼龙6、共聚聚甲醛(POM)、聚苯硫醚(PPS)或环状烯烃共聚物(COC)等介电材料。并且,在本实施例中,绝缘基材120的材料可不包括适于被激光、等离子体或机械刀具激活为可进行金属化镀膜的金属氧化复合物,例如:锌、铜、银、金、镍、钯、铂、钴、铑、铱、铟、铁、锰、铝、铬、钨、钒、钽、钛或其任意组合。
在本实施例中,第一导通孔130设置于绝缘基材120上并连通导线架110的第一接点112。图案化金属层140覆盖绝缘基材120的外表面并包括第一沟槽142以及线路部144。线路部144连接并覆盖第一导通孔130及第一接点112,第一沟槽142则环绕线路部144,以使线路部144与其余的图案化金属层140电性绝缘。在此须说明的是,所谓的「其余的图案化金属层140」是指除了被第一沟槽142所环绕的部分(例如线路部144)以外的图案化金属层140。并且,请参照图2,第一沟槽142所暴露的绝缘基材120的表面低于图案化金属层140所覆盖的绝缘基材120的外表面。如此,芯片150可设置于绝缘基材120上,并例如通过打线接合的方式与图案化金属层140的线路部144电性连接。当然,在其他实施例中,芯片150也可利用覆晶接合的方式与图案化金属层140的线路部144电性连接。
在本实施例中,图案化金属层140的制作方法可包括下列步骤。首先,可对绝缘基材120的表面进行全面化镀,以形成全面包覆绝缘基材120的外表面的金属层,接着,再以激光、等离子体或机械刀具等手段于此金属层上刻划出第一沟槽142,以形成如图1所示的图案化金属层140,其中,第一沟槽142会绕过第一导通孔130以及欲形成线路的区域,以定义出如图1所示的线路部144,并使第一导通孔130、第一接点112及线路部144与其余的图案化金属层140电性绝缘。在本实施例中,图案化金属层140的材料可与预电镀导线架(Pre-Plated Frame)的材料相同,其例如包括金、钯、银、锡、钨、钛、钒或铜。
如此,由于本实施例是以激光、等离子体或机械刀具等手段来刻划出第一沟槽142,因此,被第一沟槽142所暴露的部分绝缘基材120的表面会因受到激光、等离子体或机械刀具的刻划而低于被图案化金属层140所覆盖绝缘基材120的外表面。也就是说,被第一沟槽142所暴露的绝缘基材120的表面与被图案化金属层140所覆盖的绝缘基材120的外表面之间会存在高度段差。
在本实施例中,封装结构100还可包括第二导通孔160,其设置于绝缘基材120上并电性连接至导线架110的接地电极(如图5及图8所示的接地电极112a),并且,其余的图案化金属层140覆盖并电性连接此第二导通孔160。由于在芯片150的封装与使用过程中,当静电累积至一定程度而产生放电现象时,芯片150很容易受到静电放电的影响而被损害,因此,其余的图案化金属层140覆盖绝缘基材120的外表面并电性连接至接地电极112a,因而可作为接地/屏蔽之用,降低静电放电及电磁干扰的影响。
图2A是依照本发明的一实施例的一种封装结构的局部剖面示意图。在此必须说明的是,本实施例的封装结构100与图1及图2的封装结构100相似,因此,本实施例沿用前述实施例的元件标号与部分内容,其中采用相同的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,本实施例不再重复赘述。以下将针对本实施例的封装结构100与图1及图2的封装结构100的差异做说明。
请参照图2A,在本实施例中,封装结构100可不包括如图2所示的导线架110,如此,第一导通孔130则可贯穿绝缘基材120。图案化金属层140则同样地覆盖绝缘基材120的外表面并可包括第一沟槽142、线路部144以及多个外部接垫146。外部接垫146设置于绝缘基材120相对于第一沟槽142所设置的表面的下表面并电性连接第一导通孔130。并且,外部接垫146与其余的图案化金属层140电性绝缘。如此,芯片150设置于绝缘基材120上并与线路部144电性连接,并可经由第一导通孔130而电性连接至外部接垫146。
图3是依照本发明的一实施例的一种封装结构的俯视示意图。图4是依照本发明的一实施例的一种封装结构的局部剖面示意图。在此必须说明的是,本实施例的封装结构100与图1及图2的封装结构100相似,因此,本实施例沿用前述实施例的元件标号与部分内容,其中采用相同的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,本实施例不再重复赘述。请参照图3以及图4,以下将针对本实施例的封装结构100与图1及图2的封装结构100的差异做说明。
在本实施例中,导线架110还可包括至少一第二接点114,而绝缘基材120还可包括至少一开口124,以暴露第二接点114,并且,图案化金属层140的第一沟槽142可如图3所示的环绕此开口124,而线路部144则连接并覆盖此开口124及此第二接点114,以使第二接点114与其余的图案化金属层140电性绝缘。如此配置,本实施例的芯片150可利用在绝缘基材120上直接开口的方式而直接电性连接至导线架110的第二接点114,并且,也可利用线路部144连接第一导通孔130的方式使芯片150电性连接至线路部144,进而可通过第一导通孔130而电性连接至导线架110的第一接点112。
图5是依照本发明的一实施例的一种封装结构的制作流程俯视示意图。图6是依照本发明的一实施例的一种封装结构的局部剖面示意图。在此必须说明的是,本实施例的封装结构100与图1及图2的封装结构100相似,因此,本实施例沿用前述实施例的元件标号与部分内容,其中采用相同的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,本实施例不再重复赘述。请参照图5以及图6,以下将针对本实施例的封装结构100与图1及图2的封装结构100的差异做说明。
本实施例的封装结构的制作方法可包括下列步骤。首先,请参照图5,在绝缘基材120上以激光、等离子体或机械刀具等手段来刻划出第二沟槽126,并可同时在欲形成第一导通孔130的位置以激光、等离子体或机械刀具等手段挖凿出暴露第一接点112。之后,再对绝缘基材120的表面进行全面化镀,以形成全面包覆绝缘基材120的外表面的金属层,此金属层会覆盖通孔而形成第一导通孔130(亦可通过相同的方法形成第二导通孔160),并且,此金属层会覆盖第二沟槽126,因而可增加金属层与绝缘基材120之间的接触面积,进而可增进两者之间的接合力。
接着,再以激光、等离子体或机械刀具等手段于此金属层上刻划出第一沟槽142,以形成如图6所示的图案化金属层140,其中,第一沟槽142会绕过第一导通孔130以及欲形成线路部144的区域,以定义出如图6所示的线路部144,并使第一导通孔130、第一接点112及线路部144与其余的图案化金属层140电性绝缘。如此,第二沟槽126会如图6所示的位于第一沟槽142所框围的范围内并与第一沟槽142之间维持间隙,线路部144则覆盖第二沟槽126以及此间隙。在本实施例中,第二沟槽126的底面会低于被其余的图案化金属层140所覆盖的绝缘基材120的外表面。
此外,本实施例亦可在形成第二沟槽126及通孔的同时,在绝缘基材120上以激光、等离子体或机械刀具等手段来挖凿出如图4所示的至少一开口124,以暴露导线架110的第二接点114,而第一沟槽142可如图3所示的环绕此开口124,且线路部144连接并覆盖此开口124及此第二接点114,以使本实施例的芯片150可利用在绝缘基材120上直接开口的方式而直接电性连接至导线架110的第二接点114,并且,也可利用线路部144连接第一导通孔130的方式使芯片150电性连接至线路部144,进而可通过第一导通孔130而电性连接至导线架110的第一接点112。
此外,本实施例的封装结构100亦可不包括导线架110,线路部144可通过贯穿绝缘基板120的第一导通孔130而电性连接至外部接垫146(相似于图2A的配置)。
图7是依照本发明的一实施例的一种封装结构的仰视示意图。请参照图7,在如图1至图6所示的封装结构100中,导线架110可包括多个外部接垫146,其暴露于绝缘基材120之外并可电性连接第一导通孔130、第一接点112及第二接点114。图案化金属层140可覆盖外部接垫146。如此,封装结构100便可通过绝缘基材120上的外部接垫146而电性连接至一外部电子元件,例如:主机板。
在本实施例中,在对绝缘基材120的表面全面进行化镀之前,可先形成防镀层,其至少环绕外部接垫146,也就是说,防镀层可例如覆盖如图7中未显示斜线的部分,之后再对绝缘基材120的表面全面进行化镀,以使图案化金属层140覆盖外部接垫146,并使外部接垫146与其余的图案化金属层140电性绝缘。
此外,在其他实施例中,绝缘基材120的材料可包括适于被激光、等离子体或机械刀具激活为可进行金属化镀膜的金属氧化复合物。此金属氧化复合物包括锌、铜、银、金、镍、钯、铂、钴、铑、铱、铟、铁、锰、铝、铬、钨、钒、钽、钛或其任意组合。如此,本实施例的覆盖外部接垫146的图案化金属层140的形成方法可包括下列步骤。首先,在绝缘基材120相对于芯片150的下表面上以激光刻划出欲形成外部接垫146的路径(例如以激光刻划图7中显示斜线的部分),以刻出对应外部接垫146的接垫沟槽,使此接垫沟槽上的非导电的金属复合物破坏而释放对还原金属化具有高活性的重金属晶核,接着,再对激光刻划后的绝缘基材120进行选择性电镀,以在接垫沟槽上直接化镀及电镀而形成如图7所示的外部接垫146。因此,依上述处理所形成的外部接垫146的底面会低于绝缘基材120的外表面。本实施例的外部接垫146的形成方法可套用至图2、图2A、图4及图6的封装结构上而于绝缘基板120的下表面上形成连通第一导通孔130的外部接垫146。并且,在此实施例中,绝缘基材120上的图案化金属层140亦可利用上述的激光刻划并激活绝缘基材120中的金属氧化复合物的方式而形成。
图8是依照本发明的一实施例的一种封装结构的俯视示意图。在本实施例中,绝缘基材120还可包括元件设置槽122,芯片150、第一导通孔130、开口124(若有)及第二导通孔160(若有)皆可设置于此元件设置槽122内。在本实施例中,芯片150可通过打线接合技术而电性连接至线路部144。当然,本实施例并不以此为限,在其他实施例中,芯片150也可通过覆晶接合技术而电性连接至线路部144。
此外,本实施例的封装结构100亦可不包括导线架110,线路部144可通过贯穿绝缘基板120的第一导通孔130而电性连接至外部接垫146(相似于图2A的配置)。
图9是依照本发明的一实施例的一种封装结构的导线架的示意图。图10是依照本发明的一实施例的一种封装结构的剖面示意图。图11是依照本发明的一实施例的一种封装结构的剖面示意图。在此必须说明的是,本实施例的封装结构100与前述实施例的封装结构100相似,因此,本实施例沿用前述实施例的元件标号与部分内容,其中采用相同的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,本实施例不再重复赘述。以下将针对本实施例的封装结构100与前述实施例的封装结构100的差异做说明。
请先参照9至图10,本实施例的导线架110可如图10所示的包括金属柱阵列,其包括多个呈阵列排列的金属柱112,此金属柱112即可为前述的第一接点112/第二接点114。本实施例的导线架110可依下列步骤形成。首先,提供金属基板。接着,形成图案化光阻层于金属基板的上表面。之后,以图案化光阻层作为蚀刻阻障而对金属基板的上表面进行半蚀刻处理,以形成如图9所示的导线架110a,其具有多个金属柱112,且金属柱112的底部彼此连接。接着,将如图10所示的绝缘基材120覆盖金属柱阵列,之后,再对如图9所示的导线架110a的底部进行另一半蚀刻处理,以移除导线架110a的底部而形成如图10所示的包括多个彼此分离且呈阵列排列的金属柱112的导线架110,并使绝缘基材120暴露金属柱阵列的下表面。
接着,再依前述实施例的制作方法依序形成第一导通孔130及图案化金属层140等结构,之后,再将芯片150设置于绝缘基材120上并使其电性连接至图案化金属层140的线路部144。举例而言,芯片150可如图10所示的通过打线接合或如图11所示的覆晶接合的方式而电性连接至图案化金属层140的线路部144。也就是说,如图10所示的多条导线152和/或如图11所示的多个导电凸块153可用以电性连接于单一芯片150或多个芯片150与线路部144之间。此外,封装结构100还可包括模塑料180,其覆盖芯片150与绝缘基材120的上表面。须说明的是,模塑料180的材料可与绝缘基材120的材料相同或可为其他的绝缘材料。
图12是依照本发明的一实施例的一种封装结构的剖面示意图。图13是依照本发明的一实施例的一种封装结构的剖面示意图。在此必须说明的是,本实施例的封装结构100与图10及图11的封装结构100相似,因此,本实施例沿用前述实施例的元件标号与部分内容,其中采用相同的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,本实施例不再重复赘述。以下将针对本实施例的封装结构100与图10及图11的封装结构100的差异做说明。
请同时参照图12及图13,在本实施例中,导线架110还可包括芯片座116,而金属柱112则可围绕芯片座116而设置。本实施例的导线架110可依下列步骤形成。首先,提供金属基板。接着,对此金属基板进行半蚀刻处理,以形成具有芯片座116及多个金属柱112的导线架,且此时的金属柱112与芯片座116的底部彼此连接。接着,将绝缘基材120覆盖金属柱112与芯片座116,之后,再对导线架的底部进行另一半蚀刻处理,以移除导线架的底部而形成如图12所示的包括多个彼此分离的金属柱112及芯片座116的导线架110,并使绝缘基材120暴露芯片座116与金属柱112的下表面。在本实施例中,芯片座116的底面与各金属柱112的下表面共平面。
之后,再于绝缘基材120上形成凹槽128,以暴露芯片座116的顶面。接着,再依前述实施例的制作方法依序形成第一导通孔130及图案化金属层140等结构,之后,再将芯片150设置于芯片座116的顶面上并使其电性连接至图案化金属层140的线路部144。举例而言,芯片150可如图12所示的通过打线接合或如图13所示的覆晶接合的方式而电性连接至图案化金属层140的线路部144。也就是说,如图12所示的多条导线152和/或如图13所示的多个导电凸块153可用以电性连接于单一芯片150或多个芯片150与线路部144之间。
此外,封装结构100还可包括多个第三导通孔170,其设置于绝缘基材120上并电性连接线路部144。绝缘基材120覆盖芯片座116的周缘区域,且第三导通孔170如图12及图13所示连接芯片座116的周缘区域,而线路部144则连接第三导通孔170。在本实施例中,第三导通孔170可围绕芯片座116的周缘区域以形成电源环(power ring)或接地环(groundring),且芯片150可通过如图12所示的打线接合或如图13所示的覆晶直接贴合而电性连接至图案化金属层140的线路部144。并且,封装结构100还可包括模塑料180,其覆盖芯片150与绝缘基材120的上表面。
图14及图15是依照本发明的一实施例的一种封装结构的制作流程剖面示意图。在此必须说明的是,本实施例的封装结构100与图12及图13的封装结构100相似,因此,本实施例沿用前述实施例的元件标号与部分内容,其中采用相同的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,本实施例不再重复赘述。以下将针对本实施例的封装结构100与图14及图15的封装结构100的差异做说明。
在本实施例中,导线架110亦可包括芯片座116。芯片座116包括凹口116b,且凹口116b的底面如图14所示的与金属柱112的下表面共平面。本实施例中导线架110的处理可包括下列步骤。先利用半蚀刻处理形成导线架110b,其包括多个金属柱112及具有凹口116b的芯片座凸块,金属柱112如图14所示的围绕芯片座凸块,且金属柱112与芯片座凸块的底部相连。接着,形成绝缘基材120以覆盖金属柱112,且绝缘基材120还包括凹槽128。凹槽128位于绝缘基材120的上表面122并暴露凹口116b的底面,且金属柱112围绕绝缘基材120的凹槽128。
接着,形成如图14所示的蚀刻阻障层116a,以覆盖导线架110的部分底面,且被蚀刻阻障层116a所覆盖的部分底面对应于如图15所示的芯片座116。接着(较佳的时间点是模塑料180形成后),对导线架110a的底面进行半蚀刻处理,以移除导线架110的底面中除了被蚀刻阻障层116a所覆盖的部分,以形成如图15所示的芯片座116。如此,金属柱112则围绕芯片座116,绝缘基材120覆盖芯片座116的周缘区域,而凹口116b的底面则不会如图15所示的与金属柱112的下表面共平面,也就是说,芯片座116的下表面会突出于绝缘基材120的下表面。
此外,封装结构100也可包括多个第三导通孔170,其设置于绝缘基材120上并电性连接线路部144。进一步而言,第三导通孔170如图15所示连接芯片座116的周缘区域,此周缘区域围绕凹口116b,也就是说,第三导通孔170会连接芯片座116中围绕凹口116b的周围区域,而线路部144则连接第三导通孔170。在本实施例中,第三导通孔170可围绕芯片座116的周缘区域以形成电源环或接地环,并且,本实施例的芯片150也可通过打线接合或覆晶贴合而电性连接至图案化金属层140的线路部144。并且,封装结构100还可包括模塑料180,其覆盖芯片150与绝缘基材120的上表面。
图16是依照本发明的一实施例的一种封装结构的剖面示意图。在此必须说明的是,本实施例的封装结构100a与前述实施例的封装结构100相似,因此,本实施例沿用前述实施例的元件标号与部分内容,其中采用相同的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,本实施例不再重复赘述。以下将针对本实施例的封装结构100a与前述实施例的封装结构100的差异做说明。
在本实施例中,封装结构100a的制作方法是先将绝缘基材120设置于基板190上,其中,基板190可例如为晶片,其包括多个电性接点192、有源表面S1以及相对有源表面S1的背面S2,电性接点192设置于有源表面S1。在一实施例中,基板190还可包括多个基板贯孔194,其贯穿基板190并电性连通基板190的有源表面S1以及背面S2,而电性接点192则依需要而可选择性电性连接基板贯孔194。在本实施例中,基板190可例如为晶片,此晶片可由呈阵列排列的多个芯片所组成,绝缘基材120包覆此晶片,而基板贯孔194则可为贯穿晶片的硅通孔。当然,本实施例仅为举例说明,本揭露并不限定基板190的种类及形式。
在本实施例中,绝缘基材120可如图16所示的至少覆盖基板190的有源表面S1,并覆盖上述的电性接点192。此外,在基板190包括多个基板贯孔194的实施例中,绝缘基材120可至少覆盖基板190的有源表面S1及背面S2。接着,可利用相似于前述导通孔的制作方法,例如先以激光、等离子体或机械刀具挖凿再全面化镀的方式形成第一导通孔130,使其如图16所示的设置于绝缘基材120上并贯穿绝缘基材120,以连通电性接点192。
接着,请参照图1及图16,再利用相似于前述图案化金属层140的制作方法形成本实施例的图案化金属层140(其俯视图可参照图1),其覆盖绝缘基材120的外表面并包括第一沟槽142以及第一线路部144,第一线路部144连接并覆盖第一导通孔130及电性接点192,第一沟槽142环绕线路部144,以使第一线路部144与其余的图案化金属层140电性绝缘,其中第一沟槽142所暴露的绝缘基材120的表面低于绝缘基材120被图案化金属层140所覆盖的外表面。
在本实施例中,封装结构100a还可包括多个第二导通孔160。第二导通孔160贯穿覆盖基板190的背面S2的绝缘基材120,并电性连接基板贯孔194。并且,请参照图1及图16,图案化金属层140还可包括第三沟槽以及第二线路部148(其俯视图相似于图1的第一沟槽142及线路部144),第二线路部148连接并覆盖第二导通孔160,第二沟槽环绕第二线路部148,以使第二线路部148与其余的图案化金属层140电性绝缘,其中第二沟槽所暴露的绝缘基材120的表面会低于外表面。
此外,请参照图6及图16,本实施例还可利用相似于前述第二沟槽126的制作方法于本实施例的绝缘基材120上先形成第二沟槽126,其位于第一沟槽142所框围的范围内并与第一沟槽142之间维持间隙,线路部144覆盖第二沟槽以及间隙,且第二沟槽的底面低于外表面,因而可增加图案化金属层140与绝缘基材120之间的接触面积,进而增进图案化金属层140与绝缘基材120之间的接合力。
并且,封装结构100a还可包括至少一芯片150,其设置于绝缘基材120上并电性连接图案化金属层140的第一线路部144和/或第二线路部148。本实施例仅显示一层绝缘基材120作为示意,但本发明并不限定绝缘基材120的层数,可视实际产品需求而于基板190上依序堆叠多层图案化金属层140及绝缘基材120。
综上所述,本发明实施例的封装结构可先对绝缘基材进行全面化镀而形成覆盖绝缘基材的外表面的金属层,再以激光、等离子体或机械刀具等手段于金属层上形成第一沟槽,以将欲形成线路部的部分与其余的金属层电性绝缘而形成图案化金属层。因此,被刻划后所暴露出的绝缘基材的表面会低于被图案化金属层所覆盖的绝缘基材的外表面。并且,依此处理所形成的封装结构可有效简化处理步骤,更可避免在激光烧熔以形成线路的过程中在线路边缘形成溢镀铜而导致线路间距无法有效缩小的问题。
除此之外,本发明实施例的封装结构更可先以激光、等离子体或机械刀具等手段于绝缘基材欲形成线路部处刻划出第二沟槽,再对绝缘基材进行全面化镀,并形成第一沟槽以使线路部与其余的金属层电性绝缘。因此,线路部会覆盖于第二沟槽上,因而可增加其与绝缘基材的接触面积,进而可增进图案化金属层的线路部与绝缘基材之间的接合力。
再者,线路部以外的其余的图案化金属层会大面积地覆盖绝缘基材的表面,因而可作为接地/屏蔽之用,降低静电放电及电磁干扰的影响。并且,本发明实施例的绝缘基材可通过模塑(molding)的方式定型,故对其厚度及外型上具有较大的设计弹性。因此,本发明的封装结构不仅可提升其设计弹性,更可轻易符合细线路的标准,且可有效简化处理步骤及降低生产成本及封装结构的整体厚度。
虽然本发明已以实施例揭示如上,然其并非用以限定本发明,任何所属技术领域中技术人员,在不脱离本发明的精神和范围内,当可作些许的更改与润饰,故本发明的保护范围当视后附的申请专利范围所界定的为准。
Claims (40)
1.一种封装结构,其特征在于,包括:
导线架,包括多个第一接点;
绝缘基材,包覆所述导线架;
多个第一导通孔,设置于所述绝缘基材上并连通所述多个第一接点;
图案化金属层,覆盖所述绝缘基材的外表面并包括第一沟槽以及线路部,所述线路部连接并覆盖所述多个第一导通孔及所述多个第一接点,所述第一沟槽环绕所述线路部,以使所述线路部与其余的所述图案化金属层电性绝缘,其中所述第一沟槽所暴露的所述绝缘基材的一表面低于所述外表面;以及
芯片,设置于所述绝缘基材上并与所述线路部电性连接。
2.根据权利要求1所述的封装结构,其特征在于,所述绝缘基材的材料包括环氧化合物、邻苯二甲酸二烯丙酯、苯并环丁烯、聚脂、丙烯酸酯、氟素聚合物、聚亚苯基氧化物、聚酰亚胺、酚醛树脂、聚砜、硅素聚合物、BT树脂、氰酸聚酯、聚乙烯、聚碳酸酯树脂、丙烯腈-丁二烯-苯乙烯共聚物、聚对苯二甲酸乙二酯、聚对苯二甲酸丁二酯、液晶高分子、聚酰胺、尼龙6、共聚聚甲醛、聚苯硫醚、聚碳酸脂、聚甲基丙烯酸甲脂、ABS树脂或环状烯烃共聚物。
3.根据权利要求1所述的封装结构,其特征在于,所述绝缘基材的材料不包括能够被激光、等离子体或机械刀具激活为可进行金属化镀膜的金属氧化复合物。
4.根据权利要求1所述的封装结构,其特征在于,所述绝缘基材的材料包括能够被激光、等离子体或机械刀具激活为可进行金属化镀膜的金属氧化复合物。
5.根据权利要求4所述的封装结构,其特征在于,所述金属氧化复合物包括锌、铜、银、金、镍、钯、铂、钴、铑、铱、铟、铁、锰、铝、铬、钨、钒、钽、钛或其任意组合。
6.根据权利要求1所述的封装结构,其特征在于,所述图案化金属层还包括多个外部接垫,设置于所述绝缘基材相对于所述芯片的下表面并电性连接所述多个第一接点。
7.根据权利要求1所述的封装结构,其特征在于,所述导线架包括多个外部接垫,暴露于所述绝缘基材之外并电性连接所述多个第一接点。
8.根据权利要求1所述的封装结构,其特征在于,还包括第二导通孔,设置于所述绝缘基材上并电性连接所述导线架的接地电极,且所述其余的图案化金属层覆盖并电性连接所述第二导通孔。
9.根据权利要求1所述的封装结构,其特征在于,所述绝缘基材还包括元件设置槽,所述芯片及所述多个第一导通孔设置于所述元件设置槽内。
10.根据权利要求1所述的封装结构,其特征在于,所述导线架还包括至少一第二接点,所述绝缘基材还包括至少一开口,以暴露所述第二接点,所述线路部连接并覆盖所述开口及所述第二接点。
11.根据权利要求1所述的封装结构,其特征在于,所述绝缘基材还包括第二沟槽,其位于所述第一沟槽所框围的范围内并与所述第一沟槽之间维持间隙,所述线路部覆盖所述第二沟槽以及所述间隙,所述第二沟槽的底面低于所述外表面。
12.根据权利要求1所述的封装结构,其特征在于,所述图案化金属层的材料包括金、钯、银、锡、钨、钛、钒或铜。
13.根据权利要求1所述的封装结构,其特征在于,所述导线架包括金属柱阵列,且所述多个第一接点包括多个金属柱。
14.根据权利要求13所述的封装结构,其特征在于,所述导线架还包括芯片座,所述多个金属柱围绕所述芯片座设置。
15.根据权利要求14所述的封装结构,其特征在于,所述绝缘基材还包括凹槽,以暴露所述芯片座的顶面。
16.根据权利要求14所述的封装结构,其特征在于,所述芯片座的底面与各所述金属柱的下表面共平面。
17.根据权利要求14所述的封装结构,其特征在于,还包括多个第三导通孔,设置于所述绝缘基材上,所述绝缘基材覆盖所述芯片座的周缘区域,所述多个第三导通孔连接所述周缘区域,且所述线路部连接所述多个第三导通孔。
18.根据权利要求13所述的封装结构,其特征在于,所述导线架还包括芯片座,所述芯片座包括凹口,所述凹口的底面与所述金属柱阵列的所述下表面共平面。
19.根据权利要求18所述的封装结构,其特征在于,所述绝缘基材还包括凹槽,以暴露所述底面,且所述多个金属柱围绕所述芯片座。
20.根据权利要求19所述的封装结构,其特征在于,所述绝缘基材覆盖所述芯片座的周缘区域,且所述芯片座的下表面突出于所述绝缘基材的下表面。
21.根据权利要求20所述的封装结构,其特征在于,还包括多个第三导通孔,设置于所述绝缘基材上,所述绝缘基材覆盖所述芯片座的周缘区域,所述周缘区域围绕所述凹口,所述多个第三导通孔连接所述周缘区域,且所述线路部连接所述多个第三导通孔。
22.根据权利要求1所述的封装结构,其特征在于,还包括模塑料,覆盖所述芯片以及所述绝缘基材的上表面。
23.一种封装结构,其特征在于,包括:
导线架,包括多个第一接点以及至少一第二接点;
绝缘基材,包覆所述导线架并包括至少一开口,所述开口暴露所述第二接点;
多个第一导通孔,设置于所述绝缘基材上并连通所述多个第一接点;
图案化金属层,覆盖所述绝缘基材的外表面并包括第一沟槽以及线路部,所述线路部连接并覆盖所述多个第一导通孔、所述多个第一接点、所述开口及所述第二接点,所述第一沟槽环绕所述线路部,以使所述线路部与其余的所述图案化金属层电性绝缘,其中所述第一沟槽所暴露的所述绝缘基材的表面低于所述外表面;以及
芯片,设置于所述绝缘基材上并与所述线路部电性连接。
24.一种封装结构,其特征在于,包括:
基板,包括多个电性接点、有源表面以及相对所述有源表面的背面,所述多个电性接点设置于所述有源表面;
绝缘基材,设置于所述基板上并至少覆盖所述有源表面;
多个第一导通孔,设置于所述绝缘基材上并连通所述多个电性接点;
图案化金属层,覆盖所述绝缘基材的外表面并包括第一沟槽以及第一线路部,所述第一线路部连接并覆盖所述多个第一导通孔及所述多个电性接点,所述第一沟槽环绕所述线路部,以使所述第一线路部与其余的所述图案化金属层电性绝缘,其中所述第一沟槽所暴露的所述绝缘基材的表面低于所述外表面。
25.根据权利要求24所述的封装结构,其特征在于,所述绝缘基材还包括第二沟槽,其位于所述第一沟槽所框围的范围内并与所述第一沟槽之间维持间隙,所述线路部覆盖所述第二沟槽以及所述间隙,所述第二沟槽的底面低于所述外表面。
26.根据权利要求24所述的封装结构,其特征在于,所述基板还包括多个基板贯孔,贯穿所述基板并电性连通所述基板的所述有源表面以及所述背面。
27.根据权利要求25所述的封装结构,其特征在于,所述绝缘基材覆盖所述背面。
28.根据权利要求26所述的封装结构,其特征在于,还包括多个第二导通孔,贯穿覆盖所述背面的所述绝缘基材并电性连接所述多个基板贯孔,其中所述图案化金属层还包括第三沟槽以及第二线路部,所述第二线路部连接并覆盖所述多个第二导通孔,所述第二沟槽环绕所述第二线路部,以使所述第二线路部与其余的所述图案化金属层电性绝缘,其中所述第二沟槽所暴露的所述绝缘基材的表面低于所述外表面。
29.根据权利要求27所述的封装结构,其特征在于,还包括至少一芯片,设置于所述绝缘基材上并电性连接所述第二线路部。
30.根据权利要求24所述的封装结构,其特征在于,所述基板为晶片。
31.根据权利要求24所述的封装结构,其特征在于,所述基板的材料包括玻璃或硅。
32.一种封装结构,其特征在于,包括:
绝缘基材;
多个第一导通孔,贯穿所述绝缘基材;
图案化金属层,覆盖所述绝缘基材的外表面并包括第一沟槽、线路部以及多个外部接垫,所述线路部连接并覆盖所述多个第一导通孔,所述第一沟槽环绕所述线路部,以使所述线路部与其余的所述图案化金属层电性绝缘,其中所述第一沟槽所暴露的所述绝缘基材的表面低于所述外表面,所述多个外部接垫设置于所述绝缘基材相对于所述第一沟槽的下表面并电性连接所述多个第一导通孔且与所述其余的所述图案化金属层电性绝缘;以及
芯片,设置于所述绝缘基材上并与所述线路部电性连接。
33.根据权利要求32所述的封装结构,其特征在于,所述绝缘基材的材料包括环氧化合物、邻苯二甲酸二烯丙酯、苯并环丁烯、聚脂、丙烯酸酯、氟素聚合物、聚亚苯基氧化物、聚酰亚胺、酚醛树脂、聚砜、硅素聚合物、BT树脂、氰酸聚酯、聚乙烯、聚碳酸酯树脂、丙烯腈-丁二烯-苯乙烯共聚物、聚对苯二甲酸乙二酯、聚对苯二甲酸丁二酯、液晶高分子、聚酰胺、尼龙6、共聚聚甲醛、聚苯硫醚、聚碳酸脂、聚甲基丙烯酸甲脂、ABS树脂或环状烯烃共聚物。
34.根据权利要求32所述的封装结构,其特征在于,所述绝缘基材的材料不包括适于被激光、等离子体或机械刀具激活为可进行金属化镀膜的金属氧化复合物。
35.根据权利要求32所述的封装结构,其特征在于,所述绝缘基材的材料包括适于被激光、等离子体或机械刀具激活为可进行金属化镀膜的金属氧化复合物。
36.根据权利要求35所述的封装结构,其特征在于,所述金属氧化复合物包括锌、铜、银、金、镍、钯、铂、钴、铑、铱、铟、铁、锰、铝、铬、钨、钒、钽、钛或其任意组合。
37.根据权利要求32所述的封装结构,其特征在于,还包括第二导通孔,设置于所述绝缘基材上并电性连接所述导线架的接地电极,且所述其余的图案化金属层覆盖并电性连接所述第二导通孔。
38.根据权利要求32所述的封装结构,其特征在于,所述绝缘基材还包括元件设置槽,所述芯片及所述多个第一导通孔设置于所述元件设置槽内。
39.根据权利要求32所述的封装结构,其特征在于,所述绝缘基材还包括第二沟槽,其位于所述第一沟槽所框围的范围内并与所述第一沟槽之间维持间隙,所述线路部覆盖所述第二沟槽以及所述间隙,所述第二沟槽的底面低于所述外表面。
40.根据权利要求32所述的封装结构,其特征在于,所述图案化金属层的材料包括金、钯、银、锡、钨、钛、钒或铜。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW106111723A TWI626724B (zh) | 2017-04-07 | 2017-04-07 | 封裝結構 |
TW106111723 | 2017-04-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN108695290A true CN108695290A (zh) | 2018-10-23 |
Family
ID=63256098
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710366949.7A Pending CN108695290A (zh) | 2017-04-07 | 2017-05-23 | 封装结构 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10134668B2 (zh) |
CN (1) | CN108695290A (zh) |
TW (1) | TWI626724B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200112369A (ko) | 2019-03-22 | 2020-10-05 | 삼성전자주식회사 | 발광 소자 패키지 |
US20210074621A1 (en) * | 2019-09-10 | 2021-03-11 | Amazing Microelectronic Corp. | Semiconductor package |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101211903A (zh) * | 2006-12-29 | 2008-07-02 | 育霈科技股份有限公司 | 射频模块封装结构及其形成方法 |
TW200926377A (en) * | 2007-12-04 | 2009-06-16 | Phoenix Prec Technology Corp | Aluminum oxide-based substrate and method for manufacturing the same |
CN101894823A (zh) * | 2009-05-18 | 2010-11-24 | 欣兴电子股份有限公司 | 复合材料结构、包括复合材料的电路板结构与其形成方法 |
CN101902884A (zh) * | 2009-05-26 | 2010-12-01 | 欣兴电子股份有限公司 | 形成复合材料电路板结构的方法 |
CN102695368A (zh) * | 2011-03-23 | 2012-09-26 | 欣兴电子股份有限公司 | 线路板的内埋式线路结构的制造方法 |
CN104752391A (zh) * | 2010-03-04 | 2015-07-01 | 日月光半导体制造股份有限公司 | 具有单侧基板设计的半导体封装及其制造方法 |
CN104979300A (zh) * | 2014-04-03 | 2015-10-14 | 南茂科技股份有限公司 | 芯片封装结构及其制作方法 |
CN105280601A (zh) * | 2014-06-24 | 2016-01-27 | 思鹭科技股份有限公司 | 封装结构及封装基板结构 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8125064B1 (en) * | 2008-07-28 | 2012-02-28 | Amkor Technology, Inc. | Increased I/O semiconductor package and method of making same |
-
2017
- 2017-04-07 TW TW106111723A patent/TWI626724B/zh not_active IP Right Cessation
- 2017-05-23 CN CN201710366949.7A patent/CN108695290A/zh active Pending
- 2017-07-24 US US15/657,208 patent/US10134668B2/en not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101211903A (zh) * | 2006-12-29 | 2008-07-02 | 育霈科技股份有限公司 | 射频模块封装结构及其形成方法 |
TW200926377A (en) * | 2007-12-04 | 2009-06-16 | Phoenix Prec Technology Corp | Aluminum oxide-based substrate and method for manufacturing the same |
CN101894823A (zh) * | 2009-05-18 | 2010-11-24 | 欣兴电子股份有限公司 | 复合材料结构、包括复合材料的电路板结构与其形成方法 |
CN101902884A (zh) * | 2009-05-26 | 2010-12-01 | 欣兴电子股份有限公司 | 形成复合材料电路板结构的方法 |
CN104752391A (zh) * | 2010-03-04 | 2015-07-01 | 日月光半导体制造股份有限公司 | 具有单侧基板设计的半导体封装及其制造方法 |
CN102695368A (zh) * | 2011-03-23 | 2012-09-26 | 欣兴电子股份有限公司 | 线路板的内埋式线路结构的制造方法 |
CN104979300A (zh) * | 2014-04-03 | 2015-10-14 | 南茂科技股份有限公司 | 芯片封装结构及其制作方法 |
CN105280601A (zh) * | 2014-06-24 | 2016-01-27 | 思鹭科技股份有限公司 | 封装结构及封装基板结构 |
Also Published As
Publication number | Publication date |
---|---|
US20180294218A1 (en) | 2018-10-11 |
TW201838120A (zh) | 2018-10-16 |
US10134668B2 (en) | 2018-11-20 |
TWI626724B (zh) | 2018-06-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5619276B2 (ja) | 誘電体塊上に端子を有するマイクロ電子パッケージ | |
US10490478B2 (en) | Chip packaging and composite system board | |
EP1091401B1 (en) | Semiconductor device package and process for production | |
US7663224B2 (en) | Semiconductor BGA package having a segmented voltage plane | |
KR20090060132A (ko) | 전자기적으로 격리된 집적회로 패키지 시스템 | |
TWI646607B (zh) | 無芯積體電路封裝系統及其製造方法 | |
CN105280601B (zh) | 封装结构及封装基板结构 | |
US9859193B2 (en) | Package structure | |
CN102244057A (zh) | 半导体封装及其制造方法 | |
US10763220B2 (en) | Systems and methods for electromagnetic interference shielding | |
CN101431031B (zh) | 半导体封装件及其制法 | |
CN108695290A (zh) | 封装结构 | |
CN102709271A (zh) | 具有减小尺寸的堆叠晶片水平封装 | |
CN108447842A (zh) | 一种指纹芯片的封装结构以及封装方法 | |
CN1071493C (zh) | 一种tab带和使用该tab带的半导体器件 | |
TWI606560B (zh) | 封裝結構 | |
CN110911541B (zh) | 发光二极管封装结构及其制造方法 | |
CN108666294A (zh) | 封装结构 | |
US9801282B2 (en) | Package structure | |
CN202940236U (zh) | 封装基板构造 | |
CN208256659U (zh) | 一种指纹芯片的封装结构 | |
CN108307590A (zh) | 封装结构及封装结构的制作方法 | |
CN103247578A (zh) | 半导体承载件暨封装件及其制法 | |
TWI232706B (en) | Manufacturing method of mounting substrate and manufacturing method of circuit device | |
TW202218083A (zh) | 封裝結構及該封裝結構的製備方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20181023 |