CN108666313B - 改善动态随机存储器行锤现象的半导体结构及其制作方法 - Google Patents
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Abstract
本发明公开一种改善动态随机存储器中行锤现象的半导体结构及其制作方法。该半导体结构包含有一半导体基底,具有一第一导电型及一第一掺杂浓度;一主动区域,位于该半导体基底上,其中该主动区域的一长轴沿着一第一方向延伸;一沟槽绝缘结构,邻接该主动区域的一端面;一通过栅极,埋设于该沟槽绝缘结构内,其中该通过栅极沿着一第二方向延伸,且该第二方向不平行于该第一方向;以及一区域掺杂区,具有一第二导电型及一第二掺杂浓度,设于该主动区域的该端面上。
Description
技术领域
本发明涉及半导体技术领域,特别是涉及一种可以改善动态随机存储器(DRAM)的行锤(row hammer)现象的半导体结构及其制作方法。
背景技术
当动态随机存取存储器(DRAM)的目标行在一段时间内被激活太多次时,存储在邻近目标行的相邻行的数据资料很可能会丢失或被干扰。更具体地说,存储在相邻行的数据资料会由于目标行的频繁激活而产生的信号串扰而损坏(data corruption),此现象又被称为“行锤(row hammer)”。
随着DRAM设计密度的增加,行锤现象会越来越严重,已成为该技术领域亟待解决的一个问题。
发明内容
本发明的主要目的在于提供一种改良的半导体结构及其制作方法,以解决现有技术技术的不足与缺点。
根据本发明一实施例,提出一种半导体结构,包含有一半导体基底,具有一第一导电型及一第一掺杂浓度;一主动区域,位于该半导体基底上,其中该主动区域的一长轴沿着一第一方向延伸;一沟槽绝缘结构,邻接该主动区域的一端面;一通过栅极,埋设于该沟槽绝缘结构内,其中该通过栅极沿着一第二方向延伸,且该第二方向不平行于该第一方向;以及一区域掺杂区,具有一第二导电型及一第二掺杂浓度,设于该主动区域的该端面上。
根据本发明另一实施例,提出一种半导体结构的制作方法。
首先提供一半导体基底,具有一第一导电型。在该半导体基底上形成至少一主动区域,其中该主动区域的一长轴沿着一第一方向延伸。进行一第一斜角度离子注入制作工艺,在该主动区域的一端面上的一第一深度以上形成一第一掺杂区,具有一第二导电型。再进行一第二斜角度离子注入制作工艺,在该主动区域的该端面上的一第二深度以上形成一第二掺杂区,具有一第三导电型,其中该第三导电型与该第二导电型互为相反电性,如此于该第一深度与该第二深度之间构成一具有该第二导电型的区域掺杂区。再于该主动区域周围形成一沟槽绝缘结构,邻接该主动区域的该端面。
为让本发明上述目的、特征及优点能更明显易懂,下文特举优选实施方式,并配合所附的附图,作详细说明如下。然而优选实施方式与附图仅供参考与说明用,并非用来对本发明加以限制者。
附图说明
图1为本发明一实施例所绘示的半导体结构的部分布局示意图;
图2为图1中沿着切线I-I’所视的剖面示意图;
图3至图6为本发明实施例所绘示的半导体结构的制作方法的剖面示意图。
主要元件符号说明
1 半导体结构
32 第一斜角度离子注入制作工艺
34 第二斜角度离子注入制作工艺
101、102、103 主动区域
102a、102b 端面
121 掺杂区
122 掺杂区
200 沟槽绝缘结构
201 沟槽填充硅氧层
210 阻障层
220 钨金属层
230 上盖介电层
302a、302b 区域掺杂区
312a、312b 第一掺杂区
341a、341b 第二掺杂区
400 绝缘沟槽
401 硅氧垫层
402 氮化硅层
d1 第一深度
d2 第二深度
AA 主动区域
BWL1~BWL4 埋入字符线
BC 位线接触区
SC 储存节点接触区
PG、PG1、PG2 通过栅极
具体实施方式
在本发明的以下详细描述中,所参考的附图也构成说明书的一部分,其例示出可具体实践本发明的实施例。这些实施例已描述足够的细节以使本领域的技术人员能够实践本发明。
其它实施例可以被利用,并且可以做出结构,逻辑和电性上的变化而不脱离本发明的范围。下面的详细说明,因此,不被视为具有限制意义,并且本发明的范围是由所附权利要求而定。
在进一步的描述优选实施例之前,以下先针对全文中使用的特定用语进行说明。
用语“蚀刻”在本文中通常用来描述图案化材料的制作工艺,使得在蚀刻完成后的材料的至少一部分能被留下。例如,应该理解的是,蚀刻硅的方法包括在硅上面图案化一掩模层(例如,光致抗蚀剂或硬掩模),然后从不被掩模层保护的区域去除硅。因此,在蚀刻过程完成,由掩模保护的区域的硅会留下。
然而,在另一实例中,刻蚀也可以指不使用掩模的方法,但在蚀刻过程完成后仍留下至少一部分的材料。上面的说明用来从区分“刻蚀”及“去除”。当“蚀刻”一材料,该材料的至少一部分在处理结束后被保留。与此相反,“去除”材料时,基本上所有的材料是在过程中除去。然而,在一些实施例中,“去除”被认为是一个广义的用语,可以包括刻蚀。
用语“形成”、“沉积”或术语“设置”在下文中用于描述施加一层材料于基底的行为。这样的用语是为了描述任何可能的层形成技术,包括但不限于,热生长、溅射、蒸发、化学气相沉积、外延生长、电镀等。
根据各种实施例,例如,沉积可以任何适当的公知方法进行。例如,沉积可以包括任何生长、镀层,或转移材料到基底上的过程。一些公知的技术包括物理气相沉积(PVD)、化学气相沉积(CVD)、电化学沉积(ECD)、分子束外延(MBE)、原子层沉积(ALD)、等离子体增强CVD(PECVD)等。
全文中所描述的“基底”,最常见的应该是硅基底。然而,基底也可以是任何半导体材料,例如锗、砷化镓、磷化铟等。在其它实施例的,基底可以是不导电的,例如玻璃或蓝宝石晶片。
请参阅图1及图2,其中图1为依据本发明一实施例所绘示的半导体结构1的部分布局示意图,图2为图1中沿着切线I-I’所视的剖面示意图。本发明半导体结构1特别适用于具有埋入字符线的动态随机存储器(DRAM),可以有效改善动态随机存储器的行锤(rowhammer)现象。
图1例示一动态随机存储器的部分布局,其中包括形成在半导体基底100内的多个主动区域(AA),各主动区域为一长条状结构,其长轴沿着一第一方向(或AA方向)延伸。根据本发明实施例,图1中的多个主动区域以交错(staggered)方式排列,换言之,不同行的主动区域(例如,主动区域101与102、主动区域102与103)会彼此部分重叠。
根据本发明实施例,围绕在各个主动区域(例如,主动区域101、102、103)周围的是沟槽绝缘结构200,将主动区域101、102、103彼此电性绝缘隔离。在半导体基底100内另形成有多条直线型的埋入字符线(buried word line,BWL),例如,BWL1~BWL4,沿着一第二方向(或参考坐标y轴方向)延伸。埋入字符线BWL1~BWL4分别穿过多个主动区域,例如,埋入字符线BWL2及BWL3穿过主动区域102,将主动区域102区隔成三个区域,分别是埋入字符线BWL2及BWL3之间的位线接触区(BC)及位于主动区域102两端的存储节点接触区(SC)。
根据本发明实施例,埋入字符线BWL1及BWL4分别通过主动区域102旁的沟槽绝缘结构200,并且十分靠近主动区域102的存储节点接触区的相对两端面102a及102b。根据本发明实施例,通过主动区域102旁的沟槽绝缘结构200,且靠近主动区域102相对两端面102a及102b的埋入字符线BWL1及BWL4又被称为通过栅极(passing gate,PG)。
如图2所示,半导体基底100可以包括,但不限于,硅基底,含硅基底,硅上氮化镓(GaN-on-silicon或III-V族的其他材料),硅上石墨烯(graphene-on-silicon)基底,或硅覆绝缘(SOI)基底。根据本发明实施例,半导体基底100具有一第一导电型,例如,P型掺杂,及一第一掺杂浓度,例如,介于1E18~2E19atoms/cm3,但不限于此。
根据本发明实施例,沟槽绝缘结构200围绕主动区域102且邻接主动区域102的端面102a及102b。各沟槽绝缘结构200包含沟槽填充硅氧层201,以及埋设于沟槽填充硅氧层201内的通过栅极PG,例如,通过栅极PG1或PG2。根据本发明实施例,通过栅极PG的埋入范围介于深度第一深度d1与第二深度d2之间,其中第一深度d1介于第二深度d2介于
根据本发明实施例,通过栅极PG包含一阻障层210,例如氮化钛层,及一钨金属层220,但不限于此。根据本发明实施例,通过栅极PG上面还可以被一上盖介电层230覆盖住。根据本发明实施例,通过栅极PG与半导体基底100之间还可以另设有一硅薄膜(图未示)。
根据本发明实施例,埋入字符线BWL2及BWL3之间的位线接触区(BC)内形成有一掺杂区121,具有一第二导电型,例如N型,根据本发明实施例,掺杂区121为N_掺杂区。而位于主动区域102两端的储存节点接触区(SC)内形成有一掺杂区122,具有第二导电型,例如N型,根据本发明实施例,掺杂区122为N_掺杂区。
根据本发明实施例,通过栅极PG1或PG2底部的深度,约略等于第一深度d1,会略深于埋入字符线BWL2及BWL3底部的深度。
根据本发明实施例,本发明半导体结构1包含一区域掺杂区302a及302b,具有一第二导电型及一第二掺杂浓度,分别设于主动区域102的两相对端面102a及102b上。根据本发明实施例,区域掺杂区302a及302b仅在端面102a及102b的第一深度d1与第二深度d2之间延伸,且分别正对通过栅极PG1及PG2。
根据本发明实施例,区域掺杂区302a及302b与位于主动区域102两端的储存节点接触区(SC)内形成的掺杂区122仍保持一段距离,彼此不相接触。
根据本发明实施例,区域掺杂区302a及302b,具有第二导电型及第二掺杂浓度,其中所述第二导电型是P型,例如,区域掺杂区302a及302b是掺杂铟,所述第二掺杂浓度介于1E18~5E19atoms/cm3。根据本发明实施例,区域掺杂区302a及302b的第二掺杂浓度大于半导体基底100的第一掺杂浓度,由此降低通过栅极PG1及PG2与端面102a及102b的之间的电性耦合(lower Q)。
根据本发明另一实施例,区域掺杂区302a及302b,具有第二导电型及第二掺杂浓度,其中所述第二导电型是P型,例如,区域掺杂区302a及302b是掺杂铟,所述第二掺杂浓度介于1E18~5E19atoms/cm3。根据本发明实施例,区域掺杂区302a及302b的第二掺杂浓度小于半导体基底100的第一掺杂浓度。
根据本发明又另一实施例,区域掺杂区302a及302b,具有第二导电型及第二掺杂浓度,其中所述第二导电型是N型,例如,区域掺杂区302a及302b是掺杂砷,所述第二掺杂浓度介于1E18~5E19atoms/cm3。
请参阅图3至图6,其为依据本发明实施例所绘示的半导体结构的制作方法的剖面示意图。
首先,如图3所示,提供一半导体基底100,具有一第一导电型,例如P型掺杂。在半导体基底100上形成至少一主动区域102及环绕主动区域102的绝缘沟槽400,其中主动区域102的长轴沿着第一(或AA)方向延伸(如图1中所示)。图3显示刚刚完成沟槽蚀刻,尚未在绝缘沟槽400中填入硅氧层的中间半导体结构。此时,在主动区域102上仍有硅氧垫层401及氮化硅层402。
如图4所示,接着进行一第一斜角度离子注入制作工艺32,利用氮化硅层402的遮蔽效果,在主动区域102的相对两端面102a及102b上的一第一深度d1以上,自动对准形成一第一掺杂区312a及312b,具有一第二导电型。根据本发明实施例,所述第一深度d1介于根据本发明实施例,第一斜角度离子注入制作工艺32的离子注入方向均为平行前述第一(或AA)方向,注入角度(掺质入射方向与水平面的夹角)例如为40°。
如图5所示,接着进行一第二斜角度离子注入制作工艺34,同样再利用氮化硅层402的遮蔽效果,在主动区域102的相对两端面102a及102b上的一第二深度d2以上,自动对准形成一第二掺杂区341a及341b,具有一第三导电型,其中第二掺杂区341a及341b的第三导电型与第一掺杂区312a及312b的第二导电型互为相反电性,如此于第一深度d1与第二深度d2之间构成具有第二导电型的区域掺杂区302a及302b。根据本发明实施例,所述第二深度d2介于根据本发明实施例,第二斜角度离子注入制作工艺34的离子注入方向均为平行前述第一(或AA)方向,注入角度例如为29°。
根据本发明实施例,第一斜角度离子注入制作工艺32的掺质为铟,离子注入能量为10keV,离子注入剂量为1E13atoms/cm2,第二斜角度离子注入制作工艺34的掺质为砷,离子注入能量为10keV,离子注入剂量为1E13atoms/cm2。
根据本发明另一实施例,第一斜角度离子注入制作工艺32的掺质为砷,离子注入能量为10keV,离子注入剂量为1E13atoms/cm2,第二斜角度离子注入制作工艺34的掺质为铟,离子注入能量为10keV,离子注入剂量为1E13atoms/cm2。
如图6所示,接着于主动区域102周围形成一沟槽绝缘结构200,包括以化学气相沉积制作工艺于绝缘沟槽400中填入硅氧层201,邻接主动区域102的端面102a及102b。接着,利用光刻制作工艺及蚀刻制作工艺,在半导体基底100中形成埋入字符线的沟槽,再于埋入字符线的沟槽中形成埋入字符线(包括通过栅极),并以上盖介电层230覆盖住埋入字符线。后续形成位线接触结构、存储节点接触结构、位线、电容结构等步骤为该技术领域周知技术,故不再赘述。
以上所述仅为本发明之优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (20)
1.一种半导体结构,包含有:
半导体基底,具有第一导电型及第一掺杂浓度;
主动区域,位于该半导体基底上,其中该主动区域的一长轴沿着一第一方向延伸;
沟槽绝缘结构,邻接该主动区域的一端面;
埋入字符线的沟槽,位于该主动区域中;
通过栅极,埋设于该沟槽绝缘结构内,其中该通过栅极沿着一第二方向延伸,且该第二方向不平行于该第一方向;以及
区域掺杂区,具有第二导电型及第二掺杂浓度,设于该主动区域的该端面上并且不接触该埋入字符线的沟槽。
2.如权利要求1所述的半导体结构,其中该第一导电型是P型,该第二导电型是P型。
3.如权利要求2所述的半导体结构,其中该区域掺杂区是掺杂铟。
4.如权利要求3所述的半导体结构,其中该第二掺杂浓度介于1E18~5E19atoms/cm3。
5.如权利要求4所述的半导体结构,其中该第二掺杂浓度大于该第一掺杂浓度。
6.如权利要求4所述的半导体结构,其中该第二掺杂浓度小于该第一掺杂浓度。
7.如权利要求1所述的半导体结构,其中该第一掺杂浓度介于1E18~2E19atoms/cm3。
8.如权利要求1所述的半导体结构,其中该第一导电型是P型,该第二导电型是N型。
9.如权利要求8所述的半导体结构,其中该区域掺杂区是掺杂砷。
10.如权利要求9所述的半导体结构,其中该第二掺杂浓度介于1E18~5E19atoms/cm3。
11.如权利要求1所述的半导体结构,其中该区域掺杂区仅在该端面的一第一深度与一第二深度之间延伸,且正对该通过栅极。
13.如权利要求1所述的半导体结构,其中该沟槽绝缘结构包含硅氧层,介于该区域掺杂区与该通过栅极之间。
14.一种半导体结构的制作方法,包含有:
提供一半导体基底,具有一第一导电型;
在该半导体基底上形成至少一主动区域,其中该主动区域的一长轴沿着一第一方向延伸;
进行一第一斜角度离子注入制作工艺,于该主动区域的一端面上的一第一深度以上形成一第一掺杂区,具有一第二导电型;
进行一第二斜角度离子注入制作工艺,在该主动区域的该端面上的一第二深度以上形成一第二掺杂区,具有一第三导电型,其中该第三导电型与该第二导电型互为相反电性,如此于该第一深度与该第二深度之间构成一具有该第二导电型的区域掺杂区;以及
在该主动区域周围形成一沟槽绝缘结构,邻接该主动区域的该端面。
15.如权利要求14所述的半导体结构的制作方法,其中该第一斜角度离子注入制作工艺与该第二斜角度离子注入制作工艺的离子注入方向均为平行该第一方向。
16.如权利要求14所述的半导体结构的制作方法,其中该第一斜角度离子注入制作工艺是以一第一注入角度进行离子注入,该第二斜角度离子注入制作工艺是以一第二注入角度进行离子注入,其中该第一注入角度大于该第二注入角度。
17.如权利要求16所述的半导体结构的制作方法,其中该第一注入角度为40°,而该第二注入角度为29°。
18.如权利要求14所述的半导体结构的制作方法,其中该第一斜角度离子注入制作工艺的掺质为铟,离子注入能量为10keV,离子注入剂量为1E13atoms/cm2,该第二斜角度离子注入制作工艺的掺质为砷,离子注入能量为10keV,离子注入剂量为1E13atoms/cm2。
19.如权利要求14所述的半导体结构的制作方法,其中该第一斜角度离子注入制作工艺的掺质为砷,离子注入能量为10keV,离子注入剂量为1E13atoms/cm2,该第二斜角度离子注入制作工艺的掺质为铟,离子注入能量为10keV,离子注入剂量为1E13atoms/cm2。
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