CN108417476A - Wafer top layer oxide layer processing method - Google Patents
Wafer top layer oxide layer processing method Download PDFInfo
- Publication number
- CN108417476A CN108417476A CN201810120437.7A CN201810120437A CN108417476A CN 108417476 A CN108417476 A CN 108417476A CN 201810120437 A CN201810120437 A CN 201810120437A CN 108417476 A CN108417476 A CN 108417476A
- Authority
- CN
- China
- Prior art keywords
- wafer
- top layer
- processing method
- border region
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
- H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a kind of wafer top layer oxide layer processing methods, after wafer completes top layer oxide coating process, it is exposed using negtive photoresist technique, and it carries out WEE edge of wafer exposure-processed and is insoluble in developer solution in negtive photoresist exposure area after exposure, the deposit retained after etching can cover in wafer and stay border region, avoid probe and stay the contact pads of border region.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacture and testing fields, particularly relate to a kind of wafer top layer oxide layer processing
Method.
Background technology
After top layer's metal routing of wafer manufacture is completed, it will usually deposit one layer of oxide or nitrogen oxides, only exist
Windowing at pad plays the role of anti-moisture and soil-repellent dye antistatic, protects internal circuit, referred to as passivation layer.
Stay border region of this layer of protective layer other than the trimming 3mm of wafer periphery is typically that (edge of wafer exposes using WEE processing
Light Wafer Edge Exposure) removed comprehensively, as shown in Figure 1, the residual figure of the invalid chip lower layer in periphery can be to rear
Continuous test generates interference, reduces yields or even probe is burnt in short circuit.
Even if process choice can allow the invalid chip in periphery if not doing WEE processing (edge of wafer exposure) full sheet exposure technology
Pad be also exposed, as shown in Figure 2.These invalid contact pads equally can cause to do to test probe to test
It disturbs.
Invention content
Technical problem to be solved by the present invention lies in a kind of wafer top layer oxide layer processing method is provided, make edge of wafer
Staying border region, pad is not contacted with probe during the test.
To solve the above problems, wafer top layer oxide layer processing method of the present invention, top layer oxidation is completed in wafer
It after layer process, is exposed using negtive photoresist technique, and to staying border region to carry out WEE processing.It is described stay border region be from wafer it is outermost
Along the range for taking 3~5mm toward the center of circle along radial direction.
Further, due to using negtive photoresist technique, negtive photoresist exposure area is insoluble in developer solution, the deposit of reservation after exposure
Object can cover in wafer and stay border region, avoid probe and stay the pad or pattern contacts of border region.
Further, when carrying out WEE processing interior layout wires designs, due to using negtive photoresist technique, placement-and-routing to set
Meter will carry out negating processing.
Wafer top layer oxide layer processing method of the present invention handles the time due to using negtive photoresist technique carrying out WEE
Photoresist is retained, and illuvium is retained after etching, the deposit that when follow-up test retains be avoided that probe directly with stay border region
Contact pads and lead to the interference to test.
Description of the drawings
Fig. 1 is the existing schematic diagram that WEE processing is carried out to wafer, and wafer outer ring stays the protective layer of border region to remove
Processing.
Fig. 2 is the existing schematic diagram handled without WEE wafer, and wafer outer ring stays the protective layer of border region not go
It removes, but stays the pad of border region still to expose after exposing.
Fig. 3 is the schematic diagram that the present invention carries out wafer WEE processing, and wafer outer ring stays the protective layer of border region to be protected in figure
It stays.
Specific implementation mode
Wafer top layer oxide layer processing method of the present invention is adopted after wafer completes top layer oxide coating process
It is exposed with negtive photoresist technique and carries out WEE processing.Exposure area is insoluble in developer solution, the shallow lake of reservation to negtive photoresist technique after exposure
Product object can cover in wafer and stay border region, as shown in figure 3, avoiding probe and staying the contact pads of border region.
Due to using negtive photoresist technique, entire chip layout wires design will carry out negating processing, to adapt to the characteristic of negtive photoresist.
It these are only the preferred embodiment of the present invention, be not intended to limit the present invention.Those skilled in the art is come
It says, the invention may be variously modified and varied.All within the spirits and principles of the present invention, any modification made by is equal
Replace, improve etc., it should all be included in the protection scope of the present invention.
Claims (5)
1. a kind of wafer top layer oxide layer processing method, it is characterised in that：After wafer completes top layer oxide coating process, use
Negtive photoresist technique is exposed, and to staying border region to carry out WEE edge of wafer exposure-processeds.
2. wafer top layer oxide layer processing method as described in claim 1, it is characterised in that：It is described that stay border region be from wafer
Most outer takes the range of 3~5mm along radial direction toward the center of circle.
3. wafer top layer oxide layer processing method as described in claim 1, it is characterised in that：Using negtive photoresist technique, in wafer
The negtive photoresist exposure area of wafer outer rim is insoluble in developer solution after boundary exposure processing.
4. wafer top layer oxide layer processing method as claimed in claim 3, it is characterised in that：The deposit that negtive photoresist technique retains
Wafer can be covered in and stay border region, avoid probe and stay the pad or pattern contacts of border region.
5. wafer top layer oxide layer processing method as described in claim 1, it is characterised in that：It is carrying out at edge of wafer exposure
When the interior layout wires design of reason, due to using negtive photoresist technique, placement-and-routing's design of entire chip to carry out negating processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810120437.7A CN108417476A (en) | 2018-02-07 | 2018-02-07 | Wafer top layer oxide layer processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810120437.7A CN108417476A (en) | 2018-02-07 | 2018-02-07 | Wafer top layer oxide layer processing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108417476A true CN108417476A (en) | 2018-08-17 |
Family
ID=63127830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810120437.7A Pending CN108417476A (en) | 2018-02-07 | 2018-02-07 | Wafer top layer oxide layer processing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108417476A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102147572A (en) * | 2010-02-09 | 2011-08-10 | 台湾积体电路制造股份有限公司 | Wafer edge exposure module and wafer edge exposure method |
| CN102479688A (en) * | 2010-11-29 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Method of wafer surface photoresistance edge removal |
| CN103307983A (en) * | 2012-03-09 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | Wafer edge exposure process detecting method |
| CN105161412A (en) * | 2015-08-31 | 2015-12-16 | 上海华力微电子有限公司 | Method for improving wafer edge product yield |
| CN106683986A (en) * | 2016-08-22 | 2017-05-17 | 上海华力微电子有限公司 | Method for improving wafer edge defects |
| CN106803482A (en) * | 2017-02-14 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | A kind of method for reducing crystal round fringes yield test problem |
-
2018
- 2018-02-07 CN CN201810120437.7A patent/CN108417476A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102147572A (en) * | 2010-02-09 | 2011-08-10 | 台湾积体电路制造股份有限公司 | Wafer edge exposure module and wafer edge exposure method |
| CN102479688A (en) * | 2010-11-29 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Method of wafer surface photoresistance edge removal |
| CN103307983A (en) * | 2012-03-09 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | Wafer edge exposure process detecting method |
| CN105161412A (en) * | 2015-08-31 | 2015-12-16 | 上海华力微电子有限公司 | Method for improving wafer edge product yield |
| CN106683986A (en) * | 2016-08-22 | 2017-05-17 | 上海华力微电子有限公司 | Method for improving wafer edge defects |
| CN106803482A (en) * | 2017-02-14 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | A kind of method for reducing crystal round fringes yield test problem |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20180817 |
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| WD01 | Invention patent application deemed withdrawn after publication |