WO2017114404A1

WO2017114404A1 - Method for protecting edges of silicon wafer and lithography exposure device

Info

Publication number: WO2017114404A1
Application number: PCT/CN2016/112563
Authority: WO
Inventors: 张家锦; 章磊
Original assignee: 上海微电子装备（集团）股份有限公司
Priority date: 2015-12-30
Filing date: 2016-12-28
Publication date: 2017-07-06
Also published as: CN106935482A; TW201723665A

Abstract

A method for protecting edges of a silicon wafer and a lithography exposure device, comprising: prior to exposure, sequentially coating a metal seed layer (21) and a negative photoresist (22) on a surface of a silicon wafer (20); during exposure, forming an integrated circuit pattern region (40) on the silicon wafer (20) by means of a mask (30), and forming an edge-protection region (41) at the edges of the silicon wafer (20) by means of a light-blocking member (31), wherein an optical channel is provided between the light-blocking member (31) and the mask (30); and forming an edge-buffer region (42) between the integrated circuit pattern region (40) and the edge-protection region (41) by means of the optical channel; after exposure, developing the silicon wafer (20), so as to remove the negative photoresist (22) in the edge-protection region (41). By means of the edge-buffer region (42), the method can reduce defects caused by the edge-protection region (41) in a edge-chip pattern of the silicon wafer (20) during the developing process, due to physical impact and chemical reaction of a developer; the method can also protect the edge-chip pattern of the silicon wafer (20) in subsequent processing procedures, thus improving the yield of edge chips of the silicon wafer (20).

Description

Silicon wafer edge protection method and lithographic exposure apparatus

Technical field

The invention relates to a method for protecting the edge of a silicon wafer and a lithographic exposure apparatus, which are applied to the field of semiconductor technology.

Background technique

In the semiconductor field, silicon edge protection technology is widely used in advanced packaging manufacturing processes, especially in lithography processes related to silicon metal plating, such as lithography such as BUMP (bump process) and RDL (rewiring layer technology). Silicon edge protection technology is required in all key processes. As shown in FIG. 1 and FIG. 2, a metal seed layer 21 is usually pre-plated on the surface of the silicon wafer 20, and then an integrated circuit pattern region 40 (ie, a patterned photoresist) is formed on the metal seed layer 21 by a photolithography process. The metal seed layer 21 at the edge of the silicon wafer 20 is exposed. In the metal plating process of the silicon wafer 20, the metal seed layer 21 exposed through the edge of the silicon wafer 20 is connected to the power supply cathode 11, so that the entire surface of the silicon wafer 20 is made electrically conductive, and a circuit is formed with the positively charged anode 10 through the current. The metal ion flow is caused to form a metal deposit 12 on the surface of the metal seed layer 21 which is not covered by the patterned photoresist, that is, the metal plating process is completed. Therefore, the edge of the silicon wafer 20 needs to be specially protected in the photolithography process to ensure that the metal seed layer 21 at the edge of the silicon wafer 20 is in a bare state, meeting the requirements of the subsequent plating process. In the photolithography process such as BUMP and RDL, a negative photoresist is used, and the negative photoresist forms an insoluble matter after illumination, that is, it remains after the lithography exposure process. As shown in FIG. 3, the prior art silicon wafer edge protection method firstly forms a metal seed layer 21 and a photoresist layer 22 on the silicon wafer 20. During the exposure process, the integrated circuit pattern region 40 is formed on the silicon wafer 20 through the reticle 30, while the edge position of the silicon wafer 20 is blocked by the light shielding member 31, so that the edge of the silicon wafer 20 is not exposed to light, forming the edge protection region 41. After the exposure, the negative photoresist at the edge of the silicon wafer 20 is removed by reaction with the developer, and the metal seed layer 21 at the bottom of the edge of the silicon wafer 20 is exposed after development, thereby meeting the needs of metal plating.

In the processing process of the semiconductor wafer, the edge position of the silicon wafer is relatively weak against the defect. That is, the edge effect of the silicon wafer. As shown in FIGS. 3 and 4, during the exposure process, an integrated circuit pattern region 40 is formed on the silicon wafer 20 through the reticle 30, and the chip pattern at the edge of the integrated circuit pattern region 40 is connected to the edge protection region 41 for development. During the process of removing the negative photoresist of the edge protection zone 41, due to the chemical reaction and physical impact of the developer, the chip pattern of the edge may be dumped or deformed, which directly reduces the chip yield of the entire wafer. Corrosion of the plating solution may also cause damage to the edge chip pattern during the later plating process. Therefore, the prior art adopts the processing method of the adjacent integrated circuit pattern region 40 and the edge protection region 41, so that the edge chip pattern of the silicon wafer 20 is easily damaged, resulting in a decrease in the yield of the entire silicon wafer.

Summary of the invention

The technical problem to be solved by the present invention is to provide a method for protecting the edge of a silicon wafer and a lithographic exposure apparatus.

In order to achieve the above object, the present invention is implemented by the following technical solution: a method for protecting a silicon wafer edge, comprising:

Step 1. Prior to exposure, a metal seed layer and a negative photoresist are sequentially coated on the surface of the silicon wafer;

Step 2. When exposing, forming an integrated circuit pattern region on the silicon wafer through the reticle, forming an edge protection region on the edge of the silicon wafer through the light shielding member, and providing an optical path between the light shielding member and the reticle; An optical path channel forms an edge buffer between the integrated circuit pattern area and the edge protection area;

Step 3. After exposure, the silicon wafer is developed to remove the negative photoresist of the edge protection region.

Preferably, the optical path is surrounded by a periphery of the reticle.

Preferably, the shape of the edge buffer is a circular ring or a positive polygonal ring shape.

Preferably, the resolution of the negative photoresist is greater than or equal to 2 mm.

Preferably, the metal seed layer uses a copper seed layer or an alloy seed layer.

Preferably, the reticle and the light blocking member are in the same horizontal position.

In order to achieve the above object, the present invention also provides the following technical solutions: a lithography exposure An optical device comprising a reticle aligned with an exposure position on the silicon wafer, forming an integrated circuit pattern region upon exposure; the light shielding member is aligned with an edge position on the silicon wafer to form an edge upon exposure a protection zone; an optical path is provided between the reticle and the light blocking member to form an edge buffer during exposure.

Preferably, the optical path is surrounded by a periphery of the reticle.

Preferably, the sum of the widths of the edge protection zone and the edge buffer is less than or equal to 5 mm.

Preferably, the width of the edge protection zone is greater than or equal to 3 mm.

Preferably, the edge buffer has a width of 1 to 2 mm.

Compared with the prior art, the method for protecting the edge of the silicon wafer and the lithographic exposure apparatus of the present invention form an integrated circuit pattern region on the silicon wafer through the reticle, and form an edge protection region on the edge of the silicon wafer through the light shielding member, and pass the reticle And an optical path between the light-shielding member forms an edge buffer between the integrated circuit pattern area and the edge protection area, and the edge buffer is used to reduce the edge protection area during the development process due to the chemical reaction and physical impact of the developer on the silicon wafer The defects caused by the edge chip pattern can also protect the chip edge chip pattern in the subsequent processing process, improve the yield of the silicon chip edge chip, and develop the metal seed layer at the bottom of the silicon wafer edge through the development of the edge protection region. Exposed to meet the needs of metal plating, the entire edge-optimized structure is completed by one exposure, which improves the process adaptability and optimizes the process.

DRAWINGS

Figure 1 is a schematic diagram of a silicon metal plating process;

2 is an effect diagram of a silicon metal plating process;

3 is a schematic flow chart of a method for protecting a silicon chip edge chip in the prior art;

4 is a schematic diagram showing the effect of a method for protecting a silicon chip edge chip in the prior art;

FIG. 5 is a schematic flow chart of a method for protecting a silicon chip edge chip according to an embodiment of the present invention; FIG.

6 is a schematic diagram of an edge optimization structure in an embodiment of the present invention;

7 is a schematic diagram of an edge buffer in an embodiment of the present invention;

FIG. 8 is a schematic diagram of an edge buffer according to an embodiment of the present invention; FIG.

FIG. 9 is a schematic diagram showing the effect of a method for protecting a silicon chip edge chip according to an embodiment of the present invention.

The figure shows: 10, anode; 11, cathode; 12, metal deposition; 20, silicon wafer; 21, metal seed layer; 22, negative photoresist; 30, reticle; 31, shading; 40, integration Circuit pattern area; 41, edge protection area; 42, edge buffer; D, edge protection area width; S, edge buffer width; W, edge protection area and edge buffer width.

detailed description

The present invention will be described in detail below with reference to the accompanying drawings:

The lithographic exposure apparatus provided by the present invention comprises a light source, an optical system, a workpiece stage, a reticle and a light blocking member, wherein, as shown in FIG. 5, the reticle 30 is aligned with an exposure position on the silicon wafer 20 during exposure. The light blocking member 31 is aligned with the edge position on the silicon wafer 20. An optical path is disposed between the reticle 30 and the light blocking member 31, and the optical path is surrounded by the periphery of the reticle 30.

Specifically, before exposure, the metal seed layer 21 is pre-plated on the surface of the silicon wafer 20, the negative photoresist 22 is coated on the metal seed layer 21 of the silicon wafer 20, and the processed silicon wafer 20 is placed on the workpiece stage. And pre-aligned. Preferably, the metal seed layer 21 is a copper seed layer or an alloy seed layer.

At the time of exposure, the light source is irradiated onto the reticle 30 and the light-shielding member 31 through the optical system, the integrated circuit pattern region 40 is formed on the silicon wafer 20 through the reticle 30, and the edge protection region 41 is formed at the edge of the silicon wafer 20 through the light-shielding member 31, The negative photoresist 22 of the edge protection region 41 is not exposed to light, and an edge buffer 42 is formed between the integrated circuit pattern region 40 and the edge protection region 41 through the optical path between the mask plate 30 and the light blocking member 31, and the edge The negative photoresist 22 of the buffer 42 is illuminated.

After the exposure, the silicon wafer 20 is subjected to development processing, and the negative photoresist 22 of the edge protection region 41 is removed by chemical reaction of the developer with the negative photoresist 22.

As shown in FIG. 6, as a preferred embodiment, the sum W of the widths of the edge protection zone 41 and the edge buffer 42 is less than or equal to 5 mm.

With this implementation method, the effective range of the integrated circuit pattern region 40 of the silicon wafer 20 can be ensured. The silicon wafer 20 is reasonably and fully applied.

As shown in FIG. 6, as a preferred embodiment, the width D of the edge protection zone 41 is greater than or equal to 3 mm.

With this implementation method, the range of the edge protection region 41 can be ensured, so that the metal seed layer 21 at the bottom of the edge of the silicon wafer 20 is sufficiently exposed to meet the needs of the subsequent metal plating process.

As shown in FIG. 6, as a preferred embodiment, the edge buffer 42 has a width S of 1 to 2 mm.

With this implementation method, the edge chip pattern of the silicon chip 20 is effectively protected by the edge buffer 42 while reducing the area occupied by the silicon wafer 20 and improving the utilization of the silicon wafer 20.

Preferably, the edge buffer 42 has a ring shape and surrounds the periphery of the integrated circuit pattern area 40. Preferably, as shown in FIGS. 7 and 8, the edge buffer 42 has a circular or positive polygonal ring shape.

With this implementation, the edge buffer 42 is wrapped around the periphery of the integrated circuit pattern area 40 to reduce the footprint of the edge buffer 42 while ensuring effective protection of the edge chip pattern of the silicon chip 20.

Preferably, the resolution of the negative photoresist 22 is greater than or equal to 2 mm.

Correspondingly, referring to FIG. 5, the present invention further provides a method for protecting a silicon wafer edge, including:

Step 1. Before exposure, the metal seed layer 21 and the negative photoresist 22 are sequentially coated on the surface of the silicon wafer 20;

Step 2. When exposing, an integrated circuit pattern region 40 is formed on the silicon wafer 20 through the reticle 30, and an edge protection region 41 is formed on the edge of the silicon wafer 20 through the light shielding member 31, between the light shielding member 31 and the reticle 30. An optical path is provided; an edge buffer 42 is formed between the integrated circuit pattern area 40 and the edge protection area 41 through the optical path;

Step 3. After the exposure, the silicon wafer 20 is subjected to development processing to remove the negative photoresist 22 of the edge protection region 41.

Referring to FIGS. 5 and 9, in the method for protecting the edge of the silicon wafer 20 of the present invention and the lithographic exposure apparatus, an integrated circuit pattern region 40 is formed on the silicon wafer 20 through the reticle 30, and the silicon wafer is passed through the light shielding member 31. The edge 20 forms an edge protection region 41, and an edge buffer 42 is formed between the integrated circuit pattern region 40 and the edge protection region 41 through an optical path between the reticle 30 and the light shielding member 31, and edge protection is reduced by the edge buffer 42 During the development process of the region 41 due to the chemical reaction and physical impact of the developer on the edge chip pattern of the silicon wafer 20, the edge chip pattern of the silicon wafer 20 can be protected in the subsequent processing process, and the edge of the silicon wafer 20 is improved. The yield of the chip, through the development of the edge protection region 41, exposes the metal seed layer 21 at the bottom of the edge of the silicon wafer 20 to meet the needs of metal plating, and the entire edge optimization structure is completed by one exposure, thereby improving the adaptability of the process, The process is more optimized.

Claims

A method for protecting a silicon wafer edge, comprising:

Step 1. Prior to exposure, a metal seed layer and a negative photoresist are sequentially coated on the surface of the silicon wafer;

Step 2. When exposing, forming an integrated circuit pattern region on the silicon wafer through the reticle, forming an edge protection region on the edge of the silicon wafer through the light shielding member, and providing an optical path between the light shielding member and the reticle; An optical path channel forms an edge buffer between the integrated circuit pattern area and the edge protection area;

Step 3. After exposure, the silicon wafer is developed to remove the negative photoresist of the edge protection region.
The protection method according to claim 1, wherein the optical path is surrounded by a periphery of the reticle.
The protection method according to claim 1, wherein the shape of the edge buffer is a circular ring or a regular polygonal ring shape.
The protection method according to claim 1, wherein the negative photoresist has a resolution of 2 mm or more.
The protection method according to claim 1, wherein the metal seed layer is a copper seed layer or an alloy seed layer.
The protection method according to claim 1, wherein the reticle and the light shielding member are at the same horizontal position.
A lithographic exposure apparatus comprising a reticle aligned with an exposure position on a silicon wafer, and an integrated circuit pattern region formed upon exposure; the light shielding member is aligned with an edge position on the silicon wafer, An edge protection region is formed during exposure; and an optical path channel is disposed between the reticle and the light shielding member to form an edge buffer during exposure.
A lithographic exposure apparatus according to claim 7, wherein said optical path is surrounded by a periphery of the reticle.
The lithographic exposure apparatus according to claim 7, wherein said edge protection area and The sum of the widths of the edge buffers is less than or equal to 5 mm.
The lithographic exposure apparatus according to claim 7, wherein the edge protection region has a width of 3 mm or more.
The lithographic exposure apparatus according to claim 7, wherein the edge buffer has a width of 1 to 2 mm.