JP2006173260A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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JP2006173260A
JP2006173260A JP2004361649A JP2004361649A JP2006173260A JP 2006173260 A JP2006173260 A JP 2006173260A JP 2004361649 A JP2004361649 A JP 2004361649A JP 2004361649 A JP2004361649 A JP 2004361649A JP 2006173260 A JP2006173260 A JP 2006173260A
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light irradiation
illuminance
semiconductor substrate
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semiconductor device
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JP4524457B2 (en
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Kenji Saito
健二 斎藤
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Renesas Technology Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device conducting a treatment destaticizing a semiconductor substrate before a wet etching treatment and the device. <P>SOLUTION: An element isolation insulating film 2 is formed on the semiconductor substrate 1 in Fig.(a), and a gate insulating film 6 is deposited. A photo-resist 7 is formed in Fig.(b), and the semiconductor substrate 1 is irradiated with a light 9 and a destaticizing is conducted in Fig.(c) for removing charges 8 generated by a pure-water washing or the like. Lastly, the gate insulating film 6 is removed selectively while using the photo-resist 7 as a mask in Fig.(d). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、ウェットエッチング処理によって絶縁膜を除去する半導体装置の製造方法及び装置に関し、特に極薄膜の絶縁膜を除去する際に除電を行なう半導体装置の製造方法及び装置に関する。   The present invention relates to a method and an apparatus for manufacturing a semiconductor device in which an insulating film is removed by wet etching, and more particularly to a method and an apparatus for manufacturing a semiconductor device that perform static elimination when removing an extremely thin insulating film.

従来の酸化膜及び窒化膜からなる絶縁膜を除去する工程において、イオン注入後の洗浄工程や環境要因で電荷が発生する。その後、希フッ酸等の薬液で絶縁膜を除去する際に、近年の微細化に伴い絶縁膜が10nm程度まで薄膜化されているため、薬液による除電作用が十分になされる前に絶縁膜が薄くなり、一時的に非常に高い電界強度となる。その結果、絶縁膜の絶縁破壊が発生し、電荷が半導体基板に抜ける際に、基板欠陥を引き起こすという問題が生じていた。   In a conventional process of removing an insulating film made of an oxide film and a nitride film, charges are generated due to a cleaning process after ion implantation and environmental factors. Thereafter, when the insulating film is removed with a chemical such as dilute hydrofluoric acid, the insulating film is thinned to about 10 nm with the recent miniaturization. It becomes thin and temporarily has a very high electric field strength. As a result, a dielectric breakdown of the insulating film occurs, causing a problem of causing a substrate defect when charges are released to the semiconductor substrate.

具体例を以下に説明する。フォトレジストをマスクとして選択的に絶縁膜を除去する処理は、Dualゲート絶縁膜の形成に使用されることが多い。半導体基板の上に公知技術で素子分離絶縁膜を形成した後、ゲート絶縁膜を半導体基板表面の全面に堆積する。その後、公知の写真製版技術でフォトレジストを形成する。この時の現像処理後の洗浄は比抵抗の高い純水で行なわれるため、絶縁物同士の摩擦により電荷が発生する。そして、フォトレジストをマスクとして選択的にゲート絶縁膜を希フッ酸等の薬品で除去する際に、基板欠陥を引き起こす。   A specific example will be described below. The process of selectively removing the insulating film using a photoresist as a mask is often used for forming a dual gate insulating film. After forming an element isolation insulating film on the semiconductor substrate by a known technique, a gate insulating film is deposited on the entire surface of the semiconductor substrate. Thereafter, a photoresist is formed by a known photolithography technique. Since the cleaning after the development processing at this time is performed with pure water having a high specific resistance, electric charges are generated by friction between the insulators. Then, a substrate defect is caused when the gate insulating film is selectively removed with a chemical such as dilute hydrofluoric acid using the photoresist as a mask.

また、蓄積された静電気により金属配線が腐食するのを防止することを目的として、Al−Si金属薄膜の所定領域を残すためにレジストパターンを形成し、その後レジストパターンを除去して水洗する工程と、ウェットエッチング工程及び水洗工程の前に絶縁基板の表面に蓄積された静電気をイオナイザーにより除去する工程を有する薄膜トランジスタの製造方法が開示されている(例えば、特許文献1参照)。   And a step of forming a resist pattern to leave a predetermined region of the Al-Si metal thin film, and then removing the resist pattern and washing with water for the purpose of preventing corrosion of the metal wiring due to accumulated static electricity. A method of manufacturing a thin film transistor is disclosed that includes a step of removing static electricity accumulated on the surface of an insulating substrate with an ionizer before a wet etching step and a water washing step (see, for example, Patent Document 1).

更に、ドライエッチング等の処理中に、荷電粒子に起因した電荷のチャージアップが発生した場合に、紫外線照射処理を行ってチャージアップの中和処理を行なう半導体装置の製造方法が開示されている(例えば、特許文献2参照)。   Further, a method for manufacturing a semiconductor device is disclosed in which, when a charge charge caused by charged particles occurs during a process such as dry etching, an ultraviolet irradiation process is performed to perform a charge-up neutralization process ( For example, see Patent Document 2).

特開平7−221311号公報Japanese Patent Laid-Open No. 7-221311 特開平4−152519号公報JP-A-4-152519

従来の半導体装置の製造方法は以上のように行なわれていたので、フォトレジスト形成後の純水による洗浄で発生した電荷が、ウェットエッチング処理の際に絶縁膜の絶縁破壊が生じた場合に基板を抜けて、基板欠陥を引き起こすという課題があった。   Since the conventional method for manufacturing a semiconductor device has been performed as described above, the substrate generated when the dielectric breakdown of the insulating film occurs during the wet etching process due to the charge generated by cleaning with pure water after forming the photoresist. There has been a problem of causing a substrate defect.

特許文献1の薄膜トランジスタの製造方法は、金属薄膜をエッチングして電極配線を形成する工程に関するものであり、近年この工程は、ウェットエッチング処理からドライエッチング処理に移行している。また、それに対して本発明の課題を有する絶縁膜を除去する工程においては、均一性、選択比、基板へのダメージ等の観点からドライエッチングは困難であり、現在もウェットエッチング処理に変わるものが無い状態である。従って、ウェットエッチング処理の前に除電を行なう方法が求められていた。   The manufacturing method of the thin film transistor of Patent Document 1 relates to a process of forming an electrode wiring by etching a metal thin film, and in recent years, this process has shifted from a wet etching process to a dry etching process. On the other hand, in the process of removing the insulating film having the subject of the present invention, dry etching is difficult from the viewpoint of uniformity, selectivity, damage to the substrate, etc. There is no state. Therefore, there has been a demand for a method of eliminating static electricity before the wet etching process.

特許文献2の半導体装置の製造方法も、ウェットエッチング処理の前に除電を行なう方法ではなく、ドライエッチング等の処理中に荷電粒子に起因したチャージアップが発生した場合に、事後処理として紫外線照射による除電を行なっている。そして、その効果は酸化膜の劣化による真性寿命の低下を抑える程度に留まっている。また、同工程におけるチャージアップ自体についても、最近の処理条件等を含む様々な改善によりその発生を抑えることが可能となっている。   The manufacturing method of the semiconductor device of Patent Document 2 is not a method of removing static electricity before the wet etching process, but when a charge-up caused by charged particles occurs during a process such as dry etching, the post-process is performed by ultraviolet irradiation. Static elimination is performed. The effect is limited to a degree that suppresses a decrease in intrinsic lifetime due to deterioration of the oxide film. In addition, the occurrence of the charge-up itself in the same process can be suppressed by various improvements including recent processing conditions.

この発明は上記のようなを課題を解決するためになされたもので、ウェットエッチング処理を行なう前に半導体基板を除電する処理を行なう半導体装置の製造方法及び装置を提供することを目的とする。   SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method and apparatus for manufacturing a semiconductor device that performs a process of discharging a semiconductor substrate before performing a wet etching process.

この発明の半導体装置の製造方法は、半導体基板上の絶縁膜のウェットエッチング処理を行なう前に、半導体基板を除電する処理を行なう。   In the method of manufacturing a semiconductor device according to the present invention, the semiconductor substrate is neutralized before the wet etching process is performed on the insulating film on the semiconductor substrate.

この発明によれば、希フッ酸等の薬液で絶縁膜を除去するウェットエッチング処理前に、半導体基板表面を除電する処理を追加するようにしたので、ウェットエッチング処理での電界強度上昇を防ぐ事が出来、半導体基板への欠陥を無くし、不良率の低減と信頼性に優れた半導体装置を得られる効果がある。   According to the present invention, since the process of removing the charge on the surface of the semiconductor substrate is added before the wet etching process for removing the insulating film with a chemical solution such as dilute hydrofluoric acid, an increase in electric field strength in the wet etching process can be prevented. Thus, it is possible to eliminate defects in the semiconductor substrate and to obtain a semiconductor device having a reduced defect rate and excellent reliability.

実施の形態1.
以下、この発明の実施の形態1について説明する。図1は、実施の形態1に係る半導体装置の製造方法の処理フローを示す図である。図1(a)で、半導体基板1の上に公知技術で素子分離絶縁膜2を形成した後、ゲート絶縁膜6を半導体基板1表面の全面に堆積する。続いて、図1(b)に示すように、公知の写真製版技術でフォトレジスト7を形成する。この時に、現像処理後の洗浄は比抵抗の高い純水で行なわれるため、絶縁物同士の摩擦により電荷8が発生する。
Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below. FIG. 1 is a diagram showing a processing flow of the method for manufacturing a semiconductor device according to the first embodiment. In FIG. 1A, after forming an element isolation insulating film 2 on a semiconductor substrate 1 by a known technique, a gate insulating film 6 is deposited on the entire surface of the semiconductor substrate 1. Subsequently, as shown in FIG. 1B, a photoresist 7 is formed by a known photolithography technique. At this time, since cleaning after development processing is performed with pure water having a high specific resistance, electric charges 8 are generated due to friction between insulators.

その後、図1(c)に示すように、蛍光灯等で半導体基板1表面に光9を照射し、同表面を除電する。図2は、図1中の光9の照度と半導体基板1の不良率の相関グラフである。図2から、不良率を低減するためには、光9の照度は少なくとも200ルクス以上必要であることが分かる。最後に、図1(d)に示すように、フォトレジスト7をマスクとして選択的にゲート絶縁膜6を希フッ酸等の薬液で除去する。   Thereafter, as shown in FIG. 1C, the surface of the semiconductor substrate 1 is irradiated with light 9 with a fluorescent lamp or the like, and the surface is neutralized. FIG. 2 is a correlation graph between the illuminance of the light 9 in FIG. 1 and the defect rate of the semiconductor substrate 1. 2 that the illuminance of the light 9 needs to be at least 200 lux in order to reduce the defect rate. Finally, as shown in FIG. 1D, the gate insulating film 6 is selectively removed with a chemical such as dilute hydrofluoric acid using the photoresist 7 as a mask.

以上のように、実施の形態1によれば、希フッ酸等の薬液で絶縁膜を除去するウェットエッチング処理の前に、半導体基板表面を除電する処理を追加するようにしたので、エッチング途中の電界強度上昇を防ぐ事が出来、半導体基板1への欠陥を無くし、不良率及び信頼性に優れた半導体装置を得られる効果がある。   As described above, according to the first embodiment, the process of removing the charge on the semiconductor substrate surface is added before the wet etching process of removing the insulating film with a chemical solution such as dilute hydrofluoric acid. It is possible to prevent an increase in electric field strength, eliminate defects in the semiconductor substrate 1, and obtain a semiconductor device having an excellent defect rate and reliability.

実施の形態2.
以下、この発明の実施の形態2を説明する。図3は、実施の形態2に係る光照射処理機構を備えた現像装置の構成図である。実施の形態1の除電(図1(c))を行なう機構を現像装置やウェットエッチング装置に付加すれば、工程数を増やすことなく同様の効果を得ることが出来る。図3において、現像装置は、半導体基板1を保持する真空チャック10と現像カップ11、現像ノズルアーム12、現像ノズル13、リンスノズル14、光照射ユニット15、照度計16、照度コントロールユニット17を備えている。なお、光照射ユニット15と照度計16、照度コントロールユニット17以外は従来の現像装置の構成と同等である。
Embodiment 2. FIG.
The second embodiment of the present invention will be described below. FIG. 3 is a configuration diagram of a developing device including the light irradiation processing mechanism according to the second embodiment. If a mechanism for performing static elimination (FIG. 1C) according to the first embodiment is added to a developing device or a wet etching device, the same effect can be obtained without increasing the number of steps. In FIG. 3, the developing device includes a vacuum chuck 10 that holds the semiconductor substrate 1, a developing cup 11, a developing nozzle arm 12, a developing nozzle 13, a rinse nozzle 14, a light irradiation unit 15, an illuminance meter 16, and an illuminance control unit 17. ing. Except for the light irradiation unit 15, the illuminance meter 16, and the illuminance control unit 17, the configuration of the conventional developing device is the same.

次に、動作について説明する。真空チャック10で固定した半導体基板1を回転させながら、現像ノズル13より現像液を吐出する。そして、半導体基板1表面に均一に現像液を塗布してフォトレジストを現像する。その後、リンスノズル14より半導体基板1表面にリンス液と純水を順次吐出し、現像処理を完了する。その後、光照射ユニット15より光を照射し、半導体基板1表面の照度を照度計16で検出し、照度コントロールユニット17で照度を200ルクス以上に保持することで除電を行なう。   Next, the operation will be described. The developer is discharged from the developing nozzle 13 while rotating the semiconductor substrate 1 fixed by the vacuum chuck 10. And a developing solution is uniformly apply | coated to the semiconductor substrate 1 surface, and a photoresist is developed. Thereafter, a rinse liquid and pure water are sequentially discharged from the rinse nozzle 14 onto the surface of the semiconductor substrate 1 to complete the development process. Thereafter, light is emitted from the light irradiation unit 15, the illuminance on the surface of the semiconductor substrate 1 is detected by the illuminance meter 16, and the illuminance control unit 17 holds the illuminance at 200 lux or more to perform static elimination.

図4は、実施の形態2に係る光照射処理室を別途設けた構成図である。光照射処理室21には図3の光照射ユニット15、照射計16、照度コントロールユニット17を備えている。図3では現像処理室内で光照射処理を行なっているが、図4に示すように、現像処理完了後に、半導体基板1を搬送カセット20に収納する前に、光照射処理室21で光照射処理を行なうこともできる。   FIG. 4 is a configuration diagram in which a light irradiation processing chamber according to Embodiment 2 is separately provided. The light irradiation processing chamber 21 includes the light irradiation unit 15, the irradiometer 16, and the illuminance control unit 17 shown in FIG. 3. Although the light irradiation process is performed in the development processing chamber in FIG. 3, the light irradiation process is performed in the light irradiation processing chamber 21 after the development processing is completed and before the semiconductor substrate 1 is stored in the transport cassette 20 as shown in FIG. 4. Can also be performed.

以上のように、実施の形態2によれば、光照射処理機構(光照射ユニット15、照度計16、照度コントロールユニット17)を現像装置に組み込み、或いは光照射処理室21を設けることで、工程数を増やすことなく実施の形態1と同様の効果が得られる。   As described above, according to the second embodiment, the light irradiation processing mechanism (light irradiation unit 15, illuminance meter 16, illuminance control unit 17) is incorporated in the developing device, or the light irradiation processing chamber 21 is provided. The same effect as in the first embodiment can be obtained without increasing the number.

実施の形態3.
以下、この発明の実施の形態3を説明する。図5は、実施の形態3に係る光照射処理機構を設けたウェットエッチング装置の構成図である。図5において、ウェットエッチング装置は、半導体基板1を収納する搬送カセット20、薬液22が満たされた薬液層23、排水口24、補助排水口25、光照射ユニット15、照度計16、照度コントロールユニット17を備えている。なお、光照射ユニット15、照度計16、照度コントロールユニット17以外は従来構成のウェットエッチング装置である。
Embodiment 3 FIG.
The third embodiment of the present invention will be described below. FIG. 5 is a configuration diagram of a wet etching apparatus provided with a light irradiation processing mechanism according to the third embodiment. In FIG. 5, the wet etching apparatus includes a transport cassette 20 for storing the semiconductor substrate 1, a chemical solution layer 23 filled with a chemical solution 22, a drain port 24, an auxiliary drain port 25, a light irradiation unit 15, an illuminance meter 16, and an illuminance control unit. 17 is provided. In addition, except the light irradiation unit 15, the illuminance meter 16, and the illuminance control unit 17, it is a wet etching apparatus of a conventional configuration.

次に、動作について説明する。先ず、半導体基板1に対して、光照射ユニット15より光を照射する。半導体基板1表面の照度を照度計16で検出し、照度コントロールユニット17で照度を200ルクス以上に保持することで半導体基板1の除電を行なう。次に、半導体基板1を収納した搬送カセット20を薬液層23に入れ、薬液22に十分に浸漬する。所定の時間に達したら搬送カセット20を薬液層23から取り出し、エッチング処理を完了する。この時に、薬液22が溢れる場合には補助排水口25から排水する。   Next, the operation will be described. First, the semiconductor substrate 1 is irradiated with light from the light irradiation unit 15. The illuminance on the surface of the semiconductor substrate 1 is detected by the illuminance meter 16, and the illuminance control unit 17 holds the illuminance at 200 lux or more, so that the semiconductor substrate 1 is neutralized. Next, the transport cassette 20 containing the semiconductor substrate 1 is placed in the chemical solution layer 23 and sufficiently immersed in the chemical solution 22. When the predetermined time is reached, the transport cassette 20 is taken out from the chemical solution layer 23 to complete the etching process. At this time, if the chemical liquid 22 overflows, it is drained from the auxiliary drain port 25.

図6は、実施の形態3に係る光照射処理室を別途設けた構成図である。図6において、処理待機室26に配置された半導体基板が搬送カセット20に収納されて、光照射処理室21、薬液処理室27、純水処理室28、乾燥処理室29の順に搬送ロボット30で運ばれる。光照射処理室21には図5の光照射ユニット15、照射計16、照度コントロールユニット17を備えている。図5ではウェットエッチング装置で光照射処理を行なっているが、図6に示すように、薬液処理室27へ半導体基板が搬入される前に、光照射処理室21で光照射処理を行なうこともできる。   FIG. 6 is a configuration diagram in which a light irradiation processing chamber according to Embodiment 3 is separately provided. In FIG. 6, the semiconductor substrate disposed in the processing standby chamber 26 is stored in the transport cassette 20, and the light irradiation processing chamber 21, the chemical solution processing chamber 27, the pure water processing chamber 28, and the drying processing chamber 29 are sequentially performed by the transport robot 30. Carried. The light irradiation processing chamber 21 is provided with the light irradiation unit 15, the irradiator 16 and the illuminance control unit 17 shown in FIG. In FIG. 5, the light irradiation process is performed by the wet etching apparatus. However, as shown in FIG. 6, the light irradiation process may be performed in the light irradiation process chamber 21 before the semiconductor substrate is carried into the chemical processing chamber 27. it can.

以上のように、実施の形態3によれば、光照射処理機構(光照射ユニット15、照度計16、照度コントロールユニット17)をウェットエッチング装置に組み込み、或いは薬液処理室27の前に光照射処理室21を設けることで、工程数を増やすことなく実施の形態1と同様の効果が得られる。   As described above, according to the third embodiment, the light irradiation processing mechanism (light irradiation unit 15, illuminance meter 16, illuminance control unit 17) is incorporated in the wet etching apparatus, or light irradiation processing is performed before the chemical solution processing chamber 27. By providing the chamber 21, the same effect as in the first embodiment can be obtained without increasing the number of steps.

この発明の実施の形態1に係る半導体装置の製造方法の処理フローを示す図である。It is a figure which shows the processing flow of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. 図1中の光の照度と半導体基板の不良率の相関グラフである。It is a correlation graph of the illumination intensity of the light in FIG. 1, and the defect rate of a semiconductor substrate. この発明の実施の形態2に係る光照射処理機構を備えた現像装置の構成図である。It is a block diagram of the developing device provided with the light irradiation processing mechanism which concerns on Embodiment 2 of this invention. この発明の実施の形態2に係る光照射処理室を別途設けた構成図である。It is the block diagram which provided separately the light irradiation process chamber which concerns on Embodiment 2 of this invention. この発明の実施の形態3に係る光照射処理機構を設けたウェットエッチング装置の構成図である。It is a block diagram of the wet etching apparatus provided with the light irradiation process mechanism which concerns on Embodiment 3 of this invention. この発明の実施の形態3に係る光照射処理室を別途設けた構成図である。It is the block diagram which provided separately the light irradiation process chamber which concerns on Embodiment 3 of this invention.

符号の説明Explanation of symbols

1 半導体基板、2 素子分離絶縁膜、6 ゲート絶縁膜、7 フォトレジスト、8 電荷、9 光、10 真空チャック、11 現像カップ、12 現像ノズルアーム、13 現像ノズル、14 リンスノズル、15 光照射ユニット、16 照度計、17 照度コントロールユニット、18 現像処理室、19 搬送アーム、20 搬送カセット、21 光照射処理室、22 薬液、23 薬液層、24 排水口、25 補助排水口、26 処理待機室、27 薬液処理室、28 純水処理室、29 乾燥処理室、30 搬送ロボット。   DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Element isolation insulating film, 6 Gate insulating film, 7 Photoresist, 8 Electric charge, 9 Light, 10 Vacuum chuck, 11 Developing cup, 12 Developing nozzle arm, 13 Developing nozzle, 14 Rinse nozzle, 15 Light irradiation unit , 16 illuminance meter, 17 illuminance control unit, 18 development processing chamber, 19 transport arm, 20 transport cassette, 21 light irradiation processing chamber, 22 chemical solution, 23 chemical solution layer, 24 drainage port, 25 auxiliary drainage port, 26 processing standby chamber, 27 Chemical treatment chamber, 28 Pure water treatment chamber, 29 Drying treatment chamber, 30 Transfer robot.

Claims (8)

半導体基板上の絶縁膜のウェットエッチング処理を行なう前に、前記半導体基板を除電する処理を行うことを特徴とする半導体装置の製造方法。   A method for manufacturing a semiconductor device, comprising: performing a process of neutralizing the semiconductor substrate before performing a wet etching process on an insulating film on the semiconductor substrate. 前記ウェットエッチング処理において、フォトレジストをマスクとして絶縁膜を選択的にエッチングすることを特徴とする請求項1記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the wet etching process, the insulating film is selectively etched using a photoresist as a mask. 前記半導体基板を除電する処理は、光照射処理であることを特徴とする請求項1または請求項2記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the process of neutralizing the semiconductor substrate is a light irradiation process. 前記光照射処理で照射される光の照度が200ルクス以上であることを特徴とする請求項3記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 3, wherein an illuminance of light irradiated in the light irradiation process is 200 lux or more. 半導体基板に対して光照射して半導体基板を除電する光照射ユニットと、
前記光照射の照度を検出する照度計と、
前記照度計が検出した照度から前記光照射ユニットを制御する照度コントロールユニットとを備えることを特徴とする半導体装置の製造装置。
A light irradiation unit for irradiating the semiconductor substrate with light to neutralize the semiconductor substrate;
An illuminometer for detecting the illuminance of the light irradiation;
An illuminance control unit that controls the light irradiation unit from the illuminance detected by the illuminance meter.
前記光照射ユニットと前記照度計と前記照度コントロールユニットが、現像装置またはウェットエッチング装置に組み込まれていることを特徴とする請求項5記載の半導体装置の製造装置。   6. The apparatus for manufacturing a semiconductor device according to claim 5, wherein the light irradiation unit, the illuminance meter, and the illuminance control unit are incorporated in a developing device or a wet etching device. 前記光照射ユニットと前記照度計と前記照度コントロールユニットが、独立した光照射処理室に配置されていることを特徴とする請求項5記載の半導体装置の製造装置。   6. The semiconductor device manufacturing apparatus according to claim 5, wherein the light irradiation unit, the illuminance meter, and the illuminance control unit are arranged in an independent light irradiation processing chamber. 前記照度コントロールユニットは、前記照度計が検出した前記光照射の照度に基づいて、前記光照射の照度を200ルクス以上に保持することを特徴とする請求項5から請求項7のうちのいずれか1項記載の半導体装置の製造装置。   The illuminance control unit holds the illuminance of the light irradiation at 200 lux or more based on the illuminance of the light irradiation detected by the illuminance meter. An apparatus for manufacturing a semiconductor device according to claim 1.
JP2004361649A 2004-12-14 2004-12-14 Method and apparatus for manufacturing semiconductor device Expired - Fee Related JP4524457B2 (en)

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