CN108231614A - A kind of method of crystal column surface residual charge amount after detection ion implanting - Google Patents
A kind of method of crystal column surface residual charge amount after detection ion implanting Download PDFInfo
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- CN108231614A CN108231614A CN201611154391.8A CN201611154391A CN108231614A CN 108231614 A CN108231614 A CN 108231614A CN 201611154391 A CN201611154391 A CN 201611154391A CN 108231614 A CN108231614 A CN 108231614A
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- crystal column
- column surface
- ion implanting
- dielectric layer
- wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Abstract
The method that the present invention provides crystal column surface residual charge amount after a kind of detection ion implanting, the method includes：Wafer is provided；Dielectric layer is formed in the crystal column surface；Ion implanting is performed to the wafer for being formed with dielectric layer；The dielectric layer is etched, and measures etch rate；Reflect the quantity of electric charge of crystal column surface according to the etch rate.Compared with the prior art, after detection ion implanting proposed by the present invention crystal column surface residual charge amount method, can more effectively monitor the quantity of electric charge of crystal column surface, and timeliness is strong, rate the defects of so as to reduce product.
Description
Technical field
The present invention relates to semiconductor fabrication process, are remained in particular to crystal column surface after a kind of detection ion implanting
The method of the quantity of electric charge.
Background technology
With the fast development of microelectronics industry, ion implanting has become a kind of heavy in microelectronic component preparation process
The doping techniques and an important means of control metal oxide semiconductor field effect transistor threshold voltage wanted.Ion implanting
Principle be that atom or molecule are formed into ion, i.e. plasma after ionization；Plasma carries a certain amount of electricity
Lotus；Ion can be accelerated by electric field, and change its direction of motion using magnetic field, so as to control ion with certain energy
Amount enters inside wafer, to achieve the purpose that doping.
However, since the ion using ion implantation technology incorporation is with charge, and these charge meetings after chip is injected
It accumulates on the surface of chip, is largely accumulated in the charge of wafer surface, it may be by having made capacitance on a surface of a wafer
Structure forms electric current, so as to cause the injury of the grid oxic horizon between the grid of chip, grid and semiconductor.More seriously
It is, due to passing through for instantaneous high current, to be easy to cause the permanent damages of gate structure.Therefore, it in ion implantation process, prevents
It is that semiconductor preparing process is urgently to be resolved hurrily due to being damaged caused by chip in wafer surface stored charge in ion implantation process
The technical issues of.Although however, added on ion injection machine table electric charge neutralization device PFG (plasma flood gun) etc. with
The charge of ion institute band is neutralized, but is difficult to detect, and to the electricity of final wafer surface when neutralization device is abnormal
Lotus accumulates situation still without effectively monitoring method.
Therefore, be to solve above-mentioned technical problem of the prior art, it is necessary to propose a kind of new detection ion implanting it
The method of crystal column surface residual charge amount afterwards.
Invention content
In view of the deficiencies of the prior art, crystal column surface residual charge amount after a kind of detection ion implanting of present invention offer
Method, including：
Wafer is provided；
Dielectric layer is formed in the crystal column surface；
Ion implanting is performed to the wafer for being formed with dielectric layer；
The dielectric layer is etched, and measures etch rate；
Reflect the quantity of electric charge of crystal column surface according to the etch rate.
Illustratively, the dielectric layer is silicon oxide layer.
Illustratively, the silicon oxide layer is the silicon oxide layer of nitrating.
Illustratively, the thickness of the dielectric layer is 800-1200 angstroms.
Illustratively, the ion of the injection is arsenic.
Illustratively, the dosage of the ion implanting is 1.0 × 1015/cm2More than.
Illustratively, the etching is wet etching.
Illustratively, etching liquid used in the wet etching is diluted hydrofluoric acid.
Compared with the prior art, it is proposed by the present invention detection ion implanting after crystal column surface residual charge amount method,
The quantity of electric charge of crystal column surface can be more effectively monitored, and timeliness is strong, rate the defects of so as to reduce product.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 is flow chart the step of implementation successively according to the method for the present invention.
Fig. 2 a-2d obtain the section signal of semiconductor devices to implement each step successively according to the manufacturing method of the present invention
Figure.
Fig. 3 is relation curve of the etch rate with neutralizing device neutralization ratio in one embodiment of the invention.
Specific embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.Disclosure will be made thoroughly and complete, and will fully convey the scope of the invention on the contrary, providing these embodiments
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or during layer, then there is no elements or layer between two parties.It should be understood that although it can make
Various elements, component, area, floor and/or part described with term first, third, second etc., these elements, component, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another
One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by third element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and be used so as to describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention, which further includes, to be made
With the different orientation with the device in operation.For example, if the device overturning in attached drawing, then, is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented to other elements or features " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
Ion implanting is a kind of important doping techniques in microelectronic component preparation process.However, due to utilizing ion
The ion of injection technology incorporation is with charge, and these charges can be accumulated on the surface of chip after chip is injected, a large amount of to accumulate
In the charge of wafer surface, electric current may be formed, by having made capacitance structure on a surface of a wafer so as to cause chip
Grid, grid oxic horizon between grid and semiconductor injury.It is more seriously, due to passing through for instantaneous high current, to hold
Easily cause the permanent damages of gate structure.Install electric charge neutralization device PFG additional usually on ion injection machine table in the prior art
(plasma flood gun) etc. indirectly reacts charging neutrality to neutralize the charge of ion institute band by the parameter of PFG
Situation.However, the measuring method of this charge is not direct, and when PFG is abnormal, it is difficult to monitor, therefore, it is necessary to one kind
To the effective monitoring method of charge accumulation situation of final wafer surface.
In view of the deficiencies of the prior art, the present invention provides crystal column surface residual charge after a kind of new detection ion implanting
The method of amount, including：
Wafer is provided；
Dielectric layer is formed in the crystal column surface；
Ion implanting is performed to the wafer for being formed with dielectric layer；
The dielectric layer is etched, and measures etch rate；
Reflect the quantity of electric charge of crystal column surface according to the etch rate.
The dielectric layer is silicon oxide layer.The silicon oxide layer is the silicon oxide layer of nitrating.
The ion of the injection is arsenic.The dosage of the ion implanting is 1.0 × 1015/cm2More than.
The etching is wet etching.Etching liquid used in the wet etching is diluted hydrofluoric acid.
Compared with the prior art, it is proposed by the present invention detection ion implanting after crystal column surface residual charge amount method,
The defects of quantity of electric charge of crystal column surface can more effectively being monitored, and timeliness is strong, reducing product rate.
In order to thoroughly understand the present invention, detailed structure and/or step will be proposed in following description, to illustrate this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this hair
It is bright to have other embodiment.[exemplary embodiment one]
Below with reference to Fig. 1-Fig. 3 to crystal column surface residual charge after the detection ion implanting of an embodiment of the present invention
The method of amount is described in detail.
First, step 101 is performed, provides wafer 201, as shown in Figure 2 a.The wafer 201 following can be previously mentioned
At least one of material：Silicon (SSOI) is laminated on insulator, SiGe is laminated on insulator for silicon, silicon-on-insulator (SOI)
(S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc., wafer 201 described in the present embodiment
For monocrystalline silicon.
Then, step 102 is performed, forms dielectric layer 202 on 201 surface of wafer, as shown in Figure 2 b.The dielectric layer
202 have charge-trapping ability, such as silicon oxide layer.The forming method of the dielectric layer 202 can be the method for deposition, such as
The methods of chemical vapor deposition, atomic layer deposition, can also be the surface formation of wafer described in thermal oxide.In the present embodiment,
One layer of silicon oxide layer is grown as dielectric layer in crystal column surface using thermal oxidation method.The thickness of the oxide layer is at 800-1200 angstroms
Between, preferably, its thickness is 1000 angstroms.Specifically, the wafer needed to be oxidized is placed in boiler tube, and passes through heater to institute
Boiler tube is stated to carry out being heated to 800-1200 DEG C；Oxygen and hydrogen are passed through into reactor and is mixed and burned；By what is generated after burning
The air inlet of vapor and remaining oxygen from the boiler tube is passed through in boiler tube；Nitrogen is passed through with will be in boiler tube from the air inlet
Gas discharged from the exhaust outlet of boiler tube.
Preferably, nitrogen can be mixed while oxide layer is grown, to improve the K values of oxide layer, (dielectric is normal
Number), strengthen the capturing ability to charge.Illustratively, the temperature range of the nitrating technique is 800-1000 degrees Celsius, described
Nitrating technology utilization N2O gases carry out.
Then, step 103 is performed, ion implanting is performed to the wafer 201 for being formed with dielectric layer 202, such as Fig. 2 c institutes
Show.Preferably, the ion of injection is arsenic ion, ion dose that when ion implanting uses is 1.0 × 1015/cm2More than, such as 5
×1015/cm2.Ion implantation device well known to those skilled in the art can be used to the wafer for being formed with dielectric layer 202
201 perform ion implanting；The voltage used during ion implanting is 5~200KeV, such as 20KeV.Described in the ion penetration of injection
Dielectric layer enters inside wafer, simultaneously because the dielectric constant of the oxide layer of crystal column surface nitrating is higher, what ion implanting generated
Charge will be largely concentrated in the oxide layer of the nitrating.Electric charge neutralization device is added on the board of ion implanting, such as
PFG (plasma flood gun, also referred to as plasma flood gun or plasma flood rifle), function are that generation is negatively charged
The electronics of lotus neutralizes the excessive cation of crystal column surface, prevents the wafer caused by being accumulated due to positive charge from damaging with this.When
Enough electronics can not be generated to neutralize the excessive cation accumulated of crystal column surface, when PFG is abnormal so as to meeting
Charge breakdown is caused to influence the performance of device and influences final testing result.
Then, step 104 is performed, etches the dielectric layer 202, and measure etch rate, as shown in Figure 2 d.Due to wafer
Surface charge amount is affected to the etch rate of wet etching, therefore the lithographic method is preferably wet etching.It can be with
According to the etching liquid of the material selection wet etching of dielectric layer.When the dielectric layer is silicon oxide layer, etching liquid can be
Dilute hydrofluoric acid solution.In one embodiment, dilute hydrofluoric acid solution uses H2The hydrofluoric acid of O and a concentration of 49% (mass ratio) with
Volume ratio 100:1 is prepared, and the diluted hydrofluoric acid of the concentration or required other concentration can also be obtained with other preparation methods
Solution.Illustratively, the measuring devices such as infrared type measurement sensor or capacitance sensor may be used to measure and feed back
The thickness of wafer and the thickness of wafer after etching is performed, and according to the thickness of etching removal and during etching before performing etching
Between calculate etch rate.
Then, step 105 is performed, the quantity of electric charge of crystal column surface is reflected according to the etch rate.Since charge is to etching
Rate has catalytic action, therefore the crystal column surface quantity of electric charge is higher, and etch rate is higher.When Fig. 3 is worked normally for PFG wherein
With rate and the relation curve of etch rate, there it can be seen that neutralization ratio is higher, i.e., crystal column surface residual charge amount is lower, then
Etch rate is lower, and the relation curve of the two is smooth, and degree of fitting is preferable.Therefore, the etching speed measured by step 104 can be passed through
Rate is compared to judge whether the neutralization ratio that PFG is generated reaches preset value with the curve in Fig. 3.
This method can measure the quantity of electric charge of crystal column surface in time after ion implantation, without waiting until that device junction is configured
Into epiphysiometer part electrical parameter and reflect by electrical parameter the residual charge of ion implanting, timeliness is strong.In execution
After stating measuring process, the dielectric layer 202 of crystal column surface can be removed, and subsequent technique is performed to the wafer 201.
So far, the processing step that the method for completing according to an exemplary embodiment of the present one is implemented.It is understood that
The method of crystal column surface residual charge amount not only includes above-mentioned steps after the detection ion implanting of the present embodiment, in above-mentioned steps
Before, other desired step is may also include among or later, is included in the range of this implementation manufacturing method.
Compared with the prior art, it is proposed by the present invention detection ion implanting after crystal column surface residual charge amount method,
The quantity of electric charge of crystal column surface can be more effectively monitored, and timeliness is strong, rate the defects of so as to reduce product.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (8)
1. a kind of method of crystal column surface residual charge amount after detection ion implanting, which is characterized in that including：
Wafer is provided；
Dielectric layer is formed in the crystal column surface；
Ion implanting is performed to the wafer for being formed with dielectric layer；
The dielectric layer is etched, and measures etch rate；
Reflect the quantity of electric charge of crystal column surface according to the etch rate.
2. according to the method described in claim 1, it is characterized in that, the dielectric layer is silicon oxide layer.
3. according to the method described in claim 2, it is characterized in that, the silicon oxide layer is the silicon oxide layer of nitrating.
4. according to the method described in one of claim 1-3, which is characterized in that the thickness of the dielectric layer is 800-1200 angstroms.
5. according to the method described in claim 1, it is characterized in that, the ion of the injection is arsenic.
6. method according to claim 1 or 5, which is characterized in that the dosage of the ion implanting is 1.0 × 1015/cm2
More than.
7. according to the method described in claim 1, it is characterized in that, the etching is wet etching.
8. the method according to the description of claim 7 is characterized in that etching liquid used in the wet etching is dilute hydrogen fluorine
Acid.
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Cited By (1)
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| CN113675106A (en) * | 2021-08-20 | 2021-11-19 | 长江存储科技有限责任公司 | Method and device for detecting surface charge amount of wafer |
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