JP2004207590A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which operates reliably by preventing the generation of a resist residue in developing in a resist process. <P>SOLUTION: Before a process of forming a resist film, the resist process of the semiconductor device is subjected to plasma treatment for generating plasma while making process gas containing gaseous oxygen and gaseous nitrogen flow on the applying surface of a resist, to remove organic materials, particles, etc. remaining on the applying surface (surfaces of a side wall insulation film 39, a silicon substrate 21, etc.) by separated oxygen radicals (O<SP>*</SP>), oxygen ions, nitride radicals (N<SP>*</SP>) and nitride ions, and to improve the quality of a surface. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a plasma treatment for preventing generation of a photoresist residue on a portion where a distance between elements is reduced and a photoresist is difficult to remove, for example, a substrate surface between adjacent transistor side wall insulating films. The present invention relates to a method for manufacturing a semiconductor device including:
[0002]
[Prior art]
In recent years, reductions in dimensions in the in-plane direction of the substrate, such as a gate width, a gate length, and an interval between transistor elements, have been rapidly advanced based on design rules. On the other hand, the size in the height direction has not been remarkably reduced. Therefore, the semiconductor device tends to have a structure with a small width and a large depth, that is, a high aspect ratio. For example, in a photoresist process frequently used in a semiconductor device manufacturing process, it is increasingly difficult to properly expose a bottom portion of the resist film and completely remove the resist film during development.
[0003]
A chemically amplified positive resist, which is a typical photoresist used in the DUV (Deep UV) wavelength region, is a base resin in which a polar group of an alkali-soluble resin is protected by another group, a photogenerating agent (PAG), and the like. It is composed of When the applied resist film is irradiated with ultraviolet rays or the like, the PAG causes an excitation reaction and releases an acid. This acid reacts with the protecting group of the base resin by heat treatment after exposure (PEB treatment), and changes the resist film to be soluble in an alkaline developer. For this reason, in a region where the excitation reaction by light is sufficiently performed, the resist film is completely dissolved by the developing solution, and no resist residue is generated.
[0004]
[Patent Document 1]
JP-A-5-152200
[0005]
[Problems to be solved by the invention]
However, as described above, as the processing size is reduced, a structure having a higher aspect ratio, for example, a substrate surface or a deep trench structure between side wall insulating films of adjacent word lines of a DRAM (Dynamic Random Access Memory) integrated device is used. That is, light of a predetermined intensity does not reach the deep groove-shaped bottom portion at the time of exposure, and the PAG excitation reaction is insufficient, so that a resist residue is generated.
[0006]
FIG. 1 is a cross-sectional view in a direction perpendicular to a direction in which a plurality of word lines of a DRAM extend in parallel. As shown in FIG. 1, after forming a sidewall insulating film 103 carried on a gate electrode 102 as a word line of a DRAM 100, a resist film 104 is formed and patterned to provide an opening. A resist residue 104-2 is likely to be generated between the sidewall insulating film 103B and the sidewall insulating film 103C in the opening 104-1 and on the surface of the substrate 101 and the like. In the vicinity of the side wall insulating film 103 and the surface of the substrate 101, the amount of exposure light to the photoresist is likely to be insufficient. Since water and the like easily adhere to and remain on these surfaces, the resist film may not be sufficiently dissolved or removed by the development treatment.
[0007]
If impurity ions are to be introduced by ion implantation with such a resist residue attached, not only the desired impurity distribution is not obtained, but also the resist residue is altered by the impact of the impurity ions, making it more difficult to remove. I will. If such a resist residue remains in the semiconductor device, it may cause an operation trouble of the DRAM integrated device in a long term, and causes a problem of lowering the operation reliability.
[0008]
Further, even if an attempt is made to form a contact plug (not shown) in such a location, the etching becomes incomplete due to the resist residue 104-2, and the contact resistance between the diffusion region 105 and the contact plug increases. Similarly, there is a problem that the operation reliability of the DRAM integrated device is reduced.
[0009]
As a countermeasure for such a problem, a method of increasing the amount of exposure to excite the PAG excitation reaction and suppressing the generation of resist residues can be considered. Although this method can suppress the generation of the resist residue, the pattern of the resist film irradiated with an excessive exposure amount is widened, so that a problem that desired dimensions cannot be obtained arises. Further, for example, in the case where the width between adjacent side wall insulating films is narrow, even if the exposure amount is increased, the exposure light is irregularly reflected on the surface of the side wall insulating film, and the exposure amount is attenuated. Insufficient excitation reaction causes a problem that a resist residue is easily generated on the substrate surface in such a region.
[0010]
In addition, the resist residue 104-2 remaining in the opening 104-1 after the pattern is formed is removed by a descum process, which is a kind of ashing process, but the amount of the remaining resist residue varies. , It is difficult to determine an appropriate processing time. Therefore, if the descum process is performed excessively, there arises a problem that the surface of the substrate 101 and the resist film 104 on which the pattern is formed are damaged.
[0011]
Furthermore, it is conceivable to suppress the generation of resist residues by optimizing the wavelength of the light to be exposed and the resist material.However, manufacturing costs have increased due to major changes such as remodeling or new purchase of exposure equipment. This causes a problem.
[0012]
Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device which prevents generation of a resist residue in a developing process of a resist process and further has a high operation reliability. It is to be.
[0013]
[Means for Solving the Problems]
According to one aspect of the present invention, a step of applying a photosensitive resin to form a resist film, a step of selectively exposing the resist film, and a step of developing the resist film to form an opening are provided. In the method for manufacturing a semiconductor device provided, a method for manufacturing a semiconductor device is provided, wherein a plasma processing step of performing a plasma processing on a coating surface of a photosensitive resin before the step of forming the resist film is provided.
[0014]
According to the present invention, before the formation of the resist film, the photosensitive resin-coated surface is subjected to plasma processing. Therefore, organic substances and particles remaining or fixed on the surface of the coating surface are removed and cleaned, and the surface is modified to prevent the resist film from being excessively adhered. As a result, it is possible to prevent the generation of a resist residue in the development processing of the resist film. By preventing the generation of the resist residue, long-term operation reliability of the semiconductor device can be maintained.
[0015]
According to another aspect of the present invention, the substrate comprises: a transistor; a transistor including a diffusion region and a gate electrode formed in an activation region of the substrate; and a sidewall insulating film supported on the gate electrode. A plurality of gate electrodes and side wall insulating films extend substantially parallel in one direction in a plane parallel to the plane, and the gate electrode is formed between two side wall insulating films formed between a pair of adjacent gate electrodes. A method of manufacturing a semiconductor device having a first width in a portion formed in parallel and a second width smaller than the first width in a portion where a plug connected to the gate electrode is provided. Forming a resist film by applying a photosensitive resin on the substrate surface and the sidewall insulating film, and exposing a region between the pair of adjacent sidewall insulating films on the substrate surface. To the resist film Selectively exposing, and developing the resist film to provide an opening, and providing a plasma processing step of performing a plasma processing on the surface of the region and the sidewall insulating film before the step of forming the resist film. A method of manufacturing a semiconductor device, characterized by the following, is provided.
[0016]
According to the present invention, in the semiconductor device, the width (second width) between the pair of adjacent side wall insulating films is such that the pair of side wall insulating films adjacent to each other in a portion where the plurality of gate electrodes are formed in parallel. (First width). The portion where the second width is formed is a case where a via plug for inputting a control signal or the like is formed in contact with the gate electrode. In the portion formed with such a small second width, the amount of exposure light is attenuated even in an exposure region that is wide open including the portion, so that sufficient exposure light is not irradiated, and the resist residue is reduced. It is easy to occur. According to the present invention, when an opening of a resist film is provided so that a region of a substrate surface between a pair of adjacent side wall insulating films is exposed, plasma processing is performed before forming a resist film. Organic substances and the like remaining in the region are removed and cleaned, and the surface is modified so that the resist film is not excessively adhered. Generation of a resist residue in the development process of such a region can be prevented.
[0017]
Before the plasma processing step, a step of cleaning the coated surface of the photosensitive resin by wet processing is provided. The wet process makes it possible to remove particles on the application surface. Further, a cleaning agent used for the wet treatment, for example, ammonium hydroxide may remain, but can be removed by a subsequent plasma treatment step, and the reaction between the residue and the PAG of the resist film can be prevented. In addition, it is possible to prevent the generation of a resist residue in the development processing of the resist film.
[0018]
The plasma processing is performed by discharging the processing gas with high frequency power and heating the substrate. Since the substrate is heated, radicals or ions of the gas species of the processing gas excited by the high-frequency power efficiently react with organic substances or particles remaining or fixed on the coated surface of the resist and are gasified. The surface can be further cleaned. Further, the processing gas is O _Two Gas may be included. O _Two Since the oxygen radical O * from which the gas has been dissociated has a high reactivity, it can be further purified.
[0019]
The plasma processing is an isotropic plasma processing. By processing the region of the substrate surface in which the width between the pair of adjacent side wall insulating films is formed to be narrow by isotropic plasma, not only the substrate surface but also the surface of the side wall insulating film formed obliquely is processed. Can be cleaned and modified.
[0020]
Further, the photosensitive resin is a chemically amplified resist. Further, the photosensitive resin may be of a positive type. Chemically-amplified resists have good sensitivity to exposure light, and positive-type resists also have excellent resolution. Therefore, generation of resist residue can be prevented even at the bottom of a structure having a high aspect ratio.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
According to the present invention, as described above, the bottom of a resist film such that exposure light does not sufficiently reach, particularly, for example, a side wall insulating film carrying a word line in a memory integrated device is formed close to an adjacent side wall insulating film. Means for forming a desired resist pattern in a narrow portion without generating a resist residue at the time of development processing.
[0022]
First, the flow of the resist process according to the present invention will be briefly described. FIG. 2 is a flowchart of the resist process according to the present invention.
[0023]
Referring to FIG. 2, at the beginning of the resist process, a plasma process is performed on a surface to which a photosensitive resin (hereinafter, the photosensitive resin is referred to as a resist) is applied (S102). By generating a plasma while flowing a process gas containing an oxygen gas, a cleaning agent and a rinsing liquid in a cleaning step before the resist step, particularly a wet step, are removed, and the resist-coated surface is further modified. Next, resist coating (S104), soft baking (S106), exposure (S108), PEB (heating process) (S110), and then development process (S112) are performed. In the developing treatment, the portion irradiated with the exposure light which has become soluble in the alkaline aqueous solution is removed. Since organic substances, cleaning agents, and the like on the surface of the substrate on which the resist is applied are removed by the plasma treatment, no resist residue is generated. Next, post baking (S114), impurity ions are implanted using the resist as a mask to form a diffusion region and the like (S116), and the resist is removed (S118). As described above, the present invention is characterized in that plasma treatment is performed before resist application.
[0024]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0025]
FIG. 3 is a plan view of the flash memory integrated device. FIG. 4 is a sectional view taken along the line X′-X ′ shown in FIG. Referring to FIGS. 3 and 4, the flash memory integrated device 10 includes a semiconductor substrate 20, an element isolation film 17 formed on the semiconductor substrate, an activation region 16 defined in the element isolation film 17, A diffusion region 18 formed on the substrate 20, a tunnel oxide film 19 formed on the surface of the semiconductor substrate 20, a floating gate 11 and a control gate formed on the semiconductor substrate 20 and extending in the Y direction shown in FIG. And a side wall insulating film 15 formed on both sides of the stacked body 14 and the like. Hereinafter, a method of manufacturing the flash memory integrated device will be described.
[0026]
FIGS. 5A to 7I are cross-sectional views showing the steps of manufacturing a flash memory.
[0027]
In the step shown in FIG. 5A, a silicon oxide film 22 having a thickness of 10 nm is formed by surface thermal oxidation on a silicon substrate 21 having a main surface (100) into which p-type impurity ions have been introduced. On the silicon oxide film 22, a silicon nitride film 23 having a thickness of 20 nm is formed by a CVD method. Further, a silicon oxide film 24 having a thickness of 100 nm is formed on the silicon nitride film 23 by a CVD method. A resist film 25 is formed on the silicon oxide film 24, and the resist film 25 is patterned so that a portion to be an element isolation region is opened to provide an opening 25-1.
[0028]
Next, in the step of FIG. 5B, the silicon oxide films 22, 24 and the silicon nitride film 23 in the opening 25-1 are removed by an anisotropic etching method. Next, the resist film 25 is removed. The surface of the silicon substrate 21 is etched to a depth of 300 nm using the remaining stack of the silicon oxide films 22 and 24 and the silicon nitride film 23 as a mask to form a trench 21-1.
[0029]
Next, in the step of FIG. 5C, a 20 nm thick silicon oxide film 26 is formed in the trench 21-1 by surface thermal oxidation, and then the trench 21-1 is filled with a 500 nm thick silicon oxide film 28 by a CVD method. . Using the silicon nitride film 23 shown in FIG. 5B as a polishing stopper, planarization is performed by a CMP (chemical mechanical polishing) method, and then the silicon nitride film 23 is peeled off. Thus, an element isolation region 29 having the element isolation film 28 is formed.
[0030]
Next, in the step of FIG. 6D, the silicon oxide film 22 shown in FIG. 5C on the surface of the silicon substrate 21 is removed with hydrofluoric acid to expose the surface of the silicon substrate 21. A tunnel oxide film 30 of a silicon oxide film is formed. Next, a 100 nm-thick amorphous silicon film 31 (corresponding to the floating gate 11 shown in FIG. 4) doped with phosphorus (P) is formed on the tunnel oxide film 30. An ONO film 32 (a stacked film of a silicon oxide film (thickness: 10 nm) / silicon nitride film (10 nm) / silicon oxide film (5 nm)) is further formed thereon by a CVD method.
[0031]
6D, a 100 nm-thick amorphous silicon film 33 (corresponding to the control gate 12 shown in FIG. 4) doped with phosphorus (P) by the CVD method is further formed on the ONO film 32. Form. Next, a 20 nm-thick silicon oxide film 34 is further formed on the amorphous silicon film 33 by a CVD method.
[0032]
Next, in the step of FIG. 6E, a photoresist film (not shown) is formed on the structure of FIG. 6D, and patterning is performed using a reticle optically opened in the Y direction shown in FIG. Then, a stacked body 35 of the floating gate 11 and the control gate 12 shown in FIG. 4 is formed. Next, after the resist film is peeled off and washed, B ions are implanted at an accelerating voltage of 65 keV to 4.5 × 10 4 by an ion implantation method using the laminate 35 as a mask. ^Three Pieces / cm ^Two Is implanted to form an LDD region 36.
[0033]
Next, in the step of FIG. 6F, a silicon nitride film 38 having a thickness of 100 nm is formed by a CVD method so as to cover the entire structure of FIG. 6E.
[0034]
Next, in the step of FIG. 7G, the silicon nitride film 38 is etched by the RIE method to form the side wall insulating film 39. Specifically, the etching is performed until the fluorocarbon-based gas reaches the silicon oxide films 30 and 34 serving as the etching stopper by the fluorine-based radicals or ions dissociated.
[0035]
In the step of FIG. 7G, organic substances, particles, and the like generated by the etching are further removed by ashing. Specifically, using a barrel type ashing apparatus, the pressure in the ashing apparatus is set to 80 Pa (0.6 Torr), the oxygen gas flow rate is set to 1500 sccm, the substrate temperature is set to 90 ° C., and the RF power is set to 1300 W, and ashing is performed for 60 minutes. Do.
[0036]
In the step of FIG. 7G, particles that cannot be completely removed by ashing are further removed by a wet process. Specifically, a sulfuric acid-based cleaning solution (including dilute sulfuric acid and hydrogen peroxide) heated to 135 ° C. was washed for 20 minutes by an immersion type washing device, and then heated to 40 ° C. by the same washing device. Washing is performed for 10 minutes using an alkali washing solution (including ammonium hydroxide, hydrogen peroxide and water). Next, rinsing is performed using pure water by a spin method. Note that the above wet process may be repeated a plurality of times.
[0037]
In the step of FIG. 7G, the plasma processing of the surface of the silicon substrate 21 and the side wall insulating film 39 is further performed by a plasma processing apparatus or an ashing apparatus. For the plasma treatment, a plasma etching apparatus or a plasma ashing apparatus can be used. Examples of the plasma ashing apparatus include a parallel plate type plasma asher, a microwave asher, a high density plasma asher, a barrel type plasma asher, a downstream asher, and a combination of these ashers. As an example, using a microwave downstream asher, the RF frequency is 2.45 GHz, the RF power is 100 W to 2000 W, the flow ratio of oxygen gas to nitrogen gas is 100: 1 to 1: 1 and the pressure is 4 Pa (30 mTorr) or more. The processing is performed for 10 seconds to 100 seconds while setting the heating temperature of the silicon substrate 21 at 3990 Pa (30 Torr) and 25 ° C. to 300 ° C.
[0038]
Here, even if the processing gas of the plasma processing is only nitrogen gas, the sputtering effect of nitrogen ions and the nitrogen radical (N ^* ) Can remove deposits and the like on the surfaces of the silicon substrate 21 and the side wall insulating film 39. However, by adding oxygen gas, oxygen ions or oxygen radicals (O ^* ) Can be further purified.
[0039]
Further, by heating the silicon substrate 21, water and the like adsorbed on the surface of the silicon substrate 21 are vaporized, and the reaction speed of the above-described oxygen ions or oxygen radicals is increased, so that the process time can be shortened. .
[0040]
Further, a high-frequency bias may be applied to the substrate holder. Sputtering effects due to dissociated oxygen ions, nitrogen ions, and the like become larger, and deposits and the like on the surfaces of the silicon substrate 21 and the side wall insulating film 39 can be more efficiently removed.
[0041]
Here, as an example of the processing conditions, an oxygen gas of 3000 sccm, a nitrogen gas of 130 sccm, a pressure of 200 Pa (1.5 Torr), and a heating temperature of the silicon substrate 21 of 270 ° C. were used.
[0042]
Next, in the step of FIG. 7H, a resist is applied and patterning is performed. Specifically, a chemically amplified resist can be used as the resist. As the chemically amplified resist, either a positive type or a negative type can be used, but a positive type is preferable from the viewpoint of resolution. As the base polymer of the chemically amplified resist, a polyvinylphenol-based, polyacrylic-acid-based, novolak resin, or the like can be used, and is not particularly limited thereto. From the viewpoint of the wavelength of the exposure light, in the case of a KrF excimer laser (wavelength: 248 nm), a polyvinylphenol-based compound is preferable in terms of transparency. In the case of an ArF excimer laser (wavelength 193 nm), polyacrylic acid is preferable in terms of transparency. Here, as an example, a resist film 40 having a thickness of 700 nm is formed by a spin coating method using poly (t-butoxycarbonyloxystyrene) in which a positive base polymer is a polyvinylphenol-based polymer. Next, soft baking is performed at 130 ° C. for 60 seconds using a halogen lamp or the like.
[0043]
In the step of FIG. 7H, exposure is further performed using a KrF excimer laser (wavelength: 248 nm) via a reticle 41 on which a pattern that transmits exposure light in the Y direction of FIG. 3 is formed. The irradiation energy is set to be smaller than the pattern of the reticle 41, specifically, 240 J / cm. ^Two ~ 280J / cm ^Two More choice. By this exposure, the resist film 40 is converted into a resist film 40A made of an alkali-soluble polymer.
[0044]
In the step of FIG. 7H, PEB processing (heating processing) is further performed at 130 ° C. for 90 seconds in an oven furnace. The heat treatment further activates the action of the acid catalyst, thereby further improving the uniformity of the alkali-soluble polymer in the resist film 40A.
[0045]
Next, in the step of FIG. 7I, development is performed to remove the exposed resist film 40A. Specifically, a paddle development is performed by dropping a developing solution of an alkaline aqueous solution on the surfaces of the resist films 40 and 40A. The exposed resist film 40A is dissolved and removed by the alkaline aqueous solution. Next, a post-baking process is performed to increase the adhesion of the patterned resist film 40.
[0046]
In the step of FIG. 7I, impurity ions are further introduced into the activated region where the resist film is opened. Specifically, As ions are implanted by an ion implantation method at an acceleration voltage of 40 keV and a number density of 3 × 10 3. ^Fifteen Pieces / cm ^Two And the drain region 42 is formed in the silicon substrate 21 through the opening 40-1 of the resist film.
[0047]
In the step of FIG. 7I, the resist film 40 is further removed by a wet process. Specifically, cleaning is performed for 30 seconds using hydrofluoric acid at a liquid temperature of 20 ° C. by an immersion type cleaning apparatus, and then a sulfuric acid-based cleaning liquid (dilute sulfuric acid and excess (Including hydrogen oxide) for 20 minutes. Next, rinsing is performed using pure water by a spin method.
[0048]
Further, a flash memory integrated device is formed by introducing impurity ions into a known source region, forming an interlayer insulating film, and further via a wiring layer and the like.
[0049]
When the structure of FIG. 7G was observed by SEM, no resist residue was found on the surfaces of the silicon substrate 21 and the side wall insulating film 39. Similarly, no resist residue was observed on the surface of the structure after the resist was peeled off after the ion implantation in the step of FIG.
[0050]
As described above, it has been described that by performing the plasma treatment according to the present invention, it is possible to prevent the generation of the resist residue by removing the deposits and the like on the surfaces of the silicon substrate 21 and the side wall insulating film 39. The inventor of the present application speculates about the further operation and effect of the plasma treatment before the application of the resist as described below through various studies.
[0051]
In the structure of FIG. 7G, when the surface of the silicon oxide film 30 on the silicon substrate 21 after the wet processing is observed by microscopic FT-IR (infrared spectroscopy), an amino group (—NH _Two ) Was observed. Accordingly, it is assumed that the resist residue is formed by bonding Si of the silicon oxide film 30 and C or O of the resist film 40 due to a dehydration reaction between an amino group and a hydroxyl group (-OH) of the resist film. Further, it is presumed that the generation of such a bond inhibits the generation of an acid which should originally occur due to the exposure light. By the plasma treatment according to the present invention, the dangling bond of Si on the surface of the silicon oxide film 30 on the silicon substrate 21 is converted into oxygen radicals (O ^* ) And nitrogen radicals (N ^* It is presumed that by terminating with (2), excessive bonding with the resist film was prevented, and the original reaction of acid generation and alkali solubilization was able to occur.
[0052]
According to the present embodiment, the plasma treatment is performed on the surface on which the resist is applied before the resist is applied, so that residues such as a cleaning process in a process before the application of the resist, for example, water and ammonium hydroxide constituting the cleaning agent And the like can be volatilized and removed, and dangling bonds of silicon atoms on the surface to which the resist is applied are terminated by oxygen radicals in the plasma, thereby reducing the activity. As a result, even if the space between adjacent sidewall insulating films is narrow, such as the surface of the substrate, the resist exposed in the development processing can be completely removed, and the generation of resist residues can be prevented. be able to.
[0053]
In some cases, a via plug is formed in the floating gate to input a control signal at a part where the stacked body in which the floating gate and the control gate sandwich the insulating film is formed and extends.
[0054]
FIG. 8 is a sectional view of another example of the flash memory integrated device. The flash memory integrated device 50 includes a semiconductor substrate 20, an element isolation film 17 formed on the semiconductor substrate 20, and a floating gate 11 and a control gate 12 formed on the semiconductor substrate 20 with an insulating film 13 interposed therebetween. And a via plug 51 that is in contact with the floating gate 11 and receives a control signal, a sidewall insulating film 15 formed on both sides of the stacked body 14, an interlayer insulating film 52, and the like.
[0055]
The characteristic feature is that the width of the laminated body 14C to which the via plug 51 is connected is large, so that the width between the interlayer insulating film 15C1 of the laminated body 14C and the interlayer insulating film 15B2 of the adjacent laminated body 14B is large. W2 is smaller than the width W1 of the interlayer insulating films 15A2 and 15B1 of the stacked bodies 14A and 14B where no via plug is formed.
[0056]
In the substrate surface region 20BC in which the space between the adjacent sidewall insulating films 15B2 and 15C1 is formed with a smaller width W2, for example, a resist mask used in a step of performing ion implantation into an activation region is formed. In the step of exposing the resist film, the exposure light is irregularly reflected on the surfaces of the side wall insulating films 15B2 and 15C1, and the amount of the exposure light is attenuated.
[0057]
In addition, as the cell size of the transistor becomes smaller, the width between the adjacent sidewall insulating films becomes further smaller, and in the portion of the substrate surface between the sidewall insulating films that does not substantially become the source or drain region, In some cases, the width between adjacent sidewall insulating films may be 100 nm or less. At present, according to the examination of experiments and the like by the inventor of the present application, the plasma processing according to the present invention has caused a change in the conditions for forming the sidewall insulating film and the alignment of the mask pattern. It is known that no residue is generated.
[0058]
Even in such a region, generation of a resist residue can be prevented by subjecting the resist-coated surface to plasma treatment with the plasma apparatus described in the above embodiment before applying the resist in this embodiment. In particular, it is preferable to use an isotropic plasma treatment. For example, a parallel plate type plasma asher or a barrel type plasma asher capable of performing isotropic ashing or isotropic plasma processing can be used. The effect of modifying the surface of the sidewall insulating film becomes more effective, and the generation of resist residues can be further prevented.
[0059]
Although the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the specific embodiment, and various modifications and changes may be made within the scope of the present invention described in the claims. It is possible. For example, in the above-described embodiment, an example of irradiation with ultraviolet light has been described. However, the plasma treatment of the present invention is not limited to ultraviolet light exposure, but may be performed using a charged particle beam such as an electron beam, X-ray, or ion beam. Can also be applied. Further, even if the width between a pair of adjacent side wall insulating films becomes narrower as the design rule is reduced in the future, the present invention can prevent the generation of resist residues in the developing process.
[0060]
In addition, the following supplementary notes are disclosed with respect to the above description.
(Supplementary Note 1) a step of applying a photosensitive resin to form a resist film;
Selectively exposing the resist film,
Providing an opening by developing the resist film.
A method for manufacturing a semiconductor device, further comprising: a plasma processing step of performing a plasma processing on a coating surface of a photosensitive resin before a step of forming the resist film.
(Supplementary Note 2) Substrate
A transistor comprising a diffusion region and a gate electrode formed in an activation region of the substrate,
A sidewall insulating film carried on the gate electrode,
A plurality of gate electrodes and sidewall insulating films extend substantially parallel in one direction on a plane parallel to the substrate surface,
A portion between two side wall insulating films formed between a pair of adjacent gate electrodes has a first width in a portion where the gate electrode is formed in parallel, and a plug connected to the gate electrode has a first width. A method for manufacturing a semiconductor device having a second width smaller than the first width in a portion provided,
Forming a resist film by applying a photosensitive resin on the substrate surface and the sidewall insulating film,
Selectively exposing the resist film so that a region between the pair of adjacent sidewall insulating films on the substrate surface is exposed,
Developing an opening by developing the resist film,
A method of manufacturing a semiconductor device, comprising: performing a plasma processing step of performing a plasma processing on the surface of the region and the sidewall insulating film before the step of forming the resist film.
(Supplementary note 3) The method for manufacturing a semiconductor device according to supplementary note 2, wherein the second width is not less than 20 nm and not more than 100 nm.
(Supplementary Note 4) The method for manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 3, wherein a step of cleaning the coated surface of the photosensitive resin by wet processing before the plasma processing step is provided. .
(Supplementary Note 5) The method for manufacturing a semiconductor device according to Supplementary Note 4, wherein the wet treatment includes ammonium hydroxide.
(Supplementary Note 6) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 5, wherein the plasma processing is performed by discharging the processing gas by high-frequency power and heating the substrate.
(Supplementary Note 7) The processing gas is O _Two The method for manufacturing a semiconductor device according to claim 6, further comprising a gas.
(Supplementary Note 8) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the plasma processing is performed by an ashing device.
(Supplementary Note 9) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 8, wherein the plasma processing is an isotropic plasma processing.
(Supplementary Note 10) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 9, wherein the photosensitive resin is a chemically amplified resist.
(Supplementary Note 11) The method of manufacturing a semiconductor device according to any one of Supplementary Notes 1 to 10, wherein the photosensitive resin is a positive chemically amplified resist.
(Supplementary Note 12) The method of manufacturing a semiconductor device according to supplementary note 11, wherein the photosensitive resin includes poly (t-butoxycarbonyloxystyrene).
[0061]
【The invention's effect】
As is apparent from the details described above, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device which prevents generation of a resist residue in a developing process in a resist process. As a result, a method for manufacturing a semiconductor device with high operation reliability can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view in a direction perpendicular to a direction in which a plurality of word lines of a DRAM extend in parallel.
FIG. 2 is a flowchart of a resist process according to the present invention.
FIG. 3 is a plan view of the flash memory integrated device.
FIG. 4 is a sectional view of the flash memory integrated device taken along line XX of FIG. 3;
FIGS. 5A to 5C are cross-sectional views illustrating a manufacturing process (part 1) of the flash memory integrated device.
FIGS. 6D to 6F are cross-sectional views illustrating a manufacturing process (part 2) of the flash memory integrated device.
FIGS. 7G to 7I are cross-sectional views illustrating a manufacturing process (part 3) of the flash memory integrated device.
FIG. 8 is a sectional view of another example of a flash memory integrated device.
[Explanation of symbols]
10,50 flash memory integrated device
11 Floating gate
12 Control gate
13 Insulating film
14, 14A, 14B, 14C laminated body
15, 15A1, 15A2, 15B1, 15B2, 15C1, 15C2, 39 Side wall insulating film
16 Activation area
17 Device isolation film
19, 30 Tunnel oxide film
20 Semiconductor substrate
21BC substrate surface area
21 Silicon substrate
29 Element isolation area
31, 33 amorphous silicon film
32 ONO film
40 resist film
40A Resist film made of alkali-soluble polymer
51 Via plug
52 Interlayer insulating film
O * oxygen radical
N * nitrogen radical
W1, W2 Width between a pair of adjacent sidewall insulating films

Claims (10)

A step of applying a photosensitive resin to form a resist film,
Selectively exposing the resist film,
Providing an opening by developing the resist film.
A method for manufacturing a semiconductor device, further comprising: a plasma processing step of performing a plasma processing on a coating surface of the photosensitive resin before the step of forming the resist film. Board and
A transistor comprising a diffusion region and a gate electrode formed in an activation region of the substrate,
A sidewall insulating film carried on the gate electrode,
A plurality of gate electrodes and sidewall insulating films extend substantially parallel in one direction on a plane parallel to the substrate surface,
A portion between two side wall insulating films formed between a pair of adjacent gate electrodes has a first width in a portion where the gate electrode is formed in parallel, and a plug connected to the gate electrode has a first width. A method for manufacturing a semiconductor device having a second width smaller than the first width in a portion provided,
Forming a resist film by applying a photosensitive resin on the substrate surface and the sidewall insulating film,
Selectively exposing the resist film so that a region between the pair of adjacent sidewall insulating films on the substrate surface is exposed,
Developing an opening by developing the resist film,
A method of manufacturing a semiconductor device, comprising: performing a plasma processing step of performing a plasma processing on the surface of the region and the sidewall insulating film before the step of forming the resist film. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of cleaning the coated surface of the photosensitive resin by wet processing before the plasma processing step. 4. The method according to claim 3, wherein the wet treatment includes ammonium hydroxide. The method of manufacturing a semiconductor device according to claim 1, wherein the plasma processing is performed by discharging the processing gas by high-frequency power and heating the substrate. The method according to claim 5, wherein the processing gas includes an O ₂ gas. The method according to claim 1, wherein the plasma processing is performed by an ashing apparatus. 8. The method according to claim 1, wherein the plasma processing is an isotropic plasma processing. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the photosensitive resin is a chemically amplified resist. 10. The method according to claim 1, wherein the photosensitive resin is a positive chemically amplified resist.

Images