JPS6173330A - Equipment for manufacturing semiconductor device - Google Patents

Equipment for manufacturing semiconductor device

Info

Publication number
JPS6173330A
JPS6173330A JP59194980A JP19498084A JPS6173330A JP S6173330 A JPS6173330 A JP S6173330A JP 59194980 A JP59194980 A JP 59194980A JP 19498084 A JP19498084 A JP 19498084A JP S6173330 A JPS6173330 A JP S6173330A
Authority
JP
Japan
Prior art keywords
resist
wafer
periphery
coating
coated surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59194980A
Other languages
Japanese (ja)
Inventor
Makoto Kitakata
北方 誠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59194980A priority Critical patent/JPS6173330A/en
Publication of JPS6173330A publication Critical patent/JPS6173330A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To enhance the yield of manufacturing a semiconductor device by exposing a resist coated surface of the periphery of a wafer in the step of coating the positive type resist, developing the resist, and then exposing the surface of the periphery, thereby preventing the resist residue from generating. CONSTITUTION:A resist coating unit 5 has a chuck 6 or sucking in vacuum a wafer and rotating it, and a dropping nozzle 7 mounted directly above the chuck 6. In the step of coating a resist, a shielding cover 10 for separating the resist coated surface 8a of the periphery of the wafer from the resist coated surface 8b of the center of the wafer, and a mercury lamp 11a for emitting the coated surface 8a separated by a cover 10 are providing, and the periphery of the wafer is annularly exposed in the prescribed width during coating the resist or after coating the resist by rotating the wafer or rotating at every prescribed angle in the step of coating the resist. Thus, since only the periphery of the wafer is preliminarily exposed, the surface of the periphery of the wafer is exposed after developing the resist. Since a wafer clamp is contacted with the surface, there is no fear of the residue.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体デバイス製造工程において用いられる
半導体デバイス製造装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device manufacturing apparatus used in a semiconductor device manufacturing process.

〔従来の技術〕[Conventional technology]

半導体デバイス製造では、感光性樹脂を用いたパターン
形成技術が広く適用されている。この感光性樹脂には、
感光することによって不溶となるネガ型レジストと、感
光することによって溶解度が大きくなるレジストがある
Pattern forming techniques using photosensitive resins are widely applied in semiconductor device manufacturing. This photosensitive resin has
There are negative resists that become insoluble when exposed to light, and resists that become more soluble when exposed to light.

イ、ガ型レジストを用いA場合には、つ、バー周辺を意
図的に未露光領域とすることにより、レジスト・パター
ン形成において、レジストを溶解させウェハー表面を露
出させることが容易に可能である。
B. In the case of A using a G-type resist, by intentionally leaving the area around the bar unexposed, it is easy to dissolve the resist and expose the wafer surface during resist pattern formation. .

一方、ポジ型レジストを用いる場合には、逆に意図的に
露光領域としなければウェハ周辺部には、パターン形成
後もレジストが残っている。
On the other hand, when a positive resist is used, the resist remains at the periphery of the wafer even after pattern formation unless the exposed area is intentionally exposed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このウェハー周辺部のレジスト2は、例えば第3図(a
)に示すようなウェハー・クランプ1による機械的接触
によって、容易に剥離し、ウェハーのデバイス・パター
ン3上のレジスト残滓4となる。
The resist 2 at the periphery of the wafer is, for example, as shown in FIG.
) is easily peeled off by mechanical contact by the wafer clamp 1 as shown in FIG.

こうしたレジスト残滓は、高い集積度を特徴とするLS
I等の半導体デバイス製造において、致命的なパターン
欠陥等゛を起こし、製造上の歩留りを低下させる。
These resist residues are used for LS, which is characterized by a high degree of integration.
In the manufacture of semiconductor devices such as I, fatal pattern defects etc. are caused and the manufacturing yield is reduced.

本発明の目的は、ポジ型レジストを用いる場合において
ウェハー周辺部を有効に表面露出させる装置を提供する
ことにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an apparatus that effectively exposes the peripheral area of a wafer when using a positive resist.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は回転するウエノ・−の表面上にポジ型レジスト
を塗布する塗布装置に、レジスト塗布工程にてウェハー
周辺部のレジスト塗布面を選択的に露光する露光機を装
備したことを特徴とする半導体デバイス製造装置でちる
The present invention is characterized in that a coating device that coats a positive resist onto the surface of a rotating wafer is equipped with an exposure machine that selectively exposes the resist-coated surface around the wafer in the resist coating process. Semiconductor device manufacturing equipment.

〔実施例〕〔Example〕

以下に本発明の一実施例を図により説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図において、レジスト塗布装置5はウエノ嶌−真空
吸着しこれを回転するチャック6と、該チャック6の真
上に設置される滴下ノズル7とを有し、滴下ノズル7よ
り滴下されたレジスト9をウェハー8の回転力にてその
表面上に均一な膜厚に塗布する。
In FIG. 1, a resist coating device 5 has a chuck 6 that vacuum-chucks a Uenoshima and rotates it, and a dripping nozzle 7 installed directly above the chuck 6. 9 is applied onto the surface of the wafer 8 to a uniform thickness by the rotational force of the wafer 8.

本発明はこのレジスト塗布装置5に、レジスト塗布工程
にて、ウェハー周辺部のレジスト塗布面を露光する露光
機を装備したものである。この露光機はウェハー周辺部
のレジスト塗布後8aをウェハー中央のレジスト塗布面
8bより隔離する遮光カバー10と、遮光カバー10に
て隔離されたレジスト塗布面8aに照射する水銀ランプ
llaとを有し、レジスト塗布工程にて、ウェハーを回
転させつつ、又は一定角度づつ回転させて、レジスト塗
布中或いはレジスト塗布後、ウニ・・−周辺を一定幅で
環状に露光する。
According to the present invention, the resist coating apparatus 5 is equipped with an exposure machine that exposes the resist coated surface of the wafer periphery in the resist coating process. This exposure machine has a light-shielding cover 10 that isolates the resist-coated surface 8a at the periphery of the wafer from the resist-coated surface 8b at the center of the wafer, and a mercury lamp lla that irradiates the resist-coated surface 8a isolated by the light-shielding cover 10. In the resist coating process, the wafer is rotated or rotated at a constant angle, and the periphery of the sea urchin is exposed in a circular manner with a constant width during or after resist coating.

したがって、レジスト塗布時にウエノ)−周辺部のみに
予備的露光が行なわれるため、レジスト現像後にウェハ
ー周辺部のウェハー表面8Cが露出する。そのため、ウ
ェノ・・クランプ1をこのウェハー表面8Gに接触させ
ることになるから、レジスト残滓の心配がなくなる。
Therefore, since preliminary exposure is performed only on the wafer periphery during resist application, the wafer surface 8C at the wafer periphery is exposed after resist development. Therefore, since the wafer clamp 1 is brought into contact with the wafer surface 8G, there is no need to worry about resist residue.

前実施例の露光機では遮光カバー10にて、露光するレ
ジスト塗布面をウェハー周辺のみに限定するようにした
が、第2図の実施例では光ファイバー12にて水銀ラン
プllbの照射光を集光させてこれをウェハー周辺部の
レジスト塗布面のみに制限して照射し露光を行なうもの
で、第1の実施例と同様な効果が得られる。その際、レ
ンズ13と光ファイバー12との間に7ヤツター14を
設け、光ファイバー12の光路の開閉制御を行ないなが
ら、露光を行なうことは露光する上で有効である。また
、本実施例のように光ファイバー12を用いる場合には
、ウェハー回転機構(チャック6など)と水銀ランプl
lbとを隔離することができ、装置の構造設計上の自由
度を増す等の利点がある。
In the exposure machine of the previous embodiment, the resist coated surface to be exposed was limited to only the periphery of the wafer using the light-shielding cover 10, but in the embodiment of FIG. Then, the irradiation is performed by restricting the irradiation to only the resist-coated surface at the periphery of the wafer, and the same effect as in the first embodiment can be obtained. At this time, it is effective to provide a seven-layer lens 14 between the lens 13 and the optical fiber 12 and to perform exposure while controlling the opening and closing of the optical path of the optical fiber 12. In addition, when using the optical fiber 12 as in this embodiment, the wafer rotation mechanism (chuck 6, etc.) and the mercury lamp l
This has the advantage of increasing the degree of freedom in the structural design of the device.

〔発明の効果〕〔Effect of the invention〕

本発明は以上説明したように、ポジ型レジスト塗布工程
にてウェハー周辺部のレジスト塗布面を露光し、レジス
ト現像後に該ウニノー−周辺部の表面を露出するように
したので、ウエノ1−・クランプにて該ウェハーをハン
ドリングする際に、レジスト残滓が発生せず、ウェハー
上のデバイス・パターンを汚すことがないから、デバイ
ス製造上の歩留りを向上できる効果を有するものである
As explained above, the present invention exposes the resist-coated surface at the periphery of the wafer in the positive resist coating process, and exposes the surface at the periphery of the wafer after resist development. When the wafer is handled at the wafer, no resist residue is generated and the device pattern on the wafer is not contaminated, which has the effect of improving the yield in device manufacturing.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す断面図、第2図は本発
明の他の実施例を示す断面図、第3図(a)は従来技術
によるポジ型レジスト塗布ウェハーの平面図、第3図[
有])は本発明によるポジ型レジスト4女^ 、−^豆
需闇4よフ 5・・・・・・レジスト塗布装置、  6・・・・・チ
ャック7・・・・・・滴下ノズル     8・・・・
・・ウェハー10・・・・・・遮光カバー    11
a、llb・・・・・・水銀ランプ12・・・・・・光
ファイバー 第2図
FIG. 1 is a sectional view showing one embodiment of the present invention, FIG. 2 is a sectional view showing another embodiment of the invention, and FIG. 3(a) is a plan view of a positive resist coated wafer according to the prior art. Figure 3 [
]) is a positive resist according to the present invention 4, -^ Bean demand 4, 5... Resist coating device, 6... Chuck 7... Dripping nozzle 8・・・・・・
... Wafer 10 ... Light-shielding cover 11
a, llb...Mercury lamp 12...Optical fiber Figure 2

Claims (1)

【特許請求の範囲】[Claims] (1)回転するウェハーの表面上にポジ型レジストを塗
布する塗布装置に、レジスト塗布工程にてウェハー周辺
部のレジスト塗布面を選択的に露光する露光機を装備し
たことを特徴とする半導体デバイス製造装置。
(1) A semiconductor device characterized in that a coating device that coats a positive resist onto the surface of a rotating wafer is equipped with an exposure machine that selectively exposes the resist-coated surface around the wafer in the resist coating process. Manufacturing equipment.
JP59194980A 1984-09-18 1984-09-18 Equipment for manufacturing semiconductor device Pending JPS6173330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59194980A JPS6173330A (en) 1984-09-18 1984-09-18 Equipment for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59194980A JPS6173330A (en) 1984-09-18 1984-09-18 Equipment for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPS6173330A true JPS6173330A (en) 1986-04-15

Family

ID=16333537

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59194980A Pending JPS6173330A (en) 1984-09-18 1984-09-18 Equipment for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPS6173330A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021114A (en) * 1988-01-29 1990-01-05 Ushio Inc Exposure of periphery of wafer and apparatus
US4910549A (en) * 1987-08-28 1990-03-20 Tokyo Electron Limited Exposure method and apparatus therefor
JPH02114628A (en) * 1988-10-25 1990-04-26 Ushio Inc Peripheral exposure of wafer
JPH02114629A (en) * 1988-10-25 1990-04-26 Ushio Inc Peripheral exposure of wafer
JPH0260229U (en) * 1988-10-25 1990-05-02
JPH0260230U (en) * 1988-10-25 1990-05-02
JPH02288326A (en) * 1989-04-28 1990-11-28 Dainippon Screen Mfg Co Ltd Apparatus for exposing periphery of wafer to light
US5028955A (en) * 1989-02-16 1991-07-02 Tokyo Electron Limited Exposure apparatus

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5868748A (en) * 1981-10-21 1983-04-23 Hitachi Ltd Photomask and developing method using said mask
JPS5892221A (en) * 1981-11-27 1983-06-01 Nec Kyushu Ltd Semiconductor substrate exposure device
JPS58139144A (en) * 1982-02-13 1983-08-18 Nec Corp Matching exposure device
JPS59138335A (en) * 1983-01-28 1984-08-08 Toshiba Corp Exposing device for resist on end portion of wafer
JPS59158520A (en) * 1983-02-28 1984-09-08 Toshiba Corp Irradiating device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5868748A (en) * 1981-10-21 1983-04-23 Hitachi Ltd Photomask and developing method using said mask
JPS5892221A (en) * 1981-11-27 1983-06-01 Nec Kyushu Ltd Semiconductor substrate exposure device
JPS58139144A (en) * 1982-02-13 1983-08-18 Nec Corp Matching exposure device
JPS59138335A (en) * 1983-01-28 1984-08-08 Toshiba Corp Exposing device for resist on end portion of wafer
JPS59158520A (en) * 1983-02-28 1984-09-08 Toshiba Corp Irradiating device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910549A (en) * 1987-08-28 1990-03-20 Tokyo Electron Limited Exposure method and apparatus therefor
JPH021114A (en) * 1988-01-29 1990-01-05 Ushio Inc Exposure of periphery of wafer and apparatus
JPH02114628A (en) * 1988-10-25 1990-04-26 Ushio Inc Peripheral exposure of wafer
JPH02114629A (en) * 1988-10-25 1990-04-26 Ushio Inc Peripheral exposure of wafer
JPH0260229U (en) * 1988-10-25 1990-05-02
JPH0260230U (en) * 1988-10-25 1990-05-02
US5028955A (en) * 1989-02-16 1991-07-02 Tokyo Electron Limited Exposure apparatus
JPH02288326A (en) * 1989-04-28 1990-11-28 Dainippon Screen Mfg Co Ltd Apparatus for exposing periphery of wafer to light

Similar Documents

Publication Publication Date Title
JPS6173330A (en) Equipment for manufacturing semiconductor device
JPS5892221A (en) Semiconductor substrate exposure device
JPS58139144A (en) Matching exposure device
JPS62142321A (en) Wafer treatment device
JPS58159535A (en) Coater for photosensitive resin
JPS61226750A (en) Manufacture of semiconductor device
JPH08335545A (en) Exposing method and apparatus
JPH02288221A (en) Peripheral exposure device for semiconductor substrate
JPH02284415A (en) Device for removing resist on periphery of semiconductor wafer
JP2610601B2 (en) Wafer periphery exposure system
JPH069487Y2 (en) Wafer edge exposure equipment
JPS62128121A (en) Manufacture of semiconductor device
JPS6179227A (en) Pattern forming method using photo resist
JPH01125828A (en) Resist development device
KR19990031795A (en) Exposure apparatus and exposure method using the same
JPH0697066A (en) Photomask for manufacturing semiconductor device
JPS63234530A (en) Resist periphery removing device
JPH064576Y2 (en) Wafer edge exposure system
JPH01286311A (en) Resist hardening device by far ultraviolet rays
JPH05144726A (en) Exposing device for unnecessary resist on wafer
JPH01134917A (en) Pattern forming method
JPH0462553A (en) Photomask
JPH05224395A (en) Resist coating device
JPS59208835A (en) Contact exposure method
JPS5994417A (en) Aligner for mask