JPS61226750A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61226750A
JPS61226750A JP60066924A JP6692485A JPS61226750A JP S61226750 A JPS61226750 A JP S61226750A JP 60066924 A JP60066924 A JP 60066924A JP 6692485 A JP6692485 A JP 6692485A JP S61226750 A JPS61226750 A JP S61226750A
Authority
JP
Japan
Prior art keywords
resist
wafer
semiconductor substrate
yield
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60066924A
Other languages
Japanese (ja)
Inventor
Hiroshi Ishitani
浩 石谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60066924A priority Critical patent/JPS61226750A/en
Publication of JPS61226750A publication Critical patent/JPS61226750A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20Exposure; Apparatus therefor

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To prevent occurrence of dust due to contact and to enhance yield by removing a resist around a wafer at the time of exposing the resist through a mask set above the wafer after coating the resist. CONSTITUTION:The semiconductor substrate wafer 11 is coated with the UV sensitive positive type resist 12 and the resist 12 is prebaked under prescribed conditions. The photomask 13 is set above the wafer 11 by using a projection reflective type exposure device, and the resist 12 is exposed. The mask 13 is formed so as to transmit UV rays and to cast them on the border of the wafer 11 at the time of exposure. The part of the resist 12 exposed to the UV rays is selectively and perfectly removed by immersing the wafer 11 in an alkaline developing soln. in a developing step, and washing it with pure water and drying it, thus permitting stable yield to be attained by eliminating the cause of yield deterioration that the resist 12 is peeled and dust occurs.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置の製造方法に係わシ、特に写真蝕刻
工程で、半導体基板(ウェハ)に塗布さnたレジストを
クエへ周辺部のみ選択的に除去し、ダストの低減化を行
なう方法に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular, in a photolithography process, only the peripheral portion of a resist coated on a semiconductor substrate (wafer) is selected. The present invention relates to a method for removing dust and reducing dust.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

一般に半導体基板周辺部のレジストは、搬送用キャリヤ
やエツチング装置等の搬送機構に当たり、ダストとなっ
て半導体基板に再付看し、歩留シ低下の原因となる0ウ
ェハ周辺部のレジスト除去方法の従来例として、第3図
のレジスト塗布装置、第4図の塗布工程図で説明する。
Generally, the resist on the periphery of the semiconductor substrate hits the transport mechanism such as a transport carrier or etching device, becomes dust, and is reattached to the semiconductor substrate, causing a decrease in yield. A conventional example will be explained with reference to a resist coating apparatus shown in FIG. 3 and a coating process diagram shown in FIG. 4.

第3図に示さnるように、半導体基板1を真空チャック
2に装着し、ノズル3よりレジストを塗布する◎7はレ
ジスト流量調整弁である。
As shown in FIG. 3, the semiconductor substrate 1 is mounted on the vacuum chuck 2, and resist is applied from the nozzle 3. ◎7 is a resist flow rate adjustment valve.

続いてモータ5が低速回転し、半導体基板10面上のレ
ジストを半導体基板面内に一様に分布させる。次にモー
タ5が低速回転しながら、半導体基板1の周辺部にレジ
スト溶解液が噴出するように位置させたノズル6から、
レジスト溶解液が噴出する。最後にモータ5が高速回転
し、遠心力でレジスト溶解液をとばし、レジスト塗布定
の膜厚にする。8は溶剤流量調整弁、9は半導体基板1
0回転装置を囲むカップ、10は駆動制御機構である0
第2図の塗布工程図は、牛導体基板ノの回転数と処理時
間の関係を示し、時間TIでレジスト塗布、時間T2で
低速回転及び半導体基板周辺部のレジスト溶解、時間T
Subsequently, the motor 5 rotates at a low speed to uniformly distribute the resist on the surface of the semiconductor substrate 10 within the surface of the semiconductor substrate. Next, while the motor 5 rotates at a low speed, a nozzle 6 is positioned so that the resist solution is spouted onto the periphery of the semiconductor substrate 1.
Resist solution sprays out. Finally, the motor 5 rotates at high speed, and the resist solution is blown away by centrifugal force, so that the resist is coated to a predetermined film thickness. 8 is a solvent flow rate adjustment valve, 9 is a semiconductor substrate 1
A cup surrounding the 0 rotation device, 10 is a drive control mechanism.
The coating process diagram in FIG. 2 shows the relationship between the number of rotations of the conductor substrate and the processing time, with resist coating at time TI, low speed rotation and resist melting around the semiconductor substrate at time T2, and time T.
.

で高速回転を表す。このようにして半導体基板周辺部の
レジストを除去してい九〇 しかしながら上記従来技術では、塗布工程にて半導体基
板1の周辺部のレジストを除去する方法のため、次のよ
うな問題点があった。第1の問題点は、真空チャック2
に装着した半導体基板1の周辺部に、回転させながらノ
ズル6から溶剤を噴出してレジストを溶解除去するため
、溶剤が回転している半導体基板1の周辺部に噴出さn
た後、カップ9に飛び散っ念溶剤が、半導体基板1の溶
解除去しない部分のレジスト部にはね返ってきて、レジ
ストを溶解しピンホールを発生させる。@20問題点は
、半導体基板1を装着する際に中心部に精度よく該基板
1を装着できないので、該基板1の周辺部のレジスト溶
解除去を行なう場合、ウニへ間及びロット関で溶解除去
面積が異なる。@3の問題点は、有機系の溶剤によるレ
ジスト除去のため、使用した有機溶剤は、回収して産業
廃棄物の専門の処理業者に依頼する必要がある。また真
空チャック2のq&1部から有機溶剤が浸入し、モータ
や電気的エネルギ一部より発火する恐nもある。
represents high-speed rotation. In this way, the resist on the periphery of the semiconductor substrate 1 is removed.90However, in the above-mentioned conventional technology, the method of removing the resist on the periphery of the semiconductor substrate 1 in the coating process had the following problems. . The first problem is that the vacuum chuck 2
In order to dissolve and remove the resist by spouting solvent from the nozzle 6 while rotating the semiconductor substrate 1 attached to the periphery of the semiconductor substrate 1, the solvent is spouted onto the periphery of the rotating semiconductor substrate 1.
After that, the solvent splashed into the cup 9 bounces back onto the resist portion of the semiconductor substrate 1 that is not dissolved and removed, thereby dissolving the resist and generating pinholes. @20 The problem is that when mounting the semiconductor substrate 1, it is not possible to mount the substrate 1 accurately in the center, so when dissolving and removing the resist around the periphery of the substrate 1, it is necessary to dissolve and remove the resist between the parts and between lots. The area is different. The problem with @3 is that the resist is removed using an organic solvent, so the used organic solvent needs to be collected and sent to a specialist industrial waste disposal company. Furthermore, there is a risk that organic solvent may enter from the q&1 portion of the vacuum chuck 2 and ignite from the motor or part of the electrical energy.

〔発明の目的〕[Purpose of the invention]

そこで本発明は、従来技術の問題点である溶剤の飛び散
りによるピンホールの発生防止と、レジストの除去面積
のばらつきを防止し、高精度にレジストを除去すること
によって半導体基板上の周辺部のレジストとキャリアや
エツチング装置等との接触によるダストを防止し、歩留
シを向上させることを目的とする。また本発明では、有
機系の溶剤を不使用として、産業廃棄物処理の問題や火
災等の安全性の同上も目的とする。
Therefore, the present invention prevents the occurrence of pinholes due to solvent scattering, which are the problems of the conventional technology, and prevents variations in the area of resist removal, and removes the resist with high precision. The purpose is to prevent dust from coming into contact with carriers, etching equipment, etc., and to improve yield. The present invention also aims to solve the problem of industrial waste disposal and safety such as fire by not using organic solvents.

〔発明の概要〕[Summary of the invention]

本発明は、半導体基板のマスク合わせを行なう際に、ホ
トマスクの透過部もしくは不透過部が半導体基板上の周
辺部のレジストの除去したい部分に一致するホトマスク
を使って、レジスト(ネガ型、/ジ型)の感光特性を利
用し、現像工程にて半導体基板上の周辺部のしIストヲ
溶解除去することを特徴とする。
In the present invention, when performing mask alignment on a semiconductor substrate, a photomask is used in which the transparent part or non-transparent part of the photomask corresponds to the part of the resist on the periphery of the semiconductor substrate that is to be removed. It is characterized in that the photosensitive properties of the semiconductor substrate are utilized to dissolve and remove the smear on the periphery of the semiconductor substrate in the development process.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照して本発明の一実施例を説明する。第1
図(−)の塗布工程図は、半導体基板11に紫外線用ポ
ジ型レジスト12を塗布して、所定の条件でプリベーク
を施こした状態を示す。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The coating process diagram in FIG.

次に@1図(b)に示さnる如く、反射投影型露光装置
を使用してウニ八11のマスク合わせを行なった後、露
光を行ない、レジスト12を感光させる。即ちこのマス
ク合わせ及び露光工程に使用しているホトマスク13は
、sl!2図にも示さnる如く半導体基板11とマスク
合わせを行なった時、半導体基板110周辺部に紫外線
が当たるように、紫外線透過の形状にしたホトマスクで
ある。第2図におい・て14はレジストの種類に応じて
、光を通したシ通さなかったりする部分、15は/fタ
ーン領域、16は合わせダーダットである。次に半導体
基板11の周辺部で紫外線に感光し九部分のレジストは
、次の現像工程でアルカリ系の現像液に浸漬した後、純
水洗浄及び乾燥することによって、Wc1図(C)の如
く半導体基板10周辺部のレジストの選択除去を完了す
るものである。
Next, as shown in FIG. 1(b), after the mask of the sea urchin 11 is aligned using a reflection projection type exposure apparatus, exposure is performed to expose the resist 12. That is, the photomask 13 used in this mask alignment and exposure process is sl! As shown in FIG. 2, the photomask is shaped to transmit ultraviolet rays so that when the mask is aligned with the semiconductor substrate 11, the periphery of the semiconductor substrate 110 is exposed to ultraviolet rays. In FIG. 2, 14 is a portion that may or may not allow light to pass through depending on the type of resist, 15 is an /f turn region, and 16 is a matching dot. Next, the resist at the periphery of the semiconductor substrate 11 exposed to ultraviolet rays is immersed in an alkaline developer in the next development process, washed with pure water, and dried, resulting in the resist being exposed to ultraviolet rays as shown in Figure Wc1 (C). This completes the selective removal of the resist around the semiconductor substrate 10.

なお本発明は上記実施例のみに限らnず、種々の応用が
可能である。例えば第2図の八ツチング部分14f:非
透過型にすnば、ネガ型レジストのレジスト除去用ホト
マスクとして使用でき、半導体基板の周辺部のレジスト
除去できる。
Note that the present invention is not limited to the above-mentioned embodiments, and can be applied in various ways. For example, if the eighting portion 14f in FIG. 2 is made of a non-transmissive type, it can be used as a photomask for removing a negative resist, and the resist from the peripheral portion of the semiconductor substrate can be removed.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く本発明によnば、従来技術のように半
導体基板に塗布したレジストに溶剤が飛び散り、ピンホ
ールが発生したシ、レジストの溶解除去面積のばらつき
による歩留シ低下等の問題を解決できる◎また本発明で
は、マスク合わせの工程と現像工程とを組み合わせて、
半導体基板上の周辺部のレジスト除去を行なうので、レ
ジストの溶解除去面積t−高精度に制御でき、溶剤は不
使用のため、火災や公害の問題も同時に解決できる。ま
た本発明の最大の目的である半導体基板周辺のレジスト
とキャリアやエツチング装置との接触により、レジスト
が剥がnダストが発生して歩留〕低下の原因となる問題
を解決でき、安定した歩留シを得ることができるもので
ある。
As explained above, according to the present invention, problems such as pinholes caused by solvent scattering on the resist coated on a semiconductor substrate and a decrease in yield due to variations in the area of the resist to be dissolved and removed, as in the prior art, can be avoided. ◎In the present invention, the mask alignment process and the development process are combined,
Since the resist is removed from the periphery of the semiconductor substrate, the area t of resist dissolution and removal can be controlled with high accuracy, and since no solvent is used, problems of fire and pollution can be solved at the same time. In addition, the main purpose of the present invention is to solve the problem of resist peeling off and generation of dust due to contact between the resist around the semiconductor substrate and the carrier or etching equipment, which causes a decrease in yield, thereby achieving stable yield. This is something that can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の工程説明図、第2図は同実
施例に用いるホトマスクの概略的構成図、@3図は従来
のレジスト除去装置の構成図、第4図は同装置を使用し
たレジスト除去シーケンス図である0 11・・・半導体基板、12・・・レジスト、13・・
・ホトマスク。 出願人代理人  弁理士 鈴 江 武 彦第1図 I Mt2図
Figure 1 is a process explanatory diagram of an embodiment of the present invention, Figure 2 is a schematic configuration diagram of a photomask used in the same embodiment, Figure 3 is a diagram of a conventional resist removal apparatus, and Figure 4 is the same apparatus. 0 11...semiconductor substrate, 12...resist, 13...
・Photomask. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure I Mt2

Claims (1)

【特許請求の範囲】[Claims] 半導体装置の写真蝕刻工程で、ウェハにレジストを塗布
後、マスク合わせによるレジストの感光で前記ウェハの
周辺のレジストを除去することを特徴とする半導体装置
の製造方法。
1. A method for manufacturing a semiconductor device, which comprises applying a resist to a wafer in a photolithography process for semiconductor devices, and then removing the resist around the wafer by exposing the resist to light through mask alignment.
JP60066924A 1985-03-30 1985-03-30 Manufacture of semiconductor device Pending JPS61226750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60066924A JPS61226750A (en) 1985-03-30 1985-03-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60066924A JPS61226750A (en) 1985-03-30 1985-03-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61226750A true JPS61226750A (en) 1986-10-08

Family

ID=13330012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60066924A Pending JPS61226750A (en) 1985-03-30 1985-03-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61226750A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6423539A (en) * 1987-07-20 1989-01-26 Matsushita Electronics Corp Cleaning of rear of semiconductor wafer
JPH0232526A (en) * 1988-07-22 1990-02-02 Mitsubishi Electric Corp Substrate periphery exposure device
US5362583A (en) * 1992-01-31 1994-11-08 Sharp Kabushiki Kaisha Reticle mask exposure method comprising blank to remove incomplete circuits

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6423539A (en) * 1987-07-20 1989-01-26 Matsushita Electronics Corp Cleaning of rear of semiconductor wafer
JPH0232526A (en) * 1988-07-22 1990-02-02 Mitsubishi Electric Corp Substrate periphery exposure device
US5362583A (en) * 1992-01-31 1994-11-08 Sharp Kabushiki Kaisha Reticle mask exposure method comprising blank to remove incomplete circuits

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