JPH0282517A - Pattern formation - Google Patents

Pattern formation

Info

Publication number
JPH0282517A
JPH0282517A JP63234017A JP23401788A JPH0282517A JP H0282517 A JPH0282517 A JP H0282517A JP 63234017 A JP63234017 A JP 63234017A JP 23401788 A JP23401788 A JP 23401788A JP H0282517 A JPH0282517 A JP H0282517A
Authority
JP
Japan
Prior art keywords
wafer
peripheral part
region
periphery
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63234017A
Other languages
Japanese (ja)
Inventor
Toshio Endo
遠藤 稔雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP63234017A priority Critical patent/JPH0282517A/en
Publication of JPH0282517A publication Critical patent/JPH0282517A/en
Pending legal-status Critical Current

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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To prevent the yield from being lowered owing to conductive foreign matter without reducing the number of removal from a water by changing a distance from the peripheral part of the wafer depending upon the position on the peripheral part of the wafer to selectively expose the peripheral part of the wafer. CONSTITUTION:A peripheral part of a wafer is exposed corresponding to a region without any pattern, the region including a region 16 which is formed by selectively exposing 3mm of the peripheral part of the wafer through a positive type photoresist. At the same time, a region which is a unexposed 13 due to a pawl 11 of a 1:1 reflection projecting exposure device, is exposed by controlling an exposure device 5 using an exposed location adjusting section 6 such that a distance from the wafer peripheral part is larger 0.5mm than the shape of the pawl 11 of the 1:1 reflection projecting exposure device. Thus, there is completely eliminated the region which is the unexposed portion of the negative type photoresist along the wafer peripheral part, and hence any conductive foreign matter an be prevented from occurring upon etching of a passivation film to keep the number of removal of a semiconductor device from the wafer to slight reduction.

Description

【発明の詳細な説明】 [産業上の利用分野1 本発明は、パターン形成方法に関するものである。特に
パターンを形成すべきウェハの全面にフォトレジストを
付したウェハの周辺部を選択的に露光するパターン形成
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a pattern forming method. In particular, the present invention relates to a pattern forming method that selectively exposes the periphery of a wafer on which a photoresist is applied over the entire surface of the wafer on which a pattern is to be formed.

[従来の技術1 従来の技術は特開昭61−79227の様にフォトレジ
ストを全面に付したウェハの周辺部3〜5mmを直径3
〜5mmの円形のUV光照射を行ない選択的に露光して
いた。
[Prior art 1] The conventional technology, as disclosed in Japanese Unexamined Patent Publication No. 79227/1983, is to remove a wafer with a diameter of 3 to 5 mm from the periphery of a wafer coated with photoresist on the entire surface.
Selective exposure was performed by irradiating UV light in a circular shape of ~5 mm.

[発明が解決しようとする課題) しかし、従来の技術は、固くてもろい樹脂を用いたポジ
タイプフォトレジストに対しての技術であり、ウェハの
周辺部を一様に全周露光するものであった。ウェハに付
したフォトレジストがポジタイプではなくネガタイプフ
ォトレジストの場合でさらにはウェハの周辺部の選択的
な露光を一様ではなくウェハの周辺部の位置によりウェ
ハの周辺部からの距離を変化させなければならない場合
では、適切な処理が不可能であった。それは、第3図に
示した様に、l:1反射投影型露光装置(たとえば、キ
ャノン製ミラープロジェクションアライナ−MPA−6
00FA)の場合、ウェハに付したフォトレジストに所
定のパターン形成を行なうための露光の時、焦点(FO
CUS)を合わすためにウェハな露光装置のウェハディ
スクの3本または4本有るツメ1に押えつける事を行な
っていた。第4図に3本ツメの場合のツメによる未露光
部13とウェハ1の位置関係を示した。このツメは光を
透過しない金属でできていて決して露光される事がなく
ネガタイプフォトレジストの場合は現象するとツメ11
が当る部分はネガタイプフォトレジストはなくなるわけ
である。この場合、工程がパッシベーション膜のフォト
エツチングとすると第5図の様にウェハの上に形成され
た半導体装置14のパターンの一部15の上のパッシベ
ーション膜をエツチングにより除去する事となり、この
エツチングによって、半導体装置14の導電配線パター
ンの下にある絶縁膜をもエツチングすることとなり、前
記導電配線パターンがウェハより剥離し、導電性異物が
発生する事になる。この発生した前記導電性異物がウェ
ハに付着すると、導電配線やゲート電極の短絡の原因と
なり半導体装置は不良となる。また、ウェハ上の突起物
となってフォトリソグラフィ工程においてフォトレジス
トの膜厚にむらを生じさせ正常なパターン形成を阻害し
パターン欠陥をもたらし歩留りの低下を引き起こす原因
となる。
[Problem to be solved by the invention] However, the conventional technology is a technology for positive type photoresists using hard and brittle resin, and does not uniformly expose the entire periphery of the wafer. Ta. If the photoresist applied to the wafer is not a positive type photoresist but a negative type photoresist, the selective exposure of the wafer's periphery must not be uniform but the distance from the wafer's periphery must be varied depending on the position of the wafer's periphery. In certain cases, appropriate treatment was not possible. As shown in FIG.
00FA), the focal point (FO
In order to align the wafer (CUS), the wafer was pressed against three or four claws 1 on the wafer disk of the wafer exposure device. FIG. 4 shows the positional relationship between the unexposed portion 13 and the wafer 1 due to the three claws. This claw is made of a metal that does not transmit light and is never exposed to light, and in the case of negative type photoresist, this phenomenon occurs.
This means that the negative type photoresist disappears in the areas where this occurs. In this case, if the process is photo-etching of the passivation film, the passivation film on a part 15 of the pattern of the semiconductor device 14 formed on the wafer will be removed by etching as shown in FIG. Then, the insulating film under the conductive wiring pattern of the semiconductor device 14 is also etched, and the conductive wiring pattern is peeled off from the wafer, resulting in generation of conductive foreign matter. If the generated conductive foreign matter adheres to the wafer, it will cause a short circuit between the conductive wiring and the gate electrode, resulting in a defective semiconductor device. In addition, they become protrusions on the wafer, causing unevenness in the thickness of the photoresist in the photolithography process, inhibiting normal pattern formation, causing pattern defects, and lowering yield.

また、前記ツメによる未露光部13の長さはウェハの周
辺端部から5〜6mmあり、従来の技術を使用してウェ
ハ周辺部を5〜6mm選択的に露光してフォトレジスト
を除去すると、特に4インチ(100mm)ウェハの場
合は半導体装置を形成できる領域が88mmから90m
mという事になり、ウェハ1枚の中に形成できる半導体
装置の数が大きく減少してしまいとても許囲できる値で
はなくなってしまう。
In addition, the length of the unexposed portion 13 due to the claw is 5 to 6 mm from the peripheral edge of the wafer, and if the photoresist is removed by selectively exposing the wafer peripheral part by 5 to 6 mm using conventional technology, In particular, in the case of 4-inch (100 mm) wafers, the area in which semiconductor devices can be formed is 88 mm to 90 m.
m, which greatly reduces the number of semiconductor devices that can be formed on one wafer and is no longer an acceptable value.

本発明はこのうような従来の技術の問題点を解決するも
ので、その目的は半導体装置のウェハからの取れ数を減
らさずに導電性異物による歩留り低下を防止する技術を
提供する事にある。
The present invention solves these problems in the conventional technology, and its purpose is to provide a technology that prevents a decrease in yield due to conductive foreign matter without reducing the number of semiconductor devices that can be removed from a wafer. .

[課題を解決するための手段] 本発明のパターン形成方法は、ウェハの周辺部の位置に
よりウェハの周辺部からの距離を変化させて、ウェハの
周辺部を選択的に露光する事により前述の問題点を解決
する。
[Means for Solving the Problems] The pattern forming method of the present invention accomplishes the above-described method by selectively exposing the wafer periphery by changing the distance from the wafer periphery depending on the position of the wafer periphery. Solve problems.

[実 施 例] 第1図は本発明の実施例の構成図である。第2図は本発
明の実施例のウェハ平面図である。
[Embodiment] FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a wafer plan view of an embodiment of the present invention.

回転しているウェハ1のファセット部3をファセット検
出部4で検出しその信号を受けたコントロール部9がウ
ェハ1の周辺部2の位置により露光部5を所定の周辺部
からの距離に露光部位置調整部6により移動させながら
ウェハ周辺部にUV光を照射しウェハに付されているネ
ガタイプフォトレジストを露光し現象後においても残る
ようにした。第2図に露光した領域16を示したように
、第5図の点線で示した従来の技術によるポジタイプフ
ォトレジストのウェハの周辺部3mmの選択的露光によ
り形成されたパターン形成のない領域に対応するように
ウェハの周辺部を露光すると同時にl:1反射投影型露
光装置のツメにより未露光部13となる領域を、露光部
5を露光部位置調整部6によりウェハ周辺部からの距離
が前記1:1反射投影型露光装置のツメの形状より0.
5mm大きくなる様にコントロールして露光した。この
ようにする事により、ウェハ周辺部のネガタイプフォト
レジストの未露光部となる領域は全くなくなり、その結
果としてパッシベーション膜のエツチング時における前
述の導電性異物の発生を全て防止する事ができた。また
、ウェハからの半導体装置の取れ数も微減少にとどめる
ことができた。
The facet portion 3 of the rotating wafer 1 is detected by the facet detection portion 4, and upon receiving the signal, the control portion 9 moves the exposure portion 5 to a predetermined distance from the peripheral portion depending on the position of the peripheral portion 2 of the wafer 1. UV light was irradiated to the periphery of the wafer while being moved by the position adjustment unit 6 to expose the negative type photoresist attached to the wafer so that it remained even after the phenomenon occurred. As shown in FIG. 2, the exposed area 16 is a pattern-free area formed by selective exposure of the peripheral 3 mm of the wafer of the positive type photoresist by the conventional technique shown by the dotted line in FIG. At the same time, the periphery of the wafer is exposed to light in a corresponding manner, and at the same time, the distance from the wafer periphery is adjusted by adjusting the exposure part 5 to the unexposed part 13 using the claw of the 1:1 reflection projection type exposure device. 0.0 from the shape of the claw of the 1:1 reflection projection exposure device.
Exposure was controlled to increase the size by 5 mm. By doing this, there is no unexposed area of the negative type photoresist at the periphery of the wafer, and as a result, it is possible to completely prevent the generation of the above-mentioned conductive foreign matter during etching of the passivation film. Furthermore, the number of semiconductor devices removed from the wafer could be kept to a slight decrease.

〔発明の効果J 以上述べたように本発明によれば、ウェハ周辺部の位置
によりウェハの周辺部からの距離を変化させてウェハの
周辺部を選択的に露光することにより、導電性異物の発
生を防止し1歩留りの低下はなくなり、さらに、半導体
装置の取れ数の減少も微少に抑えるという効果を有する
ものである。
[Effect of the Invention J As described above, according to the present invention, the distance from the wafer periphery is changed depending on the position of the wafer periphery, and the wafer periphery is selectively exposed to light, thereby removing conductive foreign particles. This has the effect of preventing this occurrence, eliminating any drop in yield, and minimizing the decrease in the number of semiconductor devices that can be produced.

本発明の効果は、前述のように明らかであるが、それは
ウェハの周辺部の選択的な露光を周辺部からの距離を一
様にして行なうのみでなく、必要な箇所には、露光する
距離を変化させて行なおうとするものであり、その方法
は、実施例のみ以外にも各種方法が考えられる。露光部
ではなくウェハを回転させながら回転軸を移動する方法
、2ヶ以上の露光部を有して所定の位置により使用する
露光部を選択する方法等であり、同様の効果を得られる
ものであろう、また、本発明の効果は、半導体装置のみ
ではなく、フォトエツチングを行なう物全てに応用でき
るものである。
The effects of the present invention are clear as described above, and it is possible to not only selectively expose the periphery of the wafer at a uniform distance from the periphery, but also to selectively expose the wafer at a uniform distance from the periphery. This is attempted to be carried out by changing the , and various methods other than those of the embodiments are conceivable. Similar effects can be obtained by methods such as moving the rotation axis while rotating the wafer rather than the exposure section, or having two or more exposure sections and selecting the exposure section to be used depending on a predetermined position. Moreover, the effects of the present invention can be applied not only to semiconductor devices but also to all devices that undergo photoetching.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例の構成図。 第2図は本発明の実施例のウェハ平面図。 第3図は1:1反射投影型露光装置のツメによる未露光
部とウェハの関係概要図。 第4図は1:1反射投影型露光装置のツメのウェハ内配
置例図。 第5図はウェハの周辺部の概要図。 1・・・ウェハ 2・・・周辺部 3・・・ファセット部 5 ・ 7 ・ 8 ・ 9 ・ 11  ・ 12 ・ l 3 ・ 14 ・ l 5 ・ l 6 ・ ファセント検出部 露光部 露光部位置調整部 UV光源 石英ファイバー コントロール部 ツメ ウェハチャック ツメによる未露光部 半導体装置 パッシベーション膜欠損部 露光領域 以 出願人 セイコーエプソン株式会社 代理人 弁理士 上 柳 雅 誉(他1名)第1図 俤41¥1 第2回 第3図 箋 図
FIG. 1 is a configuration diagram of an embodiment of the present invention. FIG. 2 is a plan view of a wafer according to an embodiment of the present invention. FIG. 3 is a schematic diagram of the relationship between the unexposed area and the wafer due to the claw of the 1:1 reflection projection type exposure apparatus. FIG. 4 is a diagram showing an example of the arrangement of claws in a wafer in a 1:1 reflection projection exposure apparatus. FIG. 5 is a schematic diagram of the periphery of the wafer. 1... Wafer 2... Peripheral part 3... Facet part 5, 7, 8, 9, 11, 12, l3, 14, l5, l6, facet detection part, exposure part, exposure part position adjustment part UV light source Quartz fiber control part claw Unexposed area by wafer chuck claw Defected part of semiconductor device passivation film Exposed area Applicant Seiko Epson Corporation Agent Patent attorney Masaharu Kamiyanagi (and 1 other person) Figure 1 ¥41¥1 No. 2nd class 3rd paper map

Claims (1)

【特許請求の範囲】[Claims] (1)パターンを形成すべきウェハの全面にフォトレジ
ストを付した前記ウェハの周辺部を選択的に露光するパ
ターン形成方法において、前記露光をウェハの周辺部の
位置によりウェハの周辺部からの距離を変化させて行な
う事を特徴とするパターン形成方法。
(1) In a pattern forming method that selectively exposes the periphery of a wafer on which a photoresist is applied to the entire surface of the wafer on which a pattern is to be formed, the exposure is performed at a distance from the wafer's periphery depending on the position of the wafer's periphery. A pattern forming method characterized in that the pattern formation method is performed by changing the .
JP63234017A 1988-09-19 1988-09-19 Pattern formation Pending JPH0282517A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63234017A JPH0282517A (en) 1988-09-19 1988-09-19 Pattern formation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63234017A JPH0282517A (en) 1988-09-19 1988-09-19 Pattern formation

Publications (1)

Publication Number Publication Date
JPH0282517A true JPH0282517A (en) 1990-03-23

Family

ID=16964252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63234017A Pending JPH0282517A (en) 1988-09-19 1988-09-19 Pattern formation

Country Status (1)

Country Link
JP (1) JPH0282517A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02114629A (en) * 1988-10-25 1990-04-26 Ushio Inc Peripheral exposure of wafer
JP2012089641A (en) * 2010-10-19 2012-05-10 Mitsubishi Electric Corp Manufacturing method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02114629A (en) * 1988-10-25 1990-04-26 Ushio Inc Peripheral exposure of wafer
JP2012089641A (en) * 2010-10-19 2012-05-10 Mitsubishi Electric Corp Manufacturing method of semiconductor device

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