JPS62128121A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62128121A
JPS62128121A JP26873385A JP26873385A JPS62128121A JP S62128121 A JPS62128121 A JP S62128121A JP 26873385 A JP26873385 A JP 26873385A JP 26873385 A JP26873385 A JP 26873385A JP S62128121 A JPS62128121 A JP S62128121A
Authority
JP
Japan
Prior art keywords
wafer
resist film
film pattern
stage
periphery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26873385A
Other languages
Japanese (ja)
Inventor
Kazumasa Shigematsu
重松 和政
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP26873385A priority Critical patent/JPS62128121A/en
Publication of JPS62128121A publication Critical patent/JPS62128121A/en
Pending legal-status Critical Current

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To decrease the amount of wastes and to improve the yield and the quality of products, by forming a resist film pattern such that no resist film is provided on the periphery of a wafer, and subjecting the wafer to various treatments such as etching or the like while protecting it with the resist film. CONSTITUTION:A wafer 10 is conveyed from a casette 11 to a loading stage 13. A light beam with a diameter of 10mm is applied along the periphery of the wafer arranged on the loading stage 13 while the stage 13 is being rotated, so that the peripheral region of the wafer with a width of about 10mm is exposed. The applied light beam is conducted through an optical fiber 16 from a light source 12L of a stepper 12. The wafer is then conveyed to an exposing stage 14 where it is exposed for the formation of a pattern by the stepper 12. The wafer is developed in the next state and thus is provided with a resist film pattern 20. According to this method, the resist film will not be peeled off if the periphery of the wafer is contacted with various devices and consequently possible wastes can be decreased.

Description

【発明の詳細な説明】 [概要] フォトプロセスにおいて、レジスト膜パターンを形成す
る際、半導体ウェハー周縁のレジスト膜を除去しておき
、そのレジスト膜パターンを保護膜にしてエツチング等
の処理をおこなう。そうすれば、処理中のゴミの発生が
少な(なる。
DETAILED DESCRIPTION OF THE INVENTION [Summary] In a photo process, when forming a resist film pattern, the resist film at the periphery of a semiconductor wafer is removed, and the resist film pattern is used as a protective film for etching or other processing. This will reduce the amount of waste generated during processing.

[産業上の利用分野] 本発明は半導体装置の製造方法に係り、特に、半導体ウ
ェハーのフォトプロセスに関する。
[Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a photo process for semiconductor wafers.

半導体装置のウェハープロセスには、微細パターンを写
真食刻法で形成する、所謂フォトプロセスがあり、この
フォトプロセスはICなどの半導体装置の品質や歩留に
致命的な影響をあたえる重要な工程である。
The wafer process for semiconductor devices includes the so-called photo process, in which fine patterns are formed using photolithography, and this photo process is an important process that has a fatal impact on the quality and yield of semiconductor devices such as ICs. be.

従って、フォトプロセスにおける塵埃やゴミの付着は出
来る限り避けなければならない。
Therefore, the adhesion of dust and dirt during the photo process must be avoided as much as possible.

[従来の技術と発明が解決しようとする問題点コ従前、
フォトプロセスは半導体ウェハー(以下、ウェハーと略
称する)の表面にレジスト膜を塗布し、その上に等倍の
フォトマスク(ウェハーと同等の大きさをもち、且つ、
等倍のパターンをもったマスク)を密着して露光し、ウ
ェハー全面にレジスト膜パターンを一括形成し、このレ
ジスト膜パターンを保護膜にして、ウェハーをエツチン
グなどの加工処理する方法が採られていた。
[Previously, the problems that conventional techniques and inventions try to solve
In the photo process, a resist film is applied to the surface of a semiconductor wafer (hereinafter abbreviated as wafer), and a photomask of the same size (having the same size as the wafer and
A method is used in which a resist film pattern is formed on the entire surface of the wafer at once by exposing the wafer to light (a mask with a pattern of the same size), and this resist film pattern is used as a protective film to process the wafer such as etching. Ta.

しかし、最近では、縮小投影露光装置(ステッパ)を用
い、レチクル(5〜10倍の拡大パターンをもったマス
ク)によって、ウェハーの位置を移動させながら、繰り
返してウェハー面のレジスト膜を露光する、所謂、ステ
ップアンドレピートによる縮小投影露光法が汎用されて
おり、このようにして作成したレジスト膜パターンを保
護膜にして、ウェハーを加工処理する方法が採られてい
る。
However, recently, a reduction projection exposure device (stepper) is used to repeatedly expose the resist film on the wafer surface while moving the wafer position with a reticle (a mask with a 5 to 10 times enlarged pattern). A so-called step-and-repeat reduction projection exposure method is widely used, and a method is adopted in which a resist film pattern created in this way is used as a protective film to process a wafer.

これは、縮小投影露光法の方が微細パターンを形成する
に適しており、また、光学系の進歩によって、このよう
な縮小投影露光法が可能になってきたからである。
This is because the reduction projection exposure method is more suitable for forming fine patterns, and advances in optical systems have made such reduction projection exposure methods possible.

一方、レジストは、従前はネガ型が主体であつたが、最
近では、縮小投影露光装置を使用する関係上、この装置
は一般にgラインやiラインの波長で露光するため、ま
た、ポジ型が高解像力が得られるために、微細パターン
形成に適したポジ型レジストが常用されている。
On the other hand, in the past, resists were mainly negative type, but recently, due to the use of reduction projection exposure equipment, which generally exposes at G-line and I-line wavelengths, positive type resists have been used. Positive resists are commonly used because of their high resolution and are suitable for forming fine patterns.

即ち、最近のフォトプロセスの主体は、縮小投影露光法
によってポジ型レジスト膜パターンを形成する方法とな
っているわけである。
That is, the mainstay of recent photoprocessing is a method of forming a positive resist film pattern by a reduction projection exposure method.

ところが、ポジ型レジストはノボラック型フェノール樹
脂が主流で、これは機械的に弱く、ハガレやクラックが
生じ易い欠点がある。特に、ポジ型レジストは露光部が
現像で溶解される性質のレジストであるから、パターン
ニングされないウェハーの周縁部(周縁部分はハンドリ
ングで傷つき易いため、殆ど素子が形成されない)は、
未露光のレジスト膜がそのまま残存することが多い。そ
うす′ると、その周縁部分の残存レジスト膜が、後工程
のエツチング処理の際に、処理装置へのウェハーの搬送
時の摩擦などによって擦られてゴミとなり、それがウェ
ハー面に付着して歩留や品質を低下する。
However, the mainstream of positive resists is novolac type phenolic resin, which is mechanically weak and has the disadvantage of being prone to peeling and cracking. In particular, since positive resists have exposed areas that are dissolved during development, the periphery of the wafer that is not patterned (the periphery is easily damaged during handling, so almost no elements are formed on it).
Unexposed resist films often remain as they are. Then, during the subsequent etching process, the remaining resist film on the periphery becomes rubbed by friction during transport of the wafer to the processing equipment and becomes dust, which adheres to the wafer surface. Decreases yield and quality.

第4図はそれを示した図で、同図(alおよび(blは
従来のポジ型レジスト膜パターンを形成したウェハーの
平面図と断面図で、1はウェハー、2はレジスト膜パタ
ーンである。なお、同図(b)の断面図は同図(alの
平面図のAA’断面を示している。図のように、ウェハ
ーの周縁部分までレジスト膜が被覆されていると、処理
装置に接触し易いウェハー周縁部Sのレジスト膜が剥れ
て、ゴミとなるものである。
FIG. 4 is a diagram showing this, where (al and (bl) are a plan view and a cross-sectional view of a wafer on which a conventional positive resist film pattern is formed, 1 is the wafer, and 2 is the resist film pattern. Note that the cross-sectional view in Figure (b) shows the AA' cross section of the plan view in Figure (al).As shown in the figure, if the resist film is coated to the peripheral edge of the wafer, it may come into contact with the processing equipment. The resist film on the wafer periphery S, which tends to peel off, becomes dust.

本発明は、このような歩留や品質に悪影響のあるゴミを
なくするための処理方法を提案するものである。
The present invention proposes a processing method for eliminating such dust that has an adverse effect on yield and quality.

[問題点を解決するための手段] その目的は、半導体ウェハーの周縁部のレジス1−膜を
除去したレジスト膜パターンを形成し、該レジスト膜パ
ターンを保護膜にして加工処理するようにした半導体装
置の製造方法によって解決される。
[Means for solving the problem] The purpose is to form a resist film pattern by removing the resist film at the peripheral edge of a semiconductor wafer, and to process a semiconductor using the resist film pattern as a protective film. The problem is solved by a method of manufacturing the device.

[作用コ 即ち、本発明は、半導体ウェハー周縁のレジスト膜を除
去し、且つ、中央部分にレジスト膜パターンを形成し、
そのレジスト膜パターンを保護膜にしてウェハー面の処
理を行なう。そうすれば、ゴミ発生は非常に減少する。
[In other words, the present invention removes the resist film at the periphery of the semiconductor wafer, and forms a resist film pattern in the central part,
The wafer surface is processed using the resist film pattern as a protective film. This will greatly reduce waste generation.

[実施例コ 以下、図面を参照して実施例によって詳細に説明する。[Example code] Hereinafter, embodiments will be described in detail with reference to the drawings.

第1図(alおよび(b)は本発明にがかるポジ型レジ
スト膜パターンを形成したウェハーの平面図と断面図と
を示しており、1はウェハー、20はレジスト膜パター
ンである。なお、同図(b)の断面図は同図(alの平
面図のBB’断面を示している。このように、ウェハー
周縁部のレジスト膜を除去したレジスト膜パターンを形
成しておくと、処理装置にウェハーの周縁部が接触して
も、レジスト膜のハガレがなくなり、ゴミの発生が減少
する。
FIGS. 1A and 1B show a plan view and a cross-sectional view of a wafer on which a positive resist film pattern according to the present invention is formed, where 1 is the wafer and 20 is the resist film pattern. The cross-sectional view in Figure (b) shows the BB' cross-section in the plan view of Figure (al).In this way, if a resist film pattern is formed with the resist film at the wafer peripheral area removed, it is possible to Even if the peripheral edges of the wafers come into contact, the resist film will not peel off and the generation of dust will be reduced.

第2図はその形成方法の一実施例を示し、本例は自動ス
テッパの概要図である。図において、1)゜1)’はウ
ェハー10 (レジスト膜を塗布したウェハー)を収容
したカセット、12はステッパ、13はロードステージ
、14は露光処理ステージ、15はアンロードステージ
で、ステッパには光源12L、レチクル12R2縮小レ
ンズ12Eが設けられている。且つ、ウェハー10は図
示していない搬送系、例えばエヤーシュートなどによっ
て自動的にステージ上を移動し、搬送される構造である
FIG. 2 shows an example of the method for forming the same, and this example is a schematic diagram of an automatic stepper. In the figure, 1)゜1)' is a cassette containing a wafer 10 (a wafer coated with a resist film), 12 is a stepper, 13 is a load stage, 14 is an exposure processing stage, 15 is an unload stage, and the stepper is A light source 12L, a reticle 12R2 and a reduction lens 12E are provided. Further, the wafer 10 is structured to be automatically moved and transported on a stage by a transport system (not shown), such as an air chute.

この装置によって、露光処理する際、従来はカセット1
)からウェハー10をロードステージエ3に搬送し、次
にステッパ12の下部の露光処理ステージ14に載せて
、処理ステージ14をXY方向に操作してステップアン
ドレピートで露光をおこない、終了すればアンロードス
テージ15を通じてカセット1)′に収納していた。
With this device, when performing exposure processing, conventionally the cassette 1
), the wafer 10 is transferred to the load stage 3, then placed on the exposure processing stage 14 at the bottom of the stepper 12, and the processing stage 14 is operated in the X and Y directions to perform exposure in a step-and-repeat manner. It was stored in a cassette 1)' through the load stage 15.

本発明にかかる形成方法は、それに加えて、カセット1
)からウェハー10をロードステージ13に搬送し、ロ
ードステージ13に載置した時、ウェハーの周縁部に径
10鰭φの光を照射して、ウェハー10を載せたロード
ステージ13を回転させる。そうすれば、ウェハーの周
縁部は幅10m程度の帯状に露光される。且つ、その照
射光はステッパ12の光源12Lから光ファイバ16に
よって導出させる。
In addition, the forming method according to the present invention provides that the cassette 1
), and when the wafer 10 is transferred to the load stage 13 and placed on the load stage 13, the peripheral edge of the wafer is irradiated with light having a diameter of 10 fins, and the load stage 13 on which the wafer 10 is placed is rotated. In this way, the peripheral edge of the wafer is exposed in a band shape with a width of about 10 m. Further, the irradiation light is led out from the light source 12L of the stepper 12 through the optical fiber 16.

このようにして、予め、ウェハー10の周縁部を露光し
ておき、次に、露光処理ステージ14に搬送し、ステッ
パ12によってパターン形成の露光をおこなう。しかる
後、次の現像工程を終了すると、第1図に示すレジスト
膜パターン20を形成したウェハーが得られる。
In this manner, the peripheral edge of the wafer 10 is exposed in advance, and then the wafer 10 is transported to the exposure processing stage 14 and exposed to form a pattern using the stepper 12. Thereafter, when the next development process is completed, a wafer on which a resist film pattern 20 shown in FIG. 1 is formed is obtained.

また、ウェハー1にレジスト膜パターン20を形成する
他の方法として、第3図に示しているように、ウェハー
10の周縁部にレジスト膜の溶剤を含有させたローラ1
7を載せて回転し、周縁部のレジスト膜を溶解除去する
方法を採ってもよい。そのように、周縁部のレジスト膜
を溶剤に溶かして除去する方法の自動化は、余り困難な
ものではない。
As another method for forming the resist film pattern 20 on the wafer 1, as shown in FIG.
7 may be placed and rotated to dissolve and remove the resist film at the peripheral edge. In this way, it is not very difficult to automate the method of removing the resist film at the peripheral edge by dissolving it in a solvent.

以上のようにして、ウェハー周縁のレジスト膜を除去し
たレジスト膜パターンを形成し、そのレジスト膜パター
ンを保護膜にして、ウェハーのエツチングなどの加工処
理を行えば、ゴミの発生が少なくなって、歩留や品質が
改善される。
If a resist film pattern is formed by removing the resist film at the periphery of the wafer as described above, and the resist film pattern is used as a protective film for processing such as etching the wafer, the generation of dust will be reduced. Yield and quality are improved.

[発明の効果コ 上記の説明から明らかなように、本発明による製造方法
によればICなど半導体装置の歩留・品質の向上に顕著
に役立つものである。
[Effects of the Invention] As is clear from the above description, the manufacturing method according to the present invention is significantly useful for improving the yield and quality of semiconductor devices such as ICs.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)および(b)は本発明にかかるレジスト膜
パターンを形成したウェハーの平面図と断面図、第2図
および第3図はその形成方法を示す図、第4図(a)お
よび(b)は従来のレジスト膜パターンを形成したウェ
ハーの平面図と断面図である。 図において、 1.10はウェハー、 2.20はレジスト膜パターン 1).1)’はカセット、 12はステッパ、13はロ
ードステージ、 14は露光処理ステージ、15はアン
ロードステージ、 12Lは光源、     12Rはレチクル、12Eは
縮小レンズ、 16は光ファイバ、   17はローラ、苓イとF3耳
l;かか3しジズトI4鉛マク−ηが5八゛しRケ幻\
−第1図 半ナゴθI+1=51・■ジzl−膜ハ07−シりがり
賊゛方シ芝台q図第 2 図 従来のしyスト1灸wター>t−万う次しにクエハー@
 4 図 第3図
FIGS. 1(a) and (b) are a plan view and a cross-sectional view of a wafer on which a resist film pattern according to the present invention is formed, FIGS. 2 and 3 are diagrams showing the method of forming the same, and FIG. 4(a) and (b) are a plan view and a cross-sectional view of a wafer on which a conventional resist film pattern is formed. In the figure, 1.10 is a wafer, 2.20 is a resist film pattern 1). 1)' is a cassette, 12 is a stepper, 13 is a load stage, 14 is an exposure processing stage, 15 is an unload stage, 12L is a light source, 12R is a reticle, 12E is a reduction lens, 16 is an optical fiber, 17 is a roller, I and F3 ear l; Kakashi 3 and jizut I4 lead mask-η is 58゛ and R ke illusion\
- Fig. 1 Half nago θI + 1 = 51 ・■ Zl - Membrane 07 - Shigari bandit ゛ Shiba stand q Fig. 2 @
4 Figure 3

Claims (3)

【特許請求の範囲】[Claims] (1)半導体ウェハーの周縁部のレジスト膜を除去した
レジスト膜パターンを形成し、該レジスト膜パターンを
保護膜にして加工処理するようにしたことを特徴とする
半導体装置の製造方法。
(1) A method for manufacturing a semiconductor device, characterized in that a resist film pattern is formed by removing the resist film at the peripheral edge of a semiconductor wafer, and the resist film pattern is used as a protective film for processing.
(2)上記半導体ウェハーに塗布したポジ型レジスト膜
の周縁部を露光し、現像して、該ポジ型レジスト膜を除
去するようにしたことを特徴とする特許請求の範囲第1
項記載の半導体装置の製造方法。
(2) The peripheral edge of the positive resist film coated on the semiconductor wafer is exposed and developed to remove the positive resist film.
A method for manufacturing a semiconductor device according to section 1.
(3)上記半導体ウェハーに塗布したポジ型レジスト膜
の周縁部をレジスト溶剤に溶解して、該ポジ型レジスト
膜を除去するようにしたことを特徴とする特許請求の範
囲第1項記載の半導体装置の製造方法。
(3) The semiconductor according to claim 1, wherein the peripheral edge of the positive resist film coated on the semiconductor wafer is dissolved in a resist solvent to remove the positive resist film. Method of manufacturing the device.
JP26873385A 1985-11-28 1985-11-28 Manufacture of semiconductor device Pending JPS62128121A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26873385A JPS62128121A (en) 1985-11-28 1985-11-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26873385A JPS62128121A (en) 1985-11-28 1985-11-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62128121A true JPS62128121A (en) 1987-06-10

Family

ID=17462589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26873385A Pending JPS62128121A (en) 1985-11-28 1985-11-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62128121A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01261821A (en) * 1988-04-13 1989-10-18 Nec Corp Reduction projection aligner
DE10050050A1 (en) * 2000-10-10 2002-04-25 Promos Technologies Inc Process for compensating for etching stress during etching of a semiconductor wafer comprises exposing a substrate bead from the edge of the wafer forming a pattern using photolacquer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892221A (en) * 1981-11-27 1983-06-01 Nec Kyushu Ltd Semiconductor substrate exposure device
JPS59138335A (en) * 1983-01-28 1984-08-08 Toshiba Corp Exposing device for resist on end portion of wafer
JPS59158520A (en) * 1983-02-28 1984-09-08 Toshiba Corp Irradiating device
JPS6060724A (en) * 1983-09-14 1985-04-08 Toshiba Corp Semiconductor exposing device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892221A (en) * 1981-11-27 1983-06-01 Nec Kyushu Ltd Semiconductor substrate exposure device
JPS59138335A (en) * 1983-01-28 1984-08-08 Toshiba Corp Exposing device for resist on end portion of wafer
JPS59158520A (en) * 1983-02-28 1984-09-08 Toshiba Corp Irradiating device
JPS6060724A (en) * 1983-09-14 1985-04-08 Toshiba Corp Semiconductor exposing device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01261821A (en) * 1988-04-13 1989-10-18 Nec Corp Reduction projection aligner
DE10050050A1 (en) * 2000-10-10 2002-04-25 Promos Technologies Inc Process for compensating for etching stress during etching of a semiconductor wafer comprises exposing a substrate bead from the edge of the wafer forming a pattern using photolacquer
DE10050050B4 (en) * 2000-10-10 2006-06-14 Promos Technologies, Inc. Method of reducing the stress effect when etching deep trenches

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