JPH0697066A - Photomask for manufacturing semiconductor device - Google Patents

Photomask for manufacturing semiconductor device

Info

Publication number
JPH0697066A
JPH0697066A JP24535292A JP24535292A JPH0697066A JP H0697066 A JPH0697066 A JP H0697066A JP 24535292 A JP24535292 A JP 24535292A JP 24535292 A JP24535292 A JP 24535292A JP H0697066 A JPH0697066 A JP H0697066A
Authority
JP
Japan
Prior art keywords
wafer
photomask
photoresist film
semiconductor device
peripheral portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24535292A
Other languages
Japanese (ja)
Inventor
Hisashi Shirahata
久 白畑
Takumi Fujimoto
卓巳 藤本
Hajime Tada
元 多田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP24535292A priority Critical patent/JPH0697066A/en
Publication of JPH0697066A publication Critical patent/JPH0697066A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To remove photoresist from the peripheral portion of a wafer for preventing photoresist from peeling-off and turning into suspended dust which may contaminate the wafer or equipment when fixing or conveying the wafer within equipment for giving a treatment to the wafer for semiconductor device. CONSTITUTION:A chip pattern 11 for semiconductor device is arranged for a portion corresponding to a central portion 3 of a wafer 1 of a light exposure photomask 10 of a photoresist film applied to the wafer 1, and a mark pattern 12 for mask matching is formed by pushing in the array. Also, a portion corresponding to a peripheral portion 4 of the wafer 1 is formed to an unpattern portion with a clear ground or a black ground, the photoresist film exposed to light by the photomask 10 is certainly removed from the peripheral portion 4 of the wafer 1 during development, and a possibility of peeling-off off of the resin of the photoresist as a result of the contact of a presser jig 30 to the peripheral portion 4 when fixing the wafer 1 within a treatment equipment can be completely eliminated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置を作り込むべ
きウエハに対し処理を施す際に用いるフォトレジストを
パターンニングするためのフォトマスクに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photomask for patterning a photoresist used when processing a wafer on which a semiconductor device is to be formed.

【0002】[0002]

【従来の技術】集積回路や個別素子等の半導体装置を製
造するためにそれ用のウエハに所定のパターンで不純物
のイオン注入や種々な膜のエッチング等の処理を施す際
には、周知のように必ずその前にウエハの表面にフォト
レジスト膜をまず塗布した後、処理用のパターンを指定
するフォトマスクを用いてそれを露光させかつ現像する
フォトプロセスを施すことにより、処理用のマスク膜と
してフォトレジスト膜を指定されたパターンに形成する
必要がある。
2. Description of the Related Art In order to manufacture a semiconductor device such as an integrated circuit or an individual element, it is well known to perform a process such as ion implantation of impurities and etching of various films on a wafer for use in a predetermined pattern. Before that, be sure to apply a photoresist film on the surface of the wafer first, and then perform a photo process of exposing and developing it using a photomask that specifies the pattern for processing, and as a mask film for processing It is necessary to form a photoresist film in a specified pattern.

【0003】このフォトレジスト膜には、ウエハに複数
個の半導体装置を作り込むためそのチップパターンが多
数並べて配列されるほか、露光時のウエハのマスク合わ
せのためいわゆるアラインメントマーク用のマークパタ
ーンが含められるのが通例であり、図2(a) はかかるパ
ターン配列の代表例を示すものである。通例のようにほ
ぼ円形のウエハ1は上下左右の向きを区別するための切
り欠きであるいわゆるオリフラ2を備え、その表面上の
フォトレジスト膜は方形のチップパターン11の連続的な
二次元配列の中の複数個,図の例ではウエハ1の周縁部
の2個をマークパターン12で置き換えたパターンに形成
される。図ではハッチングを付してごく簡略に示された
チップパターン11はもちろん複雑な内部パターンをも
ち、マークパターン12はT字状やM字状等のアラインメ
ントマークである。
In this photoresist film, a large number of chip patterns are arranged side by side in order to form a plurality of semiconductor devices on a wafer, and a mark pattern for a so-called alignment mark is included for mask alignment of the wafer during exposure. 2A is a typical example of such a pattern arrangement. As is customary, a substantially circular wafer 1 is provided with a so-called orientation flat 2 which is a notch for distinguishing the vertical and horizontal directions, and the photoresist film on the surface thereof has a continuous two-dimensional array of rectangular chip patterns 11. A plurality of them, in the example shown, two peripheral portions of the wafer 1 are formed into a pattern in which the mark patterns 12 are replaced. In the figure, the chip pattern 11 shown with hatching and a very simple shape has a complicated internal pattern, and the mark pattern 12 is a T-shaped or M-shaped alignment mark.

【0004】ウエハ1上のフォトレジスト膜を図2(a)
のようにパターンニングするには、図と全く同じパター
ンをもつフォトマスクを用いてそれを等倍露光し、ある
いは拡大されたチップまたはマークのパターンを備える
フォトマスクであるいわゆるレチクルを用いて、位置を
順次ずらせながらレチクルを切り換えて縮小露光した後
に、通例のように簡単な加熱処理を施した上で専用の現
像液に浸漬してフォトレジスト膜を現像することでよ
い。なお、フォトマスクやレチクルにはポジ形とネガ形
の双方が場合に応じて適宜に使い分けられる。
The photoresist film on the wafer 1 is shown in FIG.
In order to pattern as shown in the figure, a photomask having exactly the same pattern as that in the figure is used to expose it at the same size, or a so-called reticle which is a photomask having an enlarged chip or mark pattern is used. The reticle may be switched while performing sequential exposure, and reduction exposure may be performed, and then the photoresist film may be developed by performing a simple heat treatment as usual and then immersing it in a dedicated developer. Both positive and negative types of photomasks and reticles are appropriately used depending on the case.

【0005】[0005]

【発明が解決しようとする課題】ところが、図2(a) の
ようにフォトレジスト膜をパターンニングしたウエハ1
では、それを処理設備内に固定する際や設備への出入の
ため搬送する際にフォトレジスト膜の一部が剥離して浮
遊塵埃となり、ウエハ面や処理設備内部を汚染しやすい
問題がある。図2(b) の拡大図に示すようにウエハ1は
その周縁部で抑え治具30により設備内の処理台上に固定
されるが、治具の鋭い爪32が当たる個所のフォトレジス
ト膜の比較的軟らかい樹脂が剥離しやすい。ウエハ1の
搬送中にもその周縁のとくに角部が搬送治具と接触する
際の摩擦によりフォトレジスト膜が剥離しやすい。
However, a wafer 1 having a photoresist film patterned as shown in FIG. 2 (a) is used.
Then, there is a problem that a part of the photoresist film is peeled off to become floating dust when it is fixed in the processing facility or is transported to and from the facility, which easily contaminates the wafer surface and the inside of the processing facility. As shown in the enlarged view of FIG. 2 (b), the wafer 1 is fixed on the processing table in the equipment by the holding jig 30 at the peripheral portion thereof, but the photoresist film at the position where the sharp claw 32 of the jig hits Relatively soft resin is easy to peel off. Even during the transportation of the wafer 1, the photoresist film is likely to be peeled off due to the friction when the corners of the peripheral edge of the wafer 1 come into contact with the transportation jig.

【0006】剥離したフォトレジスト膜の浮遊塵埃はウ
エハ面に付着するともちろん欠陥となって製造歩留まり
を低下させ、あるいは処理設備の内壁に付着蓄積して真
空度低下を招くほか、イオン注入設備では高圧部に迷い
込んで加速電圧を低下させる等の問題を起こす。かかる
問題の原因はウエハ1の周縁部にフォトレジスト膜が付
いている点にあり、従来からフォトレジスト膜をスピン
コートで塗布した後に必ずいわゆるエッジリンスにより
周縁部から除去し、さらにバックリンスにより裏面側か
らも除去するようにしているが、それでもウエハ1の周
縁部からフォトレジスト膜を取り切るのは困難である。
The floating dust of the peeled photoresist film becomes a defect when it adheres to the wafer surface, which reduces the manufacturing yield, or adheres and accumulates on the inner wall of the processing equipment to reduce the vacuum degree. There is a problem such as getting lost in the part and lowering the acceleration voltage. The cause of such a problem is that the peripheral edge of the wafer 1 is provided with a photoresist film. Conventionally, after the photoresist film is applied by spin coating, it is always removed from the peripheral edge by so-called edge rinse, and further back rinsed by back rinse. Although it is also removed from the side, it is still difficult to remove the photoresist film from the peripheral portion of the wafer 1.

【0007】これは、エッジリンスがアセトン等の溶剤
をウエハ1の周縁部に注いで行なう原理のためフォトレ
ジスト膜の除去範囲を限定するのが元々困難なことに加
え、スピンコートされたフォトレジストがウエハ1の中
央部よりも周縁部に厚いめに付きやすいので、フォトレ
ジスト膜を周縁部から完全に除去している間にそれを必
要とする隣接範囲から洗い流されてしまうからである。
本発明はかかる問題を解決して、ウエハの周縁部からフ
ォトレジスト膜を確実に除去して樹脂の塵埃に起因する
トラブルを防止することを目的とする。
This is because it is originally difficult to limit the removal range of the photoresist film due to the principle that the edge rinse is performed by pouring a solvent such as acetone onto the peripheral portion of the wafer 1, and in addition, the spin-coated photoresist is used. Is more likely to be thicker on the peripheral portion than on the central portion of the wafer 1, so that the photoresist film is washed away from the adjacent area where it is needed while the photoresist film is completely removed from the peripheral portion.
An object of the present invention is to solve such a problem and to reliably remove the photoresist film from the peripheral portion of the wafer to prevent the trouble caused by the dust of the resin.

【0008】[0008]

【課題を解決するための手段】かかる目的は本発明によ
れば、フォトレジスト膜のパターンニング用のフォトマ
スクの半導体装置を並べて作り込むべきウエハの中央部
に対応する部分にそのチップパターンとウエハとのマス
ク合わせ用のマークパターンを設け、かつそのウエハの
周縁部に対応する部分は必ず非パターン部として置き、
ウエハ面に塗布されたフォトレジスト膜がフォトプロセ
スの間に周縁部から自動的に除去されるようにすること
により達成される。なお、フォトマスクの上述の非パタ
ーン部とすべき範囲はふつうウエハの少なくとも2mmの
幅の周縁部に対応する部分とする必要がある。また、本
発明は前述のレチクル形のフォトマスクにも原理上適用
が可能であるが、チップパターンがウエハに対する等倍
露光用サイズに形成されるフォトマスクに適用するのが
最適である。
According to the present invention, such an object is to provide a chip pattern and a wafer at a portion corresponding to a central portion of a wafer on which a semiconductor device of a photomask for patterning a photoresist film is to be formed side by side. A mark pattern for mask alignment with is provided, and the portion corresponding to the peripheral edge of the wafer is always placed as a non-patterned portion.
This is accomplished by allowing the photoresist film applied to the wafer surface to be automatically removed from the periphery during the photo process. Note that the above-mentioned non-patterned area of the photomask usually needs to be a portion corresponding to the peripheral portion of the wafer having a width of at least 2 mm. Further, the present invention can be applied in principle to the reticle-type photomask described above, but is most suitable for a photomask in which a chip pattern is formed in a size for equal-magnification exposure on a wafer.

【0009】本発明はもちろんポジとネガの双方の形の
フォトマスクに適用が可能であり、上述の非パターン部
はポジ形の場合は透明とされ、ネガ形の場合は不透明な
いし黒とされる。本発明のフォトマスクを用いてフォト
レジスト膜をパターンニングする際には、フォトマスク
と同じマークパターンを同じ位置にもつ基準ウエハをあ
らかじめ準備しておいて、露光装置にこの基準ウエハを
装荷した状態でフォトマスクをそのマークパターンと合
わせて固定した後に、このフォトマスクに対し各作業用
ウエハをマスク合わせするのがフォトレジスト膜を除去
すべきウエハの周縁部の幅を正確に管理する上で有利で
あり、これによってマスク合わせ作業も容易になる。な
お、この基準ウエハは特定の半導体装置の製造に用いる
すべてのフォトマスクに対して共通に1個だけ準備する
ことでよい。
The present invention can of course be applied to both positive and negative photomasks, and the above-mentioned non-patterned portion is transparent in the positive type and opaque or black in the negative type. . When patterning a photoresist film using the photomask of the present invention, a reference wafer having the same mark pattern as the photomask at the same position is prepared in advance, and the exposure apparatus is loaded with the reference wafer. After fixing the photomask with its mark pattern by using, the mask alignment of each work wafer to this photomask is advantageous in accurately controlling the width of the peripheral portion of the wafer from which the photoresist film should be removed. This also facilitates mask alignment work. It is sufficient to prepare only one reference wafer for all photomasks used for manufacturing a specific semiconductor device.

【0010】[0010]

【作用】前項の構成にいうように本発明は、フォトマス
クのウエハの中央部に対応する部分にウエハ内に作り込
むべき半導体装置のチップパターンを多数個並べて配列
するほか、この配列内にウエハのマスク合わせ用マーク
パターンも割り込ませて配設してしまい、これに応じて
フォトマスクのウエハの周縁部に対応する部分をすべて
非パターン部とすることにより、フォトプロセス中にこ
のフォトマスクにより露光させかつ現像したときフォト
レジスト膜がウエハの周縁部から完全かつ自動的に除去
されるようにしたものである。
According to the present invention as described in the above paragraph, in addition to arranging a large number of semiconductor device chip patterns to be formed in the wafer in a portion corresponding to the central portion of the wafer of the photomask, the wafer is arranged in this arrangement. Also, the mask alignment mark pattern of No. 1 is arranged so as to be interrupted, and accordingly, all the portions corresponding to the peripheral portion of the wafer of the photomask are made non-patterned, so that the photomask is exposed during the photoprocess. The photoresist film is completely and automatically removed from the peripheral portion of the wafer when it is developed and developed.

【0011】[0011]

【実施例】以下、図1を参照して本発明の実施例を説明
する。図1(a) は本発明のフォトマスクの上面図、図1
(b) はそれによりフォトレジスト膜をパターンニングし
たウエハの上面図、図1(c) はフォトマスクを露光装置
に固定する際に用いる基準ウエハの上面図、図1(d) は
図1(b) のウエハを処理設備の処理台上に抑え治具によ
り固定した状態を図2(b) と対比して示す要部の拡大上
面図である。なお、以下説明する実施例ではフォトマス
クは等倍露光用であってかつポジ形のフォトレジスト膜
用であるものとする。
Embodiments of the present invention will be described below with reference to FIG. FIG. 1 (a) is a top view of the photomask of the present invention, and FIG.
1 (b) is a top view of a wafer having a photoresist film patterned thereby, FIG. 1 (c) is a top view of a reference wafer used when fixing a photomask to an exposure apparatus, and FIG. 1 (d) is shown in FIG. FIG. 3 is an enlarged top view of essential parts showing a state in which the wafer of b) is fixed on a processing table of processing equipment by a holding jig in comparison with FIG. 2 (b). In the examples described below, the photomask is for equal-magnification exposure and for a positive photoresist film.

【0012】図1(a) のフォトマスク10は図に重ねて細
線で示されたウエハ1に塗布されたフォトレジスト膜の
露光用であり、半導体装置を製造するウエハプロセスに
際しそのフォトプロセス工程ごとにチップパターン11等
の内容が互いに異なるものが用いられる。フォトマスク
10はウエハ1が例えば 100mm径のとき 125mm角程度のサ
イズのもので、そのウエハ1の中央部3に対応する範囲
に数mm角の方形, 図の例では正方形の各半導体装置用の
チップパターン11が行列状に多数個二次元配列され、こ
の配列中に割り込んで図の例では2個のマークパターン
12ができるだけ互いに離れた位置に配置される。さらに
フォトマスク10のウエハ1の周縁部4に対応する環状部
分は、本発明では必ず非パターン部, この実施例では透
明な地とされる。この非パターン部ないしは周縁部4の
幅はふつうは最低でも2mm以上に設定して置くことが必
要である。
The photomask 10 shown in FIG. 1 (a) is for exposing a photoresist film applied to the wafer 1 shown by thin lines in the figure, and is used for each photoprocess step in a wafer process for manufacturing a semiconductor device. The chip patterns 11 and the like having different contents are used. Photo mask
When the wafer 1 has a diameter of 100 mm, for example, a size of about 125 mm square, a square of several mm square within the range corresponding to the central portion 3 of the wafer 1, and a square chip pattern for each semiconductor device in the illustrated example. A large number of 11 are arranged in a two-dimensional array, and two mark patterns are inserted in the array by interrupting this array.
The 12 are placed as far apart from each other as possible. Further, the annular portion of the photomask 10 corresponding to the peripheral portion 4 of the wafer 1 is always a non-patterned portion in the present invention, which is a transparent ground in this embodiment. It is usually necessary to set the width of the non-patterned portion or the peripheral portion 4 to at least 2 mm or more.

【0013】なお、マークパターン12は最初のフォトプ
ロセス用, ふつうはウエハ1を覆うプロセス酸化膜のエ
ッチング用のフォトマスク10では、前述のT字状やM字
状のアラインメントマークとしてウエハ面上の酸化膜に
マーキングを施すようにし、その後のフォトプロセス用
のフォトマスク10では、場合により若干異なるがこの最
初のマーキングをできるだけ保護するためフォトレジス
ト膜を残すようにこの実施例では一様な黒地パターンと
するのがよい。
In the photomask 10 for the first photo process, usually for etching the process oxide film covering the wafer 1, the mark pattern 12 is used as the above-mentioned T-shaped or M-shaped alignment mark on the wafer surface. In this embodiment, a uniform black background pattern is used so that the oxide film is marked, and the photomask 10 for the subsequent photo process uses a photoresist film to protect the first marking as much as possible, although the mask pattern 10 may be slightly different. It is good to say

【0014】このフォトマスク10によりウエハ1上のフ
ォトレジスト膜を露光かつ現像して図1(b) の状態とす
るが、この際のフォトマスク1の露光装置への取り付け
用に図1(c) の基準ウエハ20を準備して置くのが有利で
ある。この基準ウエハ20には作業用のウエハ1と全く同
じものを用い、それに例えば酸化膜を 0.5μm程度の膜
厚で付けた上で、望ましくは上述の最初のフォトプロセ
ス用のフォトマスクを用いるフォトエッチングをそれに
施すことにより、酸化膜から形成されたマークパターン
12を図示のように少なくとも備える基準ウエハ20とする
のがよい。この場合には酸化膜がマークパターン12のほ
かチップパターン11にも形成されるが、もちろんなんら
差し支えはない。
The photoresist film on the wafer 1 is exposed and developed by the photomask 10 to obtain the state shown in FIG. 1B. At this time, the photomask 1 is attached to the exposure apparatus as shown in FIG. It is advantageous to prepare and place the reference wafer 20 of The reference wafer 20 is exactly the same as the work wafer 1 and, for example, an oxide film having a film thickness of about 0.5 μm is attached to the reference wafer 20 and, preferably, a photomask using the photomask for the first photoprocess described above is used. A mark pattern formed from an oxide film by subjecting it to etching
The reference wafer 20 preferably comprises at least 12 as shown. In this case, an oxide film is formed not only on the mark pattern 12 but also on the chip pattern 11, but of course there is no problem.

【0015】図1(a) のフォトマスク10により作業用の
ウエハ1のフォトレジスト膜を露光するには、まず図1
(c) の基準ウエハ20を露光装置に装荷した状態でそのマ
ークパターン12に合わせてフォトマスク10を露光装置に
固定し、これ以降は作業用のウエハ1を露光装置に順次
に装荷して露光すればよいが、最初のフォトプロセスを
除く以降の工程ではウエハ1とフォトマスク10のマーク
パターン12が合致するようマスク合わせした上で露光す
る。このように基準ウエハ20を利用してフォトマスク10
を露光装置に取り付けることにより、マスク合わせ作業
を容易にするとともに、フォトレジスト膜が除去される
ウエハ1の周縁部4の幅を非常に正確に管理することが
できる。
To expose the photoresist film on the working wafer 1 by the photomask 10 shown in FIG.
In the state where the reference wafer 20 of (c) is loaded in the exposure apparatus, the photomask 10 is fixed to the exposure apparatus according to the mark pattern 12 thereof, and thereafter, the working wafers 1 are sequentially loaded in the exposure apparatus and exposed. However, in the subsequent steps except the first photo process, the wafer 1 and the photo mask 10 are mask-aligned so that the mark patterns 12 of the photo mask 10 match with each other, and then exposed. As described above, the photomask 10 is formed by using the reference wafer 20.
Is attached to the exposure apparatus, the mask alignment work can be facilitated, and the width of the peripheral portion 4 of the wafer 1 from which the photoresist film is removed can be controlled very accurately.

【0016】このようにウエハ1上のフォトレジスト膜
をフォトマスク10により露光させた上で現像を行なった
後は、図1(b) に示すようにウエハ1の中央部3にはチ
ップパターン11とマークパターン12のフォトレジスト膜
が形成され、かつ周縁部4のフォトレジスト膜はこの例
ではポジ形で露光時に感光するので現像の際に完全に除
去される。本発明のフォトマスク10を用いるフォトプロ
セスでは、このようにウエハ1の周縁部4からフォトレ
ジスト膜が確実に除去されるので、そのスピンコート後
にバックリンスを行なうのは望ましいが、従来のように
エッジリンスを行なう必要がなく、従ってそれに伴うト
ラブル発生を防止できる。
After the photoresist film on the wafer 1 has been exposed by the photomask 10 and developed as described above, the chip pattern 11 is formed on the central portion 3 of the wafer 1 as shown in FIG. 1 (b). A photoresist film of the mark pattern 12 is formed, and the photoresist film of the peripheral portion 4 is positive in this example and is exposed during exposure, so that it is completely removed during development. In the photoprocess using the photomask 10 of the present invention, the photoresist film is surely removed from the peripheral edge portion 4 of the wafer 1 in this manner. Therefore, it is desirable to perform back rinse after the spin coating. There is no need to perform edge rinse, and therefore troubles associated therewith can be prevented.

【0017】図1(b) のウエハ1を例えばイオン注入設
備のターゲットである処理台に装荷ないし固定する際、
図1(d) の要部拡大図に示すように抑え治具30の抑圧子
31をウエハ1の周縁部4に接触させて抑圧するが、本発
明のフォトマスク10を用いてフォトレジスト膜を露光現
像したウエハ1では周縁部4からフォトレジスト膜が確
実に除去されていて樹脂剥離のおそれがない。抑え治具
30が図2(b) のような爪32や周縁部4の全周を抑える環
状抑圧子を備える設備内でウエハ1を処理した結果でも
樹脂剥離に起因する浮遊塵埃の発生は非常に少ない。ま
た、ウエハ1の設備内の自動搬送中のフォトレジスト膜
の剥離も、本発明によりかなり減少させ得ることが認め
られている。
When loading or fixing the wafer 1 shown in FIG. 1 (b) on a processing table which is a target of ion implantation equipment, for example,
Suppressor of restraining jig 30 as shown in the enlarged view of the main part of FIG. 1 (d)
31 is brought into contact with the peripheral edge portion 4 of the wafer 1 to suppress it, but in the wafer 1 in which the photoresist film is exposed and developed using the photomask 10 of the present invention, the photoresist film is surely removed from the peripheral edge portion 4 and the resin There is no risk of peeling. Holding jig
Even when the wafer 1 is processed in a facility in which 30 is provided with a claw 32 and an annular suppressor that suppresses the entire circumference of the peripheral edge portion 4 as shown in FIG. 2B, the generation of floating dust due to resin peeling is very small. It is also recognized that the present invention can significantly reduce stripping of the photoresist film during automatic transfer of the wafer 1 in the facility.

【0018】なお、以上説明した実施例ではウエハ1に
塗布するフォトレジスト膜をポジ形としたが、ネガ形の
場合には図1(a) のフォトマスク10のウエハ1の周縁部
4に対応する環状部分を容易にわかるように不透明な例
えば黒地にすることでよい。また、実施例ではフォトマ
スク10を等倍露光用としたがそれが縮小露光用ないしレ
チクルの場合も本発明を適用可能である。このように本
発明は上述の実施例に限らず種々の態様で実施をするこ
とができる。
Although the photoresist film applied to the wafer 1 is a positive type in the embodiment described above, in the case of a negative type, it corresponds to the peripheral portion 4 of the wafer 1 of the photomask 10 of FIG. 1 (a). The annular portion to be formed may be opaque, for example, a black background so that it can be easily seen. Further, in the embodiment, the photomask 10 is used for equal-magnification exposure, but the present invention is also applicable when it is for reduction exposure or a reticle. As described above, the present invention is not limited to the above-described embodiments and can be implemented in various modes.

【0019】[0019]

【発明の効果】以上のとおり本発明のフォトマスクで
は、半導体装置を作り込むべきウエハの中央部に対応す
る部分に半導体装置のチップパターンを配列するととも
にマスク合わせ用のマークパターンを配列内に割り込ま
せて設け、かつウエハの周縁部に対応する部分を透明地
や黒地の非パターン部に形成することにより、ウエハ面
に塗布されたフォトレジスト膜をフォトプロセス中にウ
エハの周縁部から除去することができ、これによりウエ
ハを処理設備内に固定する際や設備への出入のため搬送
する際にフォトレジスト膜が剥離して浮遊塵埃となって
ウエハ面や処理設備内部を汚染する問題をほぼ根絶で
き、とくに集積回路装置の欠陥発生を防止して製造歩留
まりを向上する実効を上げることができる。
As described above, in the photomask of the present invention, the chip pattern of the semiconductor device is arranged in the portion corresponding to the central portion of the wafer in which the semiconductor device is to be formed, and the mark pattern for mask alignment is interrupted in the arrangement. By removing the photoresist film applied to the wafer surface from the peripheral portion of the wafer during the photo process, by forming the portion corresponding to the peripheral portion of the wafer on the transparent or black non-patterned portion. As a result, the problem of contaminating the wafer surface and the inside of the processing equipment is almost eliminated when the wafer is fixed in the processing equipment or is transferred to and from the equipment, and the photoresist film peels off and becomes floating dust. In particular, it is possible to prevent the occurrence of defects in the integrated circuit device and improve the manufacturing yield.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明によるフォトマスクの実施例とウエハと
を示し、同図(a) はこのフォトマスクの上面図、同図
(b) はそれによりフォトレジスト膜をパターンニングし
たウエハの上面図、同図(c) はフォトマスクを露光装置
に固定する際に用いる基準ウエハの上面図、同図(d) は
同図(b) のウエハを処理設備の処理台上に抑え治具によ
り固定した状態を示すその要部拡大上面図である。
FIG. 1 shows an embodiment of a photomask according to the present invention and a wafer. FIG. 1A is a top view of the photomask, FIG.
(b) is a top view of the wafer with the photoresist film patterned by it, (c) is a top view of the reference wafer used when fixing the photomask to the exposure apparatus, and (d) is the same figure ( FIG. 6 is an enlarged top view of the relevant part showing the state in which the wafer of b) is fixed on the processing table of the processing equipment by a holding jig.

【図2】従来のフォトマスクとその問題点の説明用で、
同図(a) は従来のフォトマスクによりフォトレジスト膜
をパターンニングしたウエハの上面図、同図(b) はこの
ウエハを抑え治具で固定した状態を示す要部拡大上面図
である。
FIG. 2 is for explaining a conventional photomask and its problems,
FIG. 1A is a top view of a wafer having a photoresist film patterned by a conventional photomask, and FIG. 1B is an enlarged top view of essential parts showing a state where the wafer is fixed by a holding jig.

【符号の説明】[Explanation of symbols]

1 ウエハ 3 ウエハの中央部 4 ウエハの周縁部 10 フォトマスク 11 フォトマスクのチップパターン 12 フォトマスクのマークパターン 20 フォトマスクの取り付け用基準ウエハ 1 wafer 3 central part of wafer 4 peripheral part of wafer 10 photomask 11 photomask chip pattern 12 photomask mark pattern 20 photomask reference wafer for attachment

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】半導体装置を作り込むべきウエハに対し処
理を施す際に用いるフォトレジストのパターンニング用
フォトマスクであって、半導体装置を並べて作り込むべ
きウエハの中央部に対応する部分に半導体装置用のチッ
プパターンとウエハとのマスク合わせ用のマークパター
ンを設け、ウエハの周縁部に対応する部分は非パターン
部に形成して置き、ウエハ面に塗布されたフォトレジス
ト膜がフォトプロセス中にウエハの周縁部から除去され
るようにしたことを特徴とする半導体装置製造用フォト
マスク。
1. A photomask for patterning a photoresist used when processing a wafer on which a semiconductor device is to be formed, the semiconductor device being provided on a portion corresponding to a central portion of the wafer on which the semiconductor devices are to be formed side by side. A mark pattern for mask alignment between the chip pattern for wafer and the wafer is provided, and the portion corresponding to the peripheral edge of the wafer is formed and placed in the non-patterned portion, and the photoresist film coated on the wafer surface is used during the photo process. A photomask for manufacturing a semiconductor device, wherein the photomask is removed from the peripheral portion of the photomask.
【請求項2】請求項1に記載のフォトマスクにおいて、
フォトマスク内の各チップパターンがウエハに対する等
倍露光用のサイズに形成されることを特徴とする半導体
装置製造用フォトマスク。
2. The photomask according to claim 1, wherein
A photomask for manufacturing a semiconductor device, wherein each chip pattern in the photomask is formed in a size for equal-magnification exposure on a wafer.
【請求項3】請求項1に記載のフォトマスクにおいて、
ウエハの少なくとも2mmの幅をもつ周縁部に対応するフ
ォトマスク部分が非パターン部に形成されることを特徴
とする半導体装置製造用フォトマスク。
3. The photomask according to claim 1, wherein
A photomask for manufacturing a semiconductor device, wherein a photomask portion corresponding to a peripheral portion having a width of at least 2 mm of a wafer is formed in a non-patterned portion.
JP24535292A 1992-09-16 1992-09-16 Photomask for manufacturing semiconductor device Pending JPH0697066A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24535292A JPH0697066A (en) 1992-09-16 1992-09-16 Photomask for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24535292A JPH0697066A (en) 1992-09-16 1992-09-16 Photomask for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPH0697066A true JPH0697066A (en) 1994-04-08

Family

ID=17132401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24535292A Pending JPH0697066A (en) 1992-09-16 1992-09-16 Photomask for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0697066A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002329677A (en) * 2001-04-27 2002-11-15 Semiconductor Energy Lab Co Ltd Doping system
JP2016009784A (en) * 2014-06-25 2016-01-18 昭和電工株式会社 Method of manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002329677A (en) * 2001-04-27 2002-11-15 Semiconductor Energy Lab Co Ltd Doping system
JP2016009784A (en) * 2014-06-25 2016-01-18 昭和電工株式会社 Method of manufacturing semiconductor device

Similar Documents

Publication Publication Date Title
US6210846B1 (en) Exposure during rework for enhanced resist removal
US6927172B2 (en) Process to suppress lithography at a wafer edge
US5885756A (en) Methods of patterning a semiconductor wafer having an active region and a peripheral region, and patterned wafers formed thereby
JPH0697066A (en) Photomask for manufacturing semiconductor device
JPH01260451A (en) Formation of dicing line
US6426168B1 (en) Method of inspecting photo masks
JPH03237459A (en) Exposing method for semiconductor wafer and reticule for step exposing
JPS6173330A (en) Equipment for manufacturing semiconductor device
JPS58105151A (en) Formation of photosensitive resin film
JPS6179227A (en) Pattern forming method using photo resist
US6730608B2 (en) Full image exposure of field with alignment marks
JPH07181686A (en) Forming method of resist pattern
JPH0462553A (en) Photomask
JPS62128121A (en) Manufacture of semiconductor device
JPH02284415A (en) Device for removing resist on periphery of semiconductor wafer
JPS6037461B2 (en) Pattern transfer mask
KR0168353B1 (en) Inspection method of non-pattern wafer
KR20000047051A (en) Method for forming fine pattern of semiconductor device
US6288411B1 (en) Defect collecting structures for photolithography
JPS6338231A (en) Forming method for resist mask
JPH01125828A (en) Resist development device
JPH03203312A (en) Contracted projection exposure device
JPH06188187A (en) Manufacture of semiconductor device
JPS6315249A (en) Manufacture of optical mask
JPH0637012A (en) Formation of pattern by wafer edge exposure