JP2002329677A - Doping system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of time-increase required for ashing due to difficult separation of resist on a periphery section of a substrate when conducting ion implantation with the resist as a mask. SOLUTION: A doping system has a shielding plate comprising a metal, a quartz, or the like provided in order to avoid ion implantation on the periphery section of the substrate. The shielding plate is arranged to cover the area especially with thicker resist in the periphery section of the substrate. In the ion doping system, except for special case, the ion accelerated by an electrical field is implanted onto the surface of the substrate approximately vertically even though with slight fluctuation. Therefore, the arrangement of the shielding plate avoids direct ion implantation onto the shaded periphery section of the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a doping apparatus which ionizes donor or acceptor impurities, accelerates them electrostatically, and implants them into a semiconductor.

[0002]

2. Description of the Related Art A MOS transistor is formed on a surface of a single crystal silicon wafer.
A technique for forming an element such as a transistor or a bipolar transistor and connecting the elements by wiring to manufacture an integrated circuit (LSI) having a predetermined function is known as a wafer process. In this wafer process, an ion implantation technique for forming an impurity region having a p-type or n-type conductivity in a predetermined region is no longer essential.

The ion implantation technique is known as a method of mass-separating ions of donor or acceptor impurities and implanting only selected ions into a semiconductor. The feature is that impurities can be implanted into a semiconductor at a predetermined depth at a predetermined concentration by controlling an acceleration voltage and an ion density.

On the other hand, the ion implantation technique applied in the manufacture of a liquid crystal display employs a method of increasing the size of an ion source and not intentionally performing mass separation in order to efficiently implant ions over the entire surface of a large area substrate. I have.

The main structure of the ion implantation apparatus is composed of an ion source, a processing chamber for holding a substrate and implanting ions, a vacuum exhaust means, a doping gas supply means, a load lock chamber, and the like. The ion source is composed of an extraction electrode system composed of a plasma source section and a plurality of electrodes, and a mass separation system for selecting an ion species is added as necessary. In order to generate a planar ion beam in response to an increase in the area of the substrate, a porous electrode or a mesh electrode is used as the extraction electrode, and a plasma source portion is provided correspondingly.

[0006] In the plasma source portion, a gas is dissociated by electric discharge to generate a plurality of ions having different mass numbers. For example, in the case of PH ₃ (phosphine), PH _x ⁺ , P ₂ H _x ⁺ ,
It is known that H _x ^{+ and the} like are generated. When mass separation is not performed, these ion species having different mass numbers are accelerated to 10 to 200 keV by the extraction electrode system and injected into the semiconductor. Since the energy of ions accelerated by an electric field is much larger than the bond energy of atoms in a semiconductor, it is known that the crystal structure or the bond itself is cut with the ion implantation, and that region becomes amorphous. Have been. Annealing after ion implantation is performed for the purpose of recrystallization.

[0007]

When a semiconductor is doped with a donor or acceptor impurity by an ion implantation method, ion implantation is performed on the entire surface of a semiconductor substrate or a substrate on which a semiconductor is formed. There are two cases in which ions are selectively implanted only in the ion implantation. When ions are implanted only in a predetermined region of the semiconductor, 10 to 2
It is necessary to provide a mask for shielding ions flying at an energy of 00 keV. As the mask, an insulating film such as silicon oxide or a metal film for forming a wiring can be used, but there is a method using a resist to more easily form a mask pattern. The resist is used in a lithography process of a semiconductor, and typically uses a novolak-based photosensitive resin material (photoresist) to apply,
Through a process such as exposure and baking, a pattern having a thickness of about 1 to 5 μm is formed and used as a mask.

[0008] The rise in the substrate temperature due to the ion implantation is caused by conversion of a part of the energy of the ions accelerated by the electric field into heat. It has been found that the rising temperature rises to about 200 ° C., depending on the ion implantation conditions. However, after all the photoresist is 100-150
Since it is fired only at a temperature of about ° C., it is deteriorated by being heated at a higher temperature with ion implantation.

Further, it has been found that the novolak resin reacts with phosphorus ions to break the crosslinked structure and form an altered layer on the surface. This altered layer is chemically stable, cannot be removed by a commonly used stripper, and requires a long ashing process, which is a problem in the ion implantation process.

Of course, the resist on the outer peripheral portion of the substrate can be removed by a technique called peripheral exposure. However, a resist having heat resistance enough to withstand ion implantation requires a light intensity required for exposure of about 100 mJ / cm ² , and only a material having low photosensitivity can be selected. As seen in the liquid crystal display manufacturing technology, it is not practical to remove the outer peripheral portion of the mother glass whose one side exceeds 1 m by exposing the resist by peripheral exposure, since the processing time per one sheet becomes long.

As another method, there is a method called peripheral cleaning, in which the resist on the outer peripheral portion is removed by a solvent before exposure of the resist. In this method, the treatment with the solvent increases the thickness of the resist edge remaining on the substrate, which makes it difficult to remove the resist after ion implantation.

The ashing process for removing the resist is generally performed at a stage where oxygen is plasma-decomposed to generate active oxygen atoms or ozone, and the main chain is cut by a reaction between the oxygen and the resist to reach a molecular size capable of evaporating. This is a reaction for sequentially separating from the substrate. Since the ashing processing time is determined by the region having the largest resist film thickness, there is a problem that the central portion of the substrate is exposed to useless plasma during that time and the surface is roughened.

In ashing, in addition to such plasma damage, mobile ions and metal ions in the resist are implanted, which causes a reduction in the yield of the device. Therefore, it is not preferable to expose the plasma to uselessly for a long time.

In any case, according to the prior art, there is no other way than to remove the resist on the outer peripheral portion of the substrate by using a peripheral exposure technique or a peripheral cleaning technique. Devices (also called coaters, developers, etc.) become complicated and have to be further enlarged.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a doping apparatus which makes it easy to remove a resist in a peripheral portion of a substrate.

[0016]

In order to solve the above-mentioned problems, a doping apparatus according to the present invention provides a shielding plate made of an insulating material such as metal or quartz so as to prevent ions from being implanted into a peripheral portion of a substrate. Is provided. The shielding plate is arranged so as to cover the peripheral portion of the substrate, particularly where the thickness of the resist is large. In the ion doping apparatus, ions accelerated by an electric field are incident on the surface of the substrate, which is arranged without special cases, at a substantially vertical angle with a slight fluctuation. Therefore, by disposing the shielding plate, ions are not directly incident on the outer peripheral portion of the substrate, which is shaded by the shielding plate.

The ions colliding with the end of the shielding plate are scattered there and enter the substrate surface obliquely. Therefore, the size of the shielding plate is provided at a position where the scattered ions do not enter the element formation region while covering the region where the resist film thickness is large on the outer peripheral portion of the substrate. Further, the shielding plate may be electrically grounded or may be floating.

The shielding plate may be formed integrally with a clamper for fixing the substrate to the stage. In this case, the portion of the claw that comes into direct contact with the substrate has a minimum area, and the shielding plate itself is separated from the substrate without coming into direct contact with the substrate to prevent the substrate from being contaminated.

By using the above-described structure, ions are not implanted into a region having a large resist film thickness formed on the outer peripheral portion of the substrate, so that the resist in that portion can be prevented from being deteriorated in quality. As a result, the ashing process for removing the resist after the ion implantation is completed in a short time, and the throughput can be improved. Due to the shortening of the ashing processing time, the central portion of the substrate from which the resist is removed relatively quickly is exposed to plasma for a short time, so that the surface can be prevented from being roughened. Further, by integrally forming the shielding plate and the clamper for fixing the substrate to the stage, the configuration of the apparatus is not complicated and the size is not increased.

The doping apparatus of the present invention is a semiconductor substrate (typically, a silicon wafer) for the purpose of manufacturing an LSI.
The present invention can be applied to ion implantation for a semiconductor film on a glass or quartz substrate such as a liquid crystal display device.

[0021]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 shows a doping apparatus according to the present invention. The main configuration of this doping apparatus comprises an ion source 101, a processing chamber 102, a load lock chamber 103, and a vacuum exhaust means 106. The processing chamber 102 is a place where a substrate is held and ions are implanted. The processing chamber 102 includes a substrate stage 104 and a shielding plate 105 also serving as a clamper. The pins 108 for moving the substrate up and down on the substrate stage are connected to the load lock chamber 10.
The substrate is transferred from the substrate stage 104 to the
Used when putting on. A mechanism for moving the shielding plate 105 up and down by the arm 107 in accordance with the loading / unloading of the substrate is provided.

As shown in FIG. 2A, the substrate is carried in by the transfer means 109 while the shield plate 105 is lifted from the substrate stage by the arm 107 as shown in FIG. At this time, the pins 108 protrude from the substrate stage 104, and the substrate 100 is placed thereon. afterwards,
As shown in FIG. 2B, the pin 108 is lowered,
As shown in (C), when the arm 107 is lowered, the shielding plate 105 also serving as a clamper fixes the substrate 100 on the substrate stage.

As shown in FIG. 3, the positional relationship between the substrate 100 fixed on the substrate stage 104 and the shielding plate 105 is such that the end of the shielding plate 105 is located inside the substrate 100. This covers the outer periphery of the substrate. The end is a position that does not affect ions incident on the element formation region 120.

In FIG. 1, as the exhaust means 106, a dry pump, a mechanical booster pump, a turbo molecular pump and the like are appropriately combined and used.

The ion source 101 includes a gas supply system 115 for supplying a gas containing a doping element (hereinafter referred to as a doping gas), and a discharge electrode 1 for forming a plasma.
16 are provided. Although the configuration of FIG. 1 shows a type of capacitively-coupled high-frequency discharge, a filament-type electrode may be used instead.

As the extraction electrode system, the extraction electrode 11 is used.
1. Acceleration electrode 112, suppression electrode 113, ground electrode 114
These electrodes are provided with a number of openings through which ions pass. The acceleration of the ions is performed by using the extraction electrode 111 to which the extraction voltage Vex is applied and the acceleration voltage Vex.
This is performed by the acceleration electrode 112 to which ac is applied, and the suppression electrode 1
At 13, the diverging ions are collected to increase the directionality of the ion flow. By applying 10 kV to the extraction voltage Vex and changing the acceleration voltage Vac, ions can be accelerated with energy of 50 to 100 keV.

The doping gas is PH ₃ , B ₂ H _6, etc., which is diluted with hydrogen or an inert gas to about 1 to 5%. For ^{_{PH 3, PH x +, P}} 2 H x +, H x + and is generated as ion species, the processing chamber in which the substrate is accelerated are established by the extraction electrode system these ions if no mass separation Drawn out. The ions are extracted almost linearly by the four electrodes as shown by arrows in FIG. 1 and are irradiated on the substrate.

The substrate 100 on which the resist mask pattern is formed is fixed on a substrate stage 104 by a shielding plate 105 having a clamper. The ion species accelerated by the extraction electrode system is incident on the substrate 100, but no ions are implanted into the outer peripheral portion of the substrate 100 which is shaded by the shielding plate 105. Thus, the resist on the outer peripheral portion of the substrate 100 is prevented from being deteriorated, and can be easily removed by ashing.

For the purpose of blocking ions, the shielding plate 1
05 may be formed of metal or an insulating material such as quartz. Further, it may be either in an electrically grounded state or in a floating state.

FIG. 4 is a diagram schematically illustrating this.
Resist 1 on substrate 100 shown in FIGS. 4A and 4B
In 31, the resist on the outer peripheral portion of the substrate is removed by the peripheral cleaning process, but the end portion of the resist 131 is thickened by the treatment with the chemical solution. As shown in FIG.
When ions are implanted in a state in which the film 130 and the resist mask 131 are formed on the mask 0, an altered layer 132 is formed on the surface of the mask 132 and in the vicinity thereof. However, no ions are implanted into the outer peripheral portion 140 of the substrate covered with the shielding plate, and no altered layer is formed. On the other hand, FIG. 4B shows a conventional case, in which the deteriorated layer 13
2 is formed, thereby forming a resist mask 131.
Removal is difficult.

FIG. 6 shows a configuration of a doping apparatus suitable for performing ion implantation on a large-area mother glass substrate as used in a liquid crystal display manufacturing process. The configuration of the ion source 601 is fixed, and emits a linear or rectangular ion beam 606. The movement of the substrate 603 disposed on the pins 605 of the transport means 604 causes the substrate 60
3 can be ion-implanted. However, also in this case, provision of the shielding plate 602 can prevent ions from being implanted into the outer peripheral portion of the substrate 603.

Injection of an impurity element into a semiconductor by such a doping apparatus is performed by using a single crystal silicon wafer or SO
Manufacturing process of integrated circuit using semiconductor substrate such as I-substrate, thin film transistor (TF) formed on glass substrate
T) can be applied to the manufacturing process.

FIG. 5 shows T using the doping apparatus of the present invention.
1 shows an example showing a manufacturing process of FT. First, FIG.
In (A), semiconductor films 702 and 703 separated in an island shape from the semiconductor film manufactured in Embodiment 2 are formed over a light-transmitting substrate 700 made of aluminoborosilicate glass or barium borosilicate glass. Also, the substrate 70
A first insulating film 701 having a thickness of 50 to 200 nm formed by combining one or a plurality of kinds selected from silicon nitride, silicon oxide, and silicon nitride oxide is formed between the semiconductor film 0 and the semiconductor film.

Thereafter, as shown in FIG. 5B, a second insulating film 704 is formed with a thickness of 80 nm. Second
The insulating film 704 is used as a gate insulating film and is formed by a plasma CVD method or a sputtering method. As the second insulating film 704, a silicon oxynitride film formed by adding O ₂ to SiH ₄ and N ₂ O can reduce the fixed charge density in the film, and is a preferable material for the gate insulating film. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and an insulating film such as a silicon oxide film or a tantalum oxide film may be used as a single layer or a stacked structure.

A first conductive film for forming a gate electrode is formed on the second insulating film 704. Although there is no limitation on the type of the first conductive film, a conductive material such as Al, Ta, Ti, W, and Mo, or an alloy thereof can be used. The gate electrode using such a material has a laminated structure of tantalum nitride or titanium nitride and W or Mo—W alloy, W and A
A laminated structure of l or Cu can be employed. A
When using l, Ti, S
A material added with 0.1 to 7% by weight of c, Nd, Si, Cu or the like is used. The first conductive film is formed with a thickness of 300 nm.

Thereafter, a resist mask 715 is formed to a thickness of 3 μm, and the first conductive film is etched by dry etching to form gate electrodes 705 and 706. Although not shown, a wiring connected to the gate electrode is also formed at the same time.

As shown in FIG. 5C, phosphorus ions are implanted by an ion implantation method (here, a method of implanting ions without mass separation) using the gate electrode as a mask while leaving the mask 715 as it is. . The ion implantation performed in this step is performed by using the mask 715 and the gate electrodes 705 and 70.
6 is used as a mask for the semiconductor films 702 and 703, and 1 × 10 ¹⁴ to 1 × 10 ¹⁵
implanted with phosphorus ions at a dose of / cm ² to form n-type semiconductor region 7.
07 and 708 are formed. Phosphorus ions are also implanted into the mask 715, and an altered layer is formed on the surface layer by a reaction with phosphorus. On the other hand, although not shown in the figure, the resist remaining at the end (outer peripheral portion) of the substrate 700 on which the semiconductor films 702 and 703 are formed can be formed by using a doping apparatus having the structure shown in FIG. Since the shielding plate blocks the implantation of phosphorus ions, no altered layer is formed in that region.

When the implantation of phosphorus ions is completed, the mask 71
5 is peeled off by ashing. Ashing is performed by oxygen plasma, and the resist can be removed by a treatment for 30 to 45 minutes. This processing time has been reduced to less than half since ashing processing for 90 minutes or more is required when a conventional doping apparatus is used.

Subsequently, as shown in FIG.
A mask 709 made of resist is formed on the conductor film 703,
Boron ions are implanted into the semiconductor film 702 and the dose is 1 ×
10 ¹⁴~ 1 × 10¹⁵/cm^TwoBut to invert the n-type
At a concentration of 1.5 to 3 times that of phosphorus.
You.

After the implantation of boron ions, the mask 709 is removed by ashing. Also in this case, the altered layer of the resist is not formed on the outer peripheral portion of the substrate due to the effect of the shielding plate of the doping device, and the resist can be easily stripped. Ashing is similarly performed by oxygen plasma, and the resist can be removed by a treatment for 30 to 45 minutes.

Thereafter, as shown in FIG. 5E, a third insulating film 711 made of a silicon oxynitride film or a silicon nitride film is formed to a thickness of 50 nm by a plasma CVD method.

Then, heat treatment is performed to recover the crystallinity and activate the n-type and p-type semiconductor regions. The heat treatment can be performed by a method such as an instantaneous heat anneal or a laser anneal other than the furnace anneal furnace.

The fourth insulating film 712 shown in FIG. 5F is formed using a silicon oxide film or silicon oxynitride. Alternatively, the surface may be planarized by using an organic insulating material such as polyimide or acrylic.

Next, a contact hole is formed from the surface of the fourth insulating film 712 to reach the impurity region of each semiconductor film, and a wiring is formed using Al, Ti, Ta or the like. In FIG. 5F, 713 and 714 are source lines or drain electrodes. Thus, an n-channel TFT and a p-channel TFT can be formed. Although each TFT is shown here as a single unit, these TFTs
Can be used to form a CMOS circuit, an NMOS circuit, and a PMOS circuit.

As described above with reference to FIG.
It is necessary to use a resist pattern as a mask in the ion implantation step in the manufacturing process of (1). When a large liquid crystal panel is manufactured, a rectangular mother glass having a side exceeding 5000 mm is used. In that case, the resist applied by the spinner becomes thick at the outer peripheral portion of the mother glass. When the deteriorated layer was formed in that part by the ion implantation step, peeling was difficult, but as described above,
The use of the doping apparatus of the present invention facilitates peeling by ashing. Further, the time required for ashing is reduced to half or less, and the productivity can be improved. Here, the TFT manufacturing process is described as an example, but the present invention can be applied to a semiconductor integrated circuit manufacturing process by a planar process.

[0047]

According to the present invention, by using the doping apparatus, the shield plate prevents the implantation of phosphorus ions, so that the altered layer is not formed in the region. Separation by ashing becomes easy, and the time required for ashing can be reduced to half or less, so that productivity can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a doping apparatus of the present invention.

FIG. 2 is a diagram illustrating an operation when a substrate is carried in the doping apparatus of the present invention.

FIG. 3 is a diagram illustrating a positional relationship between a shielding plate and a substrate on a substrate stage in the doping apparatus of the present invention.

FIG. 4 is a view for explaining the swelling of the resist on the outer peripheral portion of the substrate and the formation of the altered layer.

FIG. 5 illustrates a manufacturing process of a TFT.

FIG. 6 is a diagram illustrating a configuration of a doping apparatus of the present invention for processing a large-area substrate.

Continued on the front page F-term (reference) 2H096 AA25 HA30 JA04 5C034 CC07 5F110 AA16 BB01 CC02 DD02 DD13 DD14 DD15 EE01 EE02 EE03 EE04 EE14 FF01 FF02 FF04 FF28 FF30 HJ01 HJ04 HJ13 HJ23 NN04 NN03 NN04 NN04

Claims (4)

[Claims] 1. A doping apparatus for ionizing a doping element and implanting it into a semiconductor, comprising a shielding plate for shielding an outer peripheral portion of the semiconductor substrate from ion irradiation. 2. A doping apparatus for accelerating an ionized atom or molecule by an electric field and implanting the ionized atom or molecule into a semiconductor film formed on a substrate, wherein the shielding portion shields an outer peripheral portion of the substrate so that the ionized atom or molecule is not implanted. A doping device comprising a plate. 3. A stage for arranging a substrate, and a shielding plate for shielding an outer peripheral portion of the substrate from ions supplied from an ion source on the stage, wherein the stage faces the ion source. A doping device, which is provided. 4. The doping apparatus according to claim 1, further comprising a clamper for fixing a substrate to the shielding plate.