JP2002237588A - Method and apparatus for manufacturing power semiconductor device - Google Patents

Method and apparatus for manufacturing power semiconductor device

Info

Publication number
JP2002237588A
JP2002237588A JP2001031769A JP2001031769A JP2002237588A JP 2002237588 A JP2002237588 A JP 2002237588A JP 2001031769 A JP2001031769 A JP 2001031769A JP 2001031769 A JP2001031769 A JP 2001031769A JP 2002237588 A JP2002237588 A JP 2002237588A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
mask
back surface
pattern
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001031769A
Other languages
Japanese (ja)
Inventor
Hideki Imada
英樹 今田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2001031769A priority Critical patent/JP2002237588A/en
Publication of JP2002237588A publication Critical patent/JP2002237588A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Thyristors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method and an apparatus for manufacturing power semiconductor device, with which reduction of the number of steps for patterning both sides of a semiconductor substrate can be realized and cost reduction is realized. SOLUTION: The method comprises the steps of applying a resist on the front surface of the semiconductor substrate, holding the substrate at a prescribed position, aligning a first mask on the front surface of the substrate, exposing the front surface with the first mask and a projection lens, developing this to form a pattern and targets on the front surface, applying a resist on the rear surface of the semiconductor substrate, holding the substrate at a prescribed position, aligning a second mask on the rear surface by using the targets, exposing the rear surface by using the second mask and the projection lens, and developing the substrate to form a pattern on the rear surface.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、パワー半導体装置
の製造方法に係り、特に半導体基板の両面にパターンを
形成する方法に関する。
The present invention relates to a method of manufacturing a power semiconductor device, and more particularly to a method of forming a pattern on both surfaces of a semiconductor substrate.

【0002】[0002]

【従来の技術】大電流の制御に用いられているGTO
(Gate Turn−Off Thyristor)
等のパワー半導体は、例えば6インチの半導体基板両面
にパターンが形成され、1チップが構成されている。
2. Description of the Related Art GTO used for controlling a large current
(Gate Turn-Off Thyristor)
For example, a power semiconductor such as that described above has a pattern formed on both surfaces of a 6-inch semiconductor substrate to constitute one chip.

【0003】このような両面パターンを形成する際、図
3(a)に示すように、先ずウエーハ1表面に形成され
た酸化膜2"上にレジスト3"を塗布し、これをべークし
た後、さらに裏面にも同様に塗布する。これをオーブン
べークした後、図3(b)に示すように両面一括露光ア
ライナーを用いて、取り違い顕微鏡13により上下の各
マスクホルダー9'、9"に保持された上下マスク1
0'、10"の位置合わせを行い、ナンバリングテープ1
2によりウエーハに直接接触させることにより固定し、
両面を同時に露光する。これを現像処理し、べークした
後、両面エッチングを施し、図3(c)に示すように両
面に位置合わせのためのターゲット5'を作製する。そ
してこのターゲットに合わせて図3(d)、(e)に示
すように各々の面のパターン4"を形成している。
In forming such a double-sided pattern, as shown in FIG. 3A, first, a resist 3 "is applied on an oxide film 2" formed on the surface of a wafer 1 and baked. Thereafter, the coating is similarly applied to the back surface. After baking this, the upper and lower masks 1 held by the upper and lower mask holders 9 ′ and 9 ″ by the mistaken microscope 13 using a double-sided batch exposure aligner as shown in FIG.
0 ', 10 "alignment and numbering tape 1
Fixing by directly contacting the wafer with 2,
Expose both sides simultaneously. This is developed, baked, and then subjected to both-side etching to produce a target 5 'for alignment on both sides as shown in FIG. 3 (c). Then, a pattern 4 ″ on each surface is formed in accordance with the target as shown in FIGS. 3 (d) and 3 (e).

【0004】しかしながら、このターゲット形成工程に
おいては、ウエーハ1の表面にレジスト3"を塗布しベ
ーキングした後、これを搬送途中において裏返し、表面と
同様に、裏面にレジスト3"を塗布しベーキングするた
め、ウエーハ1の搬送時にレジストにキズ、汚れ等のダ
メージが発生する。また、ウエーハ1の反りやマスクの
ベントを制御することができないため、より精密さの要
求されるパターンの形成は、ターゲットの形成と同時に
行うことができず、工程数の削減によるコストダウンを
図ることが困難であった。
However, in this target forming step, a resist 3 "is applied to the surface of the wafer 1 and baked, and then turned upside down in the course of transport, and the resist 3" is applied and baked on the back surface in the same manner as the front surface. When the wafer 1 is transported, damage such as scratches and dirt occurs on the resist. Further, since the warpage of the wafer 1 and the venting of the mask cannot be controlled, a pattern requiring higher precision cannot be formed at the same time as the formation of the target, and the cost is reduced by reducing the number of steps. It was difficult.

【0005】[0005]

【発明が解決しようとする課題】この様に、従来のパワ
ー半導体の両面パターンを形成する方法において、工程
数を削減することができず、コストダウンを図ることが
困難であった。
As described above, in the conventional method for forming a double-sided pattern of a power semiconductor, the number of steps could not be reduced, and it was difficult to reduce the cost.

【0006】従って本発明は、このような従来の欠点を
取り除き、工程数を削減し、コストダウンを図ることが
可能となるパワー半導体装置の製造方法及びパワー半導
体装置の製造装置を提供することを目的とするものであ
る。
Accordingly, the present invention is to provide a power semiconductor device manufacturing method and a power semiconductor device manufacturing apparatus which can eliminate such conventional disadvantages, reduce the number of steps, and reduce costs. It is the purpose.

【0007】[0007]

【課題を解決するための手段】本発明のパワー半導体装
置の製造方法は、半導体基板表面にレジストを塗布する
工程と、前記半導体基板を所定位置に保持する工程と、
前記半導体基板表面において第1のマスクの位置合わせ
を行なう工程と、第1のマスクと投影レンズとを介し
て、前記半導体基板表面を露光する工程と、この露光さ
れた半導体基板表面を現像して前記半導体基板表面にパ
ターンとターゲットを形成する工程と、前記半導体基板
裏面にレジストを塗布する工程と、この半導体基板を裏
返した状態で所定位置に保持する工程と、前記ターゲッ
トを用いて、前記半導体基板裏面において第2のマスク
の位置合わせを行う工程と、この第2のマスクと投影レ
ンズとを介して前記半導体基板裏面を露光する工程と、
この露光された半導体基板裏面を現像して前記半導体基
板裏面にパターンを形成する工程とを具備することを特
徴とする。
According to the present invention, there is provided a method of manufacturing a power semiconductor device, comprising: applying a resist to a surface of a semiconductor substrate; holding the semiconductor substrate at a predetermined position;
A step of aligning a first mask on the surface of the semiconductor substrate, a step of exposing the surface of the semiconductor substrate via the first mask and a projection lens, and a step of developing the exposed surface of the semiconductor substrate. Forming a pattern and a target on the surface of the semiconductor substrate, applying a resist to the back surface of the semiconductor substrate, holding the semiconductor substrate upside down at a predetermined position, and using the target Aligning a second mask on the back surface of the substrate, exposing the back surface of the semiconductor substrate via the second mask and a projection lens,
Developing the exposed back surface of the semiconductor substrate to form a pattern on the back surface of the semiconductor substrate.

【0008】また本発明のパワー半導体装置の製造装置
は、半導体基板の裏面側に配置された素子パターンを転
写するためのマスクと、同じく前記半導体基板の裏面側
に配置された投影レンズと、前記半導体基板の表面に形
成されたターゲットをモニターするために前記半導体基
板の表面側に配置されたモニター手段と、このモニター
手段により前記半導体基板裏面のマスク合わせを行う手
段と、前記マスクと前記投影レンズを介して前記半導体
基板裏面を露光する手段とを具備することを特徴とす
る。
The power semiconductor device manufacturing apparatus according to the present invention includes a mask for transferring an element pattern disposed on the back side of the semiconductor substrate, a projection lens also disposed on the back side of the semiconductor substrate, Monitoring means arranged on the front side of the semiconductor substrate for monitoring a target formed on the surface of the semiconductor substrate; means for adjusting the mask on the back side of the semiconductor substrate by the monitoring means; the mask and the projection lens Means for exposing the back surface of the semiconductor substrate through the substrate.

【0009】[0009]

【発明の実施の形態】本発明の一実施形態について、図
1、2を参照して説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS.

【0010】図1(a)に示すように、先ずウエーハ1
表面を900℃のスチーム雰囲気中で処理し、酸化膜
2、2'を形成する。次いで図1(b)に示すように表
面の酸化膜2上にフォトレジスト3を塗布し、マスク合
わせ後、紫外線により露光、現像を行い、図1(c)に
示すようにパターン4を形成する。このとき、ターゲッ
ト5も同時に形成する。
[0010] As shown in FIG.
The surface is treated in a steam atmosphere at 900 ° C. to form oxide films 2 and 2 ′. Next, as shown in FIG. 1 (b), a photoresist 3 is applied on the oxide film 2 on the surface, and after mask alignment, exposure and development are performed with ultraviolet rays to form a pattern 4 as shown in FIG. 1 (c). . At this time, the target 5 is also formed at the same time.

【0011】次に、裏面の酸化膜2'上にフォトレジス
ト3'を塗布した後、図2の露光装置に示すように、ウ
エーハチャック6上にウエーハ1の裏面を上にして装着
する。ウエーハチャック6の一部はガラスにより形成さ
れており、ガラス部7の下部に設置されたCCD8を用
いて、表面のターゲット5によりマスクホルダー9によ
り保持されたマスク10の位置合わせを行う。そして
1:1の投影レンズ11を介して図1(d)に示すよう
に紫外線により露光し、現像することにより図1(e)
に示すように裏面のパターン4'を形成する。このよう
にして、表面、裏面に所定のパターニングを施し、パッ
ケージすることにより、パワー半導体装置が形成され
る。
Next, after a photoresist 3 'is applied on the oxide film 2' on the back surface, the wafer 1 is mounted on a wafer chuck 6 with the back surface facing upward, as shown in the exposure apparatus of FIG. A part of the wafer chuck 6 is formed of glass, and the position of the mask 10 held by the mask holder 9 by the target 5 on the surface is adjusted using the CCD 8 installed below the glass part 7. Then, as shown in FIG. 1D, exposure and development are performed through a 1: 1 projection lens 11 as shown in FIG.
A pattern 4 'on the back surface is formed as shown in FIG. In this manner, the power semiconductor device is formed by performing predetermined patterning on the front surface and the rear surface and packaging.

【0012】このような方法により、別途にターゲット
を作製するためのレジスト塗布、露光、現像の3工程を
削減することができ、コストダウンを図ることが可能と
なった。
According to such a method, three steps of resist coating, exposure, and development for separately producing a target can be reduced, and cost can be reduced.

【0013】また、1:1の投影レンズを介して露光す
る非接触のプロジェクション方式を用いているので、接
触による欠陥の発生を抑えることができる。さらに、モ
ニタリングにCCDを用いているので、自動化も可能で
ある。
Further, since a non-contact projection system in which light is exposed through a 1: 1 projection lens is used, occurrence of defects due to contact can be suppressed. Furthermore, since a CCD is used for monitoring, automation is also possible.

【0014】本実施形態においては、表面のターゲット
及びパターンを作製する際の露光装置については特に規
定していないが、裏面パターンと同じ装置を用いて作製
してもよい。また、CCDの代わりにスコープを用いて
マスク合わせを行ってもよい。
In this embodiment, an exposure apparatus for producing a target and a pattern on the front surface is not particularly specified, but it may be produced using the same apparatus as that for the back surface pattern. Further, mask alignment may be performed using a scope instead of the CCD.

【0015】[0015]

【発明の効果】本発明によれば、半導体基板両面のパタ
ーニングを行なう際の工程数を削減し、コストダウンを
図ることが可能となるパワー半導体装置の製造方法及び
パワー半導体装置の製造装置を提供することができる。
According to the present invention, there are provided a method of manufacturing a power semiconductor device and an apparatus for manufacturing a power semiconductor device, which can reduce the number of steps in patterning both surfaces of a semiconductor substrate and reduce the cost. can do.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の製造工程を示す図。FIG. 1 is a view showing a manufacturing process of the present invention.

【図2】本発明の露光装置を示す図。FIG. 2 is a view showing an exposure apparatus of the present invention.

【図3】従来の製造工程を示す図。FIG. 3 is a diagram showing a conventional manufacturing process.

【符号の説明】[Explanation of symbols]

1 ウエーハ 2、2'、2" 酸化膜 3、3'、3" フォトレジスト 4、4'、4" パターン 5、5' ターゲット 6 ウエーハチャック 7 ガラス部 8 CCD 9、9'、9" マスクホルダー 10、10'、10" マスク 11 投影レンズ 12 ナンバリングテープ 13 取り違い顕微鏡 DESCRIPTION OF SYMBOLS 1 Wafer 2, 2 ', 2 "oxide film 3, 3', 3" Photoresist 4, 4 ', 4 "Pattern 5, 5' Target 6 Wafer chuck 7 Glass part 8 CCD 9, 9 ', 9" Mask holder 10, 10 ', 10 "mask 11 Projection lens 12 Numbering tape 13 Mistake microscope

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板表面にレジストを塗布する工
程と、前記半導体基板を所定位置に保持する工程と、前
記半導体基板表面において第1のマスクの位置合わせを
行なう工程と、第1のマスクと投影レンズとを介して、
前記半導体基板表面を露光する工程と、この露光された
半導体基板表面を現像して前記半導体基板表面にパター
ンとターゲットを形成する工程と、前記半導体基板裏面
にレジストを塗布する工程と、この半導体基板を裏返し
た状態で所定位置に保持する工程と、前記ターゲットを
用いて、前記半導体基板裏面において第2のマスクの位
置合わせを行う工程と、この第2のマスクと投影レンズ
とを介して前記半導体基板裏面を露光する工程と、この
露光された半導体基板裏面を現像して前記半導体基板裏
面にパターンを形成する工程とを具備することを特徴と
するパワー半導体装置の製造方法。
A step of applying a resist to the surface of the semiconductor substrate; a step of holding the semiconductor substrate at a predetermined position; a step of aligning a first mask on the surface of the semiconductor substrate; Through the projection lens
Exposing the semiconductor substrate surface, developing the exposed semiconductor substrate surface to form a pattern and a target on the semiconductor substrate surface, applying a resist to the back surface of the semiconductor substrate, Holding the semiconductor substrate at a predetermined position in a state where the semiconductor substrate is turned over, positioning the second mask on the back surface of the semiconductor substrate using the target, and positioning the semiconductor via the second mask and the projection lens. A method for manufacturing a power semiconductor device, comprising: exposing a back surface of a substrate; and developing a pattern on the back surface of the semiconductor substrate by developing the exposed back surface of the semiconductor substrate.
【請求項2】 半導体基板の裏面側に配置された素子パ
ターンを転写するためのマスクと、同じく前記半導体基
板の裏面側に配置された投影レンズと、前記半導体基板
の表面に形成されたターゲットをモニターするために前
記半導体基板の表面側に配置されたモニター手段と、こ
のモニター手段により前記半導体基板裏面のマスク合わ
せを行う手段と、前記マスクと前記投影レンズを介して
前記半導体基板裏面を露光する手段とを具備することを
特徴とするパワー半導体装置の製造装置。
A mask for transferring an element pattern disposed on the back side of the semiconductor substrate, a projection lens also disposed on the back side of the semiconductor substrate, and a target formed on the front side of the semiconductor substrate. Monitoring means arranged on the front side of the semiconductor substrate for monitoring, means for adjusting the mask on the back surface of the semiconductor substrate by the monitoring means, and exposing the back surface of the semiconductor substrate via the mask and the projection lens Means for manufacturing a power semiconductor device, comprising:
JP2001031769A 2001-02-08 2001-02-08 Method and apparatus for manufacturing power semiconductor device Pending JP2002237588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001031769A JP2002237588A (en) 2001-02-08 2001-02-08 Method and apparatus for manufacturing power semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001031769A JP2002237588A (en) 2001-02-08 2001-02-08 Method and apparatus for manufacturing power semiconductor device

Publications (1)

Publication Number Publication Date
JP2002237588A true JP2002237588A (en) 2002-08-23

Family

ID=18895801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001031769A Pending JP2002237588A (en) 2001-02-08 2001-02-08 Method and apparatus for manufacturing power semiconductor device

Country Status (1)

Country Link
JP (1) JP2002237588A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7064807B2 (en) 2001-01-15 2006-06-20 Asml Netherlands B.V. Lithographic apparatus
US7113258B2 (en) 2001-01-15 2006-09-26 Asml Netherlands B.V. Lithographic apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7064807B2 (en) 2001-01-15 2006-06-20 Asml Netherlands B.V. Lithographic apparatus
US7084955B2 (en) 2001-01-15 2006-08-01 Asml Netherlands B.V. Lithographic apparatus
US7113258B2 (en) 2001-01-15 2006-09-26 Asml Netherlands B.V. Lithographic apparatus

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