JPH09298141A - Semiconductor manufacturing apparatus and method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a semiconductor product having a trench structure with use of an easily available low-cost ordinary wafer, without raising the ON-resistance, using an optical stepper for forming a pattern image of a reticle on the surface of the wafer. SOLUTION: A θ-stage 51d of a wafer stage 51 is rotated by a motor 53 clockwise by 45 deg.. A pattern image of a reticle 30 is projected on the surface of an ordinary wafer 50 rotated to a position shifted 45 deg. from a reference position to be a normal aligning position to the reticle 30 whereby the layout direction of the pattern image to the crystal orientation of the ordinary wafer 50 is optimized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing apparatus and a manufacturing method for projecting / exposing a pattern image formed on a reticle on a wafer surface, and more particularly to a silicon wafer surface of a pattern image having a trench structure. It is used in an optical exposure apparatus that performs upward patterning.

[0002]

2. Description of the Related Art Conventionally, in the field of manufacturing semiconductor products, one of the processes is to pattern a desired pattern image on a wafer surface by using a reduction projection type optical exposure apparatus (optical stepper). , Lithographic processes are known.

FIG. 5 shows an outline of a silicon wafer on which a desired pattern image is patterned. Generally, a silicon wafer (normal wafer) 100 used for manufacturing semiconductor products has a plane orientation of (10
At 0), the orientation flat 101 that specifies the crystal orientation direction is formed in the <110> direction.

Then, a normal wafer 1 having such specifications
00, a plurality of pattern images 102 are regularly arranged and patterned. By the way, in recent years, demands for miniaturization and high integration of semiconductor products are increasing, and demand for semiconductor products having a trench structure such as U-MOS or U-IGBT is increasing.

FIG. 6 schematically shows a trench structure in a U-MOS product. In the case of a U-MOS product, for example, an N type epitaxial layer 202, a base region 203 and a source region 204 are sequentially formed on an N ⁺ type substrate 201. Then, a trench 205 having a substantially U-shaped cross section is provided so as to penetrate the base region 203 and the source region 204 and reach the epitaxial layer 202.

When a semiconductor product having such a trench structure is manufactured using the normal wafer 100 having the above-mentioned specifications, the on-resistance in the low current region becomes a problem. That is, when patterning a pattern image of a semiconductor product having a trench structure on the surface of a silicon wafer, the on-resistance of the manufactured semiconductor product varies depending on the crystal orientation direction of the silicon wafer.

For example, as shown in FIG. 5, when a pattern image 102 of a U-MOS product having a trench structure is patterned on the surface of a normal wafer 100, the direction of the trench 205 with respect to the crystal orientation direction of the wafer 100 ( Due to the inadequacy of the arrow shown in the figure, the on-resistance R _ON of the U-MOS product (the sum of the resistance R _{201 of the} substrate 201, the resistance R 202 of the epitaxial layer ₂₀₂ , and the resistance R ₂₀₃ of the base region 203) increases. .

It is conventionally known that such an increase in on-resistance can be reduced by using a silicon wafer (custom-made wafer) having an orientation flat 101 formed in the <100> direction.

FIG. 7 shows a U-MOS having a trench structure.
1 is a schematic view of a custom-made wafer on which a pattern image of a product is patterned. That is, a custom-made wafer 300 used for manufacturing a semiconductor product having a trench structure.
Is, for example, the plane orientation is (100), and the orientation flat 301 that specifies the crystal orientation direction is <1.
00> direction.

Then, the custom-made wafer 3 having such specifications
00, a plurality of pattern images 102 are regularly arranged and patterned on the surface. In this case, the resistance R of the base region 203 is optimized by optimizing the direction of the trench 205 with respect to the crystal orientation direction of the wafer 300.
Reduction of ₂₀₃ (improvement of mobility), ON resistance R _ON
Can suppress the rise of.

FIG. 8 shows an outline of the change in electric conductivity of the U-MOS product in comparison between the case of a normal wafer and the case of a custom-made wafer. Here, the electric conductivity Y (s) is shown by the reciprocal of the on-resistance (1 / R _ON ).

As is clear from this figure, the U-MOS product (white circle in the figure) manufactured using the custom-made wafer 300 is the U manufactured using the normal wafer 100.
-The Y value is higher than that of the MOS product (black circle in the figure). The higher the value of Y, the lower the resistance, and the more excellent the characteristics are.

However, the custom-made wafer 30 described above is used.
0 is different from the normal wafer 100 and has a special specification, so that it is more expensive than the normal wafer 100, and there is a problem in that the price of semiconductor products rises.

[0014]

As described above, conventionally, the increase of the on-resistance of the semiconductor product having the trench structure can be reduced by using the custom-made wafer.
Since the custom-made wafers have special specifications, they are more expensive than normal wafers, and there is a problem that the price of semiconductor products rises.

Therefore, the present invention provides a semiconductor manufacturing apparatus and a manufacturing method capable of reducing the increase in the on-resistance of a semiconductor product having a trench structure without using a custom-made wafer and suppressing the soaring of the semiconductor product. It is an object.

[0016]

In order to achieve the above-mentioned object, in a semiconductor manufacturing apparatus of the present invention, in which a pattern image of a reticle is projected / exposed on an exposure surface of a semiconductor wafer, the semiconductor wafer Alternatively, a rotation mechanism for rotating at least one of the reticles at an arbitrary angle is provided so that the pattern image of the reticle can be arranged in an arbitrary crystal orientation direction of the semiconductor wafer.

In the semiconductor manufacturing apparatus of the present invention, a wafer stage on which a semiconductor wafer is mounted,
A reticle stage on which a reticle formed with a pattern image is projected, which is projected onto the exposure surface of a semiconductor wafer mounted on this wafer stage, and the semiconductor wafer is relative to the reticle with reference to a regular alignment position. It is composed of a rotating mechanism that rotates at an angle of 45 ° ± 0.5 °.

Further, in the semiconductor manufacturing method of the present invention, a semiconductor wafer having a plane orientation of (100) and an orientation flat direction <110> for identifying the crystal orientation direction thereof is properly aligned with a reticle. The pattern image of the semiconductor product having the trench structure formed on the reticle is projected on the exposure surface of the semiconductor wafer by rotating the semiconductor wafer at an angle of 45 ° ± 0.5 ° based on the position. .

Further, according to the semiconductor manufacturing method of the present invention, the orientation flat is formed on the exposed surface of the semiconductor wafer whose plane orientation is (100) and whose orientation flat direction is <110>. The pattern image of a semiconductor product having a U-MOS or U-IGBT cell pattern rotated at an angle of 45 ° ± 0.5 ° from the direction is projected.

According to the semiconductor manufacturing apparatus and the manufacturing method of the present invention, it becomes possible to optimize the arrangement direction of the pattern image with respect to the crystal orientation direction of the semiconductor wafer. As a result, it becomes possible to use an easily available and inexpensive ordinary wafer for manufacturing a semiconductor product having a trench structure.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a reduction projection type optical exposure apparatus (optical stepper) according to an embodiment of the present invention.

That is, the exposure light flux 11a from the light source 11
Is reflected by a mirror 21 and then a reticle (mask) 3 as a projection original plate by a condenser lens 22.
It is irradiated to 0. Then, the projection image from the reticle 30 is projected onto the wafer 50 via the projection lens (optical system) 41.

At this time, the projection lens 41 of the reticle 30
The side surface, that is, the entire pattern image formed on the pattern surface is reduced by the projection lens 41 at a predetermined magnification and projected onto the exposure surface of the wafer 50.

On the exposed surface of the wafer 50, a positive resist (for example,
OFPR8600AC) is applied, and this resist is exposed by the reduced pattern image projected through the projection lens 41.

In the case of this optical stepper, by moving the wafer 50 and changing its exposure position in order, a plurality of pattern images are regularly arranged on the wafer 50 to perform patterning (step and repeat). ).

The light source 11 is composed of an ultra-high pressure Hg lamp which emits light effective for exposing the photoresist coated on the exposed surface of the wafer 50, for example, g-line or i-line light.

The reticle 30 has, for example, a pattern image of a semiconductor product such as a U-MOS or U-IGBT having a trench structure on its pattern surface, and the reticle stage 31 fixed on the optical path of the light flux 11a. It is supposed to be mounted on top.

The wafer 50 has a plane orientation of (100),
It is the most general (eg, easily available and inexpensive) silicon wafer (normal wafer) in which an orientation flat that specifies the crystal orientation direction is formed in the <110> direction, and moves on the optical path of the light flux 11a. It is designed to be mounted on a wafer stage 51 which is provided as possible.

The wafer stage 51 includes, for example, an X-direction stage 51a, a Y-direction stage 51b, a Z-direction stage 51c, and a θ-direction stage (rotation mechanism) 51.
The normal wafer 50 is configured to be independently movable in each direction.

That is, while the in-focus state is maintained by the Z-direction stage 51c of the wafer stage 51, the position of the exposure surface of the normal wafer 50 is changed by the X-direction stage 51a and the Y-direction stage 51b. The projection of the pattern image on the normal wafer 50 by the repeat is repeatedly performed.

The normal wafer 50 mounted on the wafer stage 51 is rotated by the θ-direction stage 51d at an arbitrary angle, for example, 45 ° (CW direction) in the clockwise direction (CW direction) with reference to the regular alignment position with the reticle 30. ± 0.
It is possible to rotate at an angle of 5 °) or 30 ° (± 0.5 °).

The θ-direction stage 51d is configured to be rotationally driven by a motor 53, which is controlled based on the detected angle value from the sensor 52, for example.
The sensor 52 is, for example, the position of the orientation flat of the normal wafer 50 (or the θ-direction stage 5).
The position 1d) is mechanically or electrically detected.

FIG. 2 shows the exposure operation by the above-mentioned optical stepper. For example, normal wafer 5
For 0, first, in the previous step, a hexamethyldisilazane (HMDS) treatment is performed at a temperature of about 80 ° C. for about 30 seconds.

Then, about 1.5 by spin coating.
A positive resist is applied with a thickness of μm. The normal wafer 50 coated with the positive type resist is baked at a temperature of about 105 ° C. for about 90 seconds.

The baked normal wafer 50 is transferred to a pre-alignment section 61 of an optical stepper through a standby position (not shown). Then, from that position, it is carried by the loader 62 and mounted on the wafer stage 51.

Thereafter, the θ-direction stage 51d of the wafer stage 51 is rotated from the normal position in the CW direction by 45 ° ± 0.
The wafer is rotated to a position shifted by 5 °, and the fine alignment of the normal wafer 50 is performed by moving the θ-direction stage 51d.

As a result, the normal wafer 50 is, for example, the reticle 30 mounted on the reticle stage 31.
The position is shifted by 45 ° with respect to the regular alignment position of. In this state, the exposure process is performed for about 200 to 250 msec, and the pattern image 30 'of the reticle 30 is normally projected onto the exposure surface of the wafer 50. Then, a plurality of (here, five) pattern images 30 'are repeatedly patterned on the normal wafer 50 by step-and-repeat.

At this time, the pattern images 30 ′ are regularly arranged with a deviation of 45 ° with respect to the orientation flat 50 a of the normal wafer 50. Patterned normal wafer 50 of pattern image 30 '
Are transferred from the wafer stage 51 to the pre-alignment unit 61 by the unloader 63. Then, in the next step, with an alkaline developer, for example, 25 ° C.
The development process is performed at a temperature of about 30 seconds.

FIG. 3 shows an outline of the normal wafer 50 on which the pattern image 30 'is patterned.
That is, rotating the normal wafer 50 at an angle of 45 ° from the regular position means that the pattern image 30 is moved at a position displaced by 45 ° from the regular alignment position with respect to the reticle 30.
′ Is patterned, and as a result, each pattern image 30 ′ is arranged on the wafer 50 with a deviation of 45 ° with respect to the orientation flat 50 a provided in the <110> direction.

This is the same as patterning by arranging a plurality of pattern images 102 regularly on the surface of the custom-made wafer 300 having the orientation flat 301 formed in the <100> direction shown in FIG. Is.

Therefore, the arrangement direction (trench direction) of each pattern image 30 'with respect to the crystal orientation direction of the normal wafer 50 can be optimized. FIG. 4 is a schematic diagram showing changes in electrical conductivity of a semiconductor product having a trench structure.
FIG. 3 shows a comparison between a semiconductor product manufactured using a conventional custom-made wafer and a semiconductor product manufactured using the normal wafer of the present invention. Here, the electric conductivity Y
(S) is shown by the reciprocal of on-resistance (1 / R _ON ).

As is clear from this figure, in the case of a semiconductor product which is usually manufactured by using the wafer 50 (shown by ×
(Marked) and Y have almost the same values as in the case of a semiconductor product manufactured by using a custom-made wafer (marked by ○ in the figure). From this, it is understood that the resistance of the base region can be reduced (the mobility can be increased) even in the semiconductor product manufactured by using the normal wafer 50 without using the custom-made wafer, and the characteristics can be improved.

As described above, a semiconductor product having a trench structure can usually be manufactured using a wafer. That is, the pattern image of a semiconductor product having a trench structure is patterned while the wafer is normally rotated at an angle of 45 °. This allows
Since the pattern images are regularly arranged and patterned with respect to the orientation flats provided in the <110> direction by 45 °, the pattern images are usually arranged in the crystal orientation direction of the wafer. Will be able to optimize the direction of. Therefore, because of the special specifications, it is possible to obtain semiconductor products with low on-resistance and improved characteristics at low cost without using a custom-made wafer that is difficult to obtain and expensive compared to normal wafers. is there.

In the above-described embodiment of the present invention, the θ-direction stage of the wafer stage is moved so that each pattern image is patterned by being shifted by 45 ° with respect to the orientation flat. I explained the case that it is configured to rotate,
The present invention is not limited to this, and can be similarly performed when, for example, the reticle stage on which the reticle is mounted is configured to rotate.

Further, it is not limited to the case where the angle of the wafer is changed by rotating the θ-direction stage. For example, the wafer is rotated after the positive resist is applied, and the wafer is conveyed while maintaining the angle and mounted on the wafer stage. Alternatively, the wafer may be transported by rotating it at a standby position of the wafer after applying the positive resist or at a pre-alignment unit. In this case, all of them can be performed relatively easily by only changing a part of the transport system (without modifying the optical stepper).

The means for controlling the rotation of the wafer (rotation mechanism) is not limited to a combination of a motor and a sensor, and, for example, a robot lifts and rotates the wafer, or a wafer rotated by air is used as a stopper pin. Various methods can be applied, such as changing the angle by pressing.

It is also possible to make the angles of both the wafer and the reticle relatively rotate. Further, it is similarly applicable to various exposure apparatuses other than the reduction projection type optical exposure apparatus. Of course, various modifications can be made without departing from the scope of the present invention.

[0048]

As described above in detail, according to the present invention, the increase in the on-resistance of a semiconductor product having a trench structure can be reduced without using a custom-made wafer, and the semiconductor product can be prevented from rising sharply. A manufacturing apparatus and a manufacturing method can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an outline of a reduction projection type optical exposure apparatus (optical stepper) according to an embodiment of the present invention.

FIG. 2 is a schematic diagram similarly illustrating an exposure operation of an optical stepper.

FIG. 3 is a schematic view showing an example of patterning for a normal wafer.

FIG. 4 is a schematic view showing a change in electric conductivity of a semiconductor product having a trench structure, which is also manufactured using a normal wafer.

FIG. 5 is a view for explaining the conventional technology and its problems,
A schematic view of a normal wafer.

FIG. 6 is a schematic view of a main part of a semiconductor product having a trench structure, similarly showing a U-MOS product as an example.

FIG. 7 is a schematic view of a custom-made wafer.

FIG. 8 is a schematic diagram showing a change in electric conductivity of a semiconductor product.

[Explanation of symbols]

 11 ... Light source 21 ... Mirror 22 ... Condenser lens 30 ... Reticle 30 '... Pattern image 31 ... Reticle stage 41 ... Projection lens 50 ... Wafer 50a ... Orientation flat 51 ... Wafer stage 51a ... X direction stage 51b ... Y direction stage 51c ... Z-direction stage 51d ... θ-direction stage 52 ... Sensor 53 ... Motor

Claims (10)

[Claims] 1. A semiconductor manufacturing apparatus for projecting / exposing a pattern image of a reticle on an exposed surface of a semiconductor wafer, wherein a rotating mechanism for rotating at least one of the semiconductor wafer and the reticle at an arbitrary angle is provided. A semiconductor manufacturing apparatus characterized in that a pattern image of the reticle can be arranged in an arbitrary crystal orientation direction of a wafer. 2. The semiconductor manufacturing apparatus according to claim 1, wherein the rotating mechanism rotates a reticle stage on which the reticle is mounted. 3. The semiconductor manufacturing apparatus according to claim 1, wherein the rotating mechanism rotates a wafer stage on which the wafer is mounted. 4. The semiconductor manufacturing apparatus according to claim 1, wherein the rotation mechanism is provided in a part of a transfer system that transfers the semiconductor wafer to be mounted on the wafer stage. 5. A wafer stage on which a semiconductor wafer is mounted, a reticle stage on which a reticle having a pattern image formed thereon, which is projected onto the exposure surface of the semiconductor wafer mounted on the wafer stage, is mounted, A semiconductor manufacturing apparatus comprising: a rotating mechanism that rotates the semiconductor wafer with respect to a reticle at an angle of 45 ° ± 0.5 ° with reference to a regular alignment position. 6. The semiconductor wafer has a plane orientation of (10
The semiconductor manufacturing apparatus according to claim 5, wherein the orientation flat direction that specifies the crystal orientation direction is a silicon wafer of <110> in 0). 7. The semiconductor manufacturing apparatus according to claim 5, wherein the reticle is formed with a pattern image of a semiconductor product having a trench structure. 8. The semiconductor manufacturing apparatus according to claim 5, wherein the rotating mechanism is configured to rotate the wafer stage. 9. The plane orientation is (100), and the orientation flat direction that specifies the crystal orientation direction is <1.
The semiconductor wafer of 10> is rotated at an angle of 45 ° ± 0.5 ° with reference to the regular alignment position with the reticle, and the exposed surface of the semiconductor wafer has a trench structure formed in the reticle. A semiconductor manufacturing method characterized in that a pattern image of a semiconductor product is projected. 10. The plane orientation is (100), and the orientation flat direction that specifies the crystal orientation direction is <
On the exposed surface of the semiconductor wafer of 110>, 45 ° ± from the direction of the orientation flat.
U-MOS or U-I rotated by 0.5 °
A semiconductor manufacturing method characterized in that a pattern image of a semiconductor product having a GBT cell pattern is projected.